[gem5-dev] Change in gem5/gem5[master]: cpu: TrafficGen as BaseCPU
Tiago Mück has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18416 )
Change subject: cpu: TrafficGen as BaseCPU
..
cpu: TrafficGen as BaseCPU
TrafficGen has additional attributes to behave like a BaseCPU. Python
scripts that expect sim. objects derived from BaseCPU can now be used with
TrafficGen without additional modifications.
Change-Id: Iee848b2ba0ac1851c487b1003da9bd96253d291a
Signed-off-by: Tiago Muck
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18416
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/testers/traffic_gen/BaseTrafficGen.py
1 file changed, 37 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
index 7fd8b30..00fe087 100644
--- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2016, 2018 ARM Limited
+# Copyright (c) 2012, 2016, 2018, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -85,3 +85,39 @@
# Sources for Stream/Substream IDs to apply to requests
sids = VectorParam.Unsigned([], "StreamIDs to use")
ssids = VectorParam.Unsigned([], "SubstreamIDs to use")
+
+# These additional parameters allow TrafficGen to be used with scripts
+# that expect a BaseCPU
+cpu_id = Param.Int(-1, "CPU identifier")
+socket_id = Param.Unsigned(0, "Physical Socket identifier")
+numThreads = Param.Unsigned(1, "number of HW thread contexts")
+
+@classmethod
+def memory_mode(cls):
+return 'timing'
+
+@classmethod
+def require_caches(cls):
+return False
+
+def createThreads(self):
+pass
+
+def createInterruptController(self):
+pass
+
+def connectCachedPorts(self, bus):
+if hasattr(self, '_cached_ports') and (len(self._cached_ports) >
0):
+for p in self._cached_ports:
+exec('self.%s = bus.slave' % p)
+else:
+self.port = bus.slave
+
+def connectAllPorts(self, cached_bus, uncached_bus = None):
+self.connectCachedPorts(cached_bus)
+
+def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
+self.dcache = dc
+self.port = dc.cpu_side
+self._cached_ports = ['dcache.mem_side']
+self._uncached_ports = []
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18416
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iee848b2ba0ac1851c487b1003da9bd96253d291a
Gerrit-Change-Number: 18416
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Additional TrafficGen stats
Tiago Mück has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18418 )
Change subject: cpu: Additional TrafficGen stats
..
cpu: Additional TrafficGen stats
Additional stats to keep track of read/write latencies and throughput.
Change-Id: I7684cd33cf68fffdef4ca9c3a6db360a0f531c18
Signed-off-by: Tiago Muck
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18418
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
2 files changed, 85 insertions(+), 0 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/testers/traffic_gen/base.cc
b/src/cpu/testers/traffic_gen/base.cc
index f2385a4..154b1bd 100644
--- a/src/cpu/testers/traffic_gen/base.cc
+++ b/src/cpu/testers/traffic_gen/base.cc
@@ -354,6 +354,51 @@
retryTicks
.name(name() + ".retryTicks")
.desc("Time spent waiting due to back-pressure (ticks)");
+
+bytesRead
+.name(name() + ".bytesRead")
+.desc("Number of bytes read");
+
+bytesWritten
+.name(name() + ".bytesWritten")
+.desc("Number of bytes written");
+
+totalReadLatency
+.name(name() + ".totalReadLatency")
+.desc("Total latency of read requests");
+
+totalWriteLatency
+.name(name() + ".totalWriteLatency")
+.desc("Total latency of write requests");
+
+totalReads
+.name(name() + ".totalReads")
+.desc("Total num of reads");
+
+totalWrites
+.name(name() + ".totalWrites")
+.desc("Total num of writes");
+
+avgReadLatency
+.name(name() + ".avgReadLatency")
+.desc("Avg latency of read requests");
+avgReadLatency = totalReadLatency / totalReads;
+
+avgWriteLatency
+.name(name() + ".avgWriteLatency")
+.desc("Avg latency of write requests");
+avgWriteLatency = totalWriteLatency / totalWrites;
+
+readBW
+.name(name() + ".readBW")
+.desc("Read bandwidth in bytes/s");
+readBW = bytesRead / simSeconds;
+
+writeBW
+.name(name() + ".writeBW")
+.desc("Write bandwidth in bytes/s");
+writeBW = bytesWritten / simSeconds;
+
}
std::shared_ptr
@@ -470,6 +515,16 @@
assert(iter->second <= curTick());
+if (pkt->isWrite()) {
+++totalWrites;
+bytesWritten += pkt->req->getSize();
+totalWriteLatency += curTick() - iter->second;
+} else {
+++totalReads;
+bytesRead += pkt->req->getSize();
+totalReadLatency += curTick() - iter->second;
+}
+
waitingResp.erase(iter);
delete pkt;
diff --git a/src/cpu/testers/traffic_gen/base.hh
b/src/cpu/testers/traffic_gen/base.hh
index 5ffe508..985ab5d 100644
--- a/src/cpu/testers/traffic_gen/base.hh
+++ b/src/cpu/testers/traffic_gen/base.hh
@@ -206,6 +206,36 @@
/** Reqs waiting for response **/
std::unordered_map waitingResp;
+/** Count the number of bytes read. */
+Stats::Scalar bytesRead;
+
+/** Count the number of bytes written. */
+Stats::Scalar bytesWritten;
+
+/** Total num of ticks read reqs took to complete */
+Stats::Scalar totalReadLatency;
+
+/** Total num of ticks write reqs took to complete */
+Stats::Scalar totalWriteLatency;
+
+/** Count the number reads. */
+Stats::Scalar totalReads;
+
+/** Count the number writes. */
+Stats::Scalar totalWrites;
+
+/** Avg num of ticks each read req took to complete */
+Stats::Formula avgReadLatency;
+
+/** Avg num of ticks each write reqs took to complete */
+Stats::Formula avgWriteLatency;
+
+/** Read bandwidth in bytes/s */
+Stats::Formula readBW;
+
+/** Write bandwidth in bytes/s */
+Stats::Formula writeBW;
+
public:
BaseTrafficGen(const BaseTrafficGenParams* p);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18418
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I7684cd33cf68fffdef4ca9c3a6db360a0f531c18
Gerrit-Change-Number: 18418
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Limit TrafficGen outstanding reqs
Tiago Mück has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18417 )
Change subject: cpu: Limit TrafficGen outstanding reqs
..
cpu: Limit TrafficGen outstanding reqs
Parameter to limit the number of requests waiting for a response.
Change-Id: I6cf9e8782a06ae978fb66f7c4278f4c9e9980c79
Signed-off-by: Tiago Muck
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18417
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/testers/traffic_gen/BaseTrafficGen.py
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
3 files changed, 71 insertions(+), 10 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
index 00fe087..5980bfd 100644
--- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
@@ -72,6 +72,11 @@
elastic_req = Param.Bool(False,
"Slow down requests in case of backpressure")
+# Maximum number of requests waiting for response. Set to 0 for an
+# unlimited number of outstanding requests.
+max_outstanding_reqs = Param.Int(0,
+"Maximum number of outstanding requests")
+
# Let the user know if we have waited for a retry and not made any
# progress for a long period of time. The default value is
# somewhat arbitrary and may well have to be tuned.
diff --git a/src/cpu/testers/traffic_gen/base.cc
b/src/cpu/testers/traffic_gen/base.cc
index 43a1b83..f2385a4 100644
--- a/src/cpu/testers/traffic_gen/base.cc
+++ b/src/cpu/testers/traffic_gen/base.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2016-2018 ARM Limited
+ * Copyright (c) 2012-2013, 2016-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -75,9 +75,10 @@
noProgressEvent([this]{ noProgress(); }, name()),
nextTransitionTick(0),
nextPacketTick(0),
+ maxOutstandingReqs(p->max_outstanding_reqs),
port(name() + ".port", *this),
retryPkt(NULL),
- retryPktTick(0),
+ retryPktTick(0), blockedWaitingResp(false),
updateEvent([this]{ update(); }, name()),
masterID(system->getMasterId(this)),
streamGenerator(StreamGen::create(p))
@@ -195,7 +196,9 @@
// device accesses that could be part of a trace
if (pkt && system->isMemAddr(pkt->getAddr())) {
numPackets++;
-if (!port.sendTimingReq(pkt)) {
+// Only attempts to send if not blocked by pending responses
+blockedWaitingResp = allocateWaitingRespSlot(pkt);
+if (blockedWaitingResp || !port.sendTimingReq(pkt)) {
retryPkt = pkt;
retryPktTick = curTick();
}
@@ -213,8 +216,8 @@
}
}
-// if we are waiting for a retry, do not schedule any further
-// events, in the case of a transition or a successful send, go
+// if we are waiting for a retry or for a response, do not schedule any
+// further events, in the case of a transition or a successful send, go
// ahead and determine when the next update should take place
if (retryPkt == NULL) {
nextPacketTick = activeGenerator->nextPacketTick(elasticReq, 0);
@@ -284,10 +287,18 @@
void
BaseTrafficGen::recvReqRetry()
{
-assert(retryPkt != NULL);
-
DPRINTF(TrafficGen, "Received retry\n");
numRetries++;
+retryReq();
+}
+
+void
+BaseTrafficGen::retryReq()
+{
+assert(retryPkt != NULL);
+assert(retryPktTick != 0);
+assert(!blockedWaitingResp);
+
// attempt to send the packet, and if we are successful start up
// the machinery again
if (port.sendTimingReq(retryPkt)) {
@@ -449,9 +460,25 @@
}
bool
-BaseTrafficGen::TrafficGenPort::recvTimingResp(PacketPtr pkt)
+BaseTrafficGen::recvTimingResp(PacketPtr pkt)
{
+auto iter = waitingResp.find(pkt->req);
+
+panic_if(iter == waitingResp.end(), "%s: "
+"Received unexpected response [%s reqPtr=%x]\n",
+ pkt->print(), pkt->req);
+
+assert(iter->second <= curTick());
+
+waitingResp.erase(iter);
+
delete pkt;
+// Sends up the request if we were blocked
+if (blockedWaitingResp) {
+blockedWaitingResp = false;
+retryReq();
+}
+
return true;
}
diff --git a/src/cpu/testers/traffic_gen/base.hh
b/src/cpu/testers/traffic_gen/base.hh
index 811770f..5ffe508 100644
--- a/src/cpu/testers/traffic_gen/base.hh
+++ b/src/cpu/testers/traffic_gen/base.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2016-2018 ARM Limited
+ * Copyright (c) 2012-2013, 2016-2019 ARM Limited
* All rights reserved
*
* Th
[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: FAILED! * build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: FAILED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: FAILED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: FAILED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: FAILED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: FAILED! * build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic: FAILED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby: FAILED! * build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic: FAILED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple: FAILED! * build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing: FAILED! * build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic: FAILED! * build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing: FAILED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: FAILED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: FAILED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: FAILED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/test
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add first-/non-faulting load instructions
Hello Gabor Dozsa,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19177
to review the following change.
Change subject: arch-arm: Add first-/non-faulting load instructions
..
arch-arm: Add first-/non-faulting load instructions
First-/non-faulting loads are part of Arm SVE.
Change-Id: I93dfd6d1d74791653927e99098ddb651150a8ef7
Signed-off-by: Gabor Dozsa
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/insts/sve_macromem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/registers.hh
8 files changed, 475 insertions(+), 184 deletions(-)
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 9437471..3073564 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1216,6 +1216,14 @@
(source < ArmFault::PermissionLL + 4));
}
+template
+bool
+AbortFault::getFaultVAddr(Addr &va) const
+{
+va = (stage2 ? OVAddr : faultAddr);
+return true;
+}
+
ExceptionClass
PrefetchAbort::ec(ThreadContext *tc) const
{
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index e04a0dc..2d6ed46 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -446,6 +446,7 @@
void annotate(ArmFault::AnnotationIDs id, uint64_t val) override;
void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
override;
bool isMMUFault() const;
+bool getFaultVAddr(Addr &va) const override;
};
class PrefetchAbort : public AbortFault
diff --git a/src/arch/arm/insts/sve_macromem.hh
b/src/arch/arm/insts/sve_macromem.hh
index a31af9b..b365dcb 100644
--- a/src/arch/arm/insts/sve_macromem.hh
+++ b/src/arch/arm/insts/sve_macromem.hh
@@ -46,7 +46,8 @@
namespace ArmISA {
template class MicroopType>
+ template class MicroopType,
+ template class FirstFaultWritebackMicroopType>
class SveIndexedMemVI : public PredMacroOp
{
protected:
@@ -58,17 +59,22 @@
public:
SveIndexedMemVI(const char *mnem, ExtMachInst machInst, OpClass
__opClass,
IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
-uint64_t _imm)
+uint64_t _imm, bool firstFault)
: PredMacroOp(mnem, machInst, __opClass),
dest(_dest), gp(_gp), base(_base), imm(_imm)
{
bool isLoad = (__opClass == MemReadOp);
+assert(!firstFault || isLoad);
int num_elems = ((machInst.sveLen + 1) * 16) / sizeof(RegElemType);
numMicroops = num_elems;
if (isLoad) {
-numMicroops++;
+if (firstFault) {
+numMicroops += 2;
+} else {
+numMicroops++;
+}
}
microOps = new StaticInstPtr[numMicroops];
@@ -90,10 +96,16 @@
*uop = new MicroopType(
mnem, machInst, __opClass, _dest, _gp,
isLoad ? (IntRegIndex) VECREG_UREG0 : _base, _imm, i,
-num_elems);
+num_elems, firstFault);
}
---uop;
+if (firstFault) {
+*uop = new FirstFaultWritebackMicroopType(
+mnem, machInst, __opClass, num_elems, this);
+} else {
+--uop;
+}
+
(*uop)->setLastMicroop();
microOps[0]->setFirstMicroop();
@@ -130,7 +142,8 @@
};
template class MicroopType>
+ template class MicroopType,
+ template class FirstFaultWritebackMicroopType>
class SveIndexedMemSV : public PredMacroOp
{
protected:
@@ -147,19 +160,25 @@
SveIndexedMemSV(const char *mnem, ExtMachInst machInst, OpClass
__opClass,
IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
IntRegIndex _offset, bool _offsetIs32,
-bool _offsetIsSigned, bool _offsetIsScaled)
+bool _offsetIsSigned, bool _offsetIsScaled,
+bool firstFault)
: PredMacroOp(mnem, machInst, __opClass),
dest(_dest), gp(_gp), base(_base), offset(_offset),
offsetIs32(_offsetIs32), offsetIsSigned(_offsetIsSigned),
offsetIsScaled(_offsetIsScaled)
{
bool isLoad = (__opClass == MemReadOp);
+assert(!firstFault || isLoad);
int num_elems = ((machInst.sveLen + 1) * 16) / sizeof(RegElemType);
numMicroops = num_elems;
if (isLoad) {
-numMicroops++;
+if (firstFault) {
+numMicroops += 2;
+} else {
+numMicroops++;
+}
}
microOps = new StaticInstPtr[numMicroops];
@@ -181,10 +200,16 @@
*uop = new MicroopType(
mnem, machInst, __opClass, _dest, _gp, _base,
isLoad ? (IntRegIndex) VECREG_UREG0 : _
[gem5-dev] Change in gem5/gem5[master]: cpu: Add first-/non-faulting load support to Minor and O3
Hello Gabor Dozsa,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19178
to review the following change.
Change subject: cpu: Add first-/non-faulting load support to Minor and O3
..
cpu: Add first-/non-faulting load support to Minor and O3
Some architectures allow masking faults of memory load instructions in
some specific circumstances (e.g. first-faulting and non-faulting
loads in Arm SVE). This patch adds support for such loads in the Minor
and O3 CPU models.
Change-Id: I264a81a078f049127779aa834e89f0e693ba0bea
Signed-off-by: Gabor Dozsa
---
M src/cpu/minor/dyn_inst.cc
M src/cpu/minor/dyn_inst.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit_impl.hh
9 files changed, 235 insertions(+), 114 deletions(-)
diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc
index 3531637..087b718 100644
--- a/src/cpu/minor/dyn_inst.cc
+++ b/src/cpu/minor/dyn_inst.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, 2016 ARM Limited
+ * Copyright (c) 2013-2014, 2016,2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -108,6 +108,8 @@
os << "-";
else if (isFault())
os << "F;" << id;
+else if (translationFault != NoFault)
+os << "TF;" << id;
else
os << id;
}
@@ -120,6 +122,8 @@
if (inst.isFault())
os << "fault: \"" << inst.fault->name() << '"';
+else if (inst.translationFault != NoFault)
+os << "translation fault: \"" << inst.translationFault->name()
<< '"';
else if (inst.staticInst)
os << inst.staticInst->getName();
else
diff --git a/src/cpu/minor/dyn_inst.hh b/src/cpu/minor/dyn_inst.hh
index 0a8ff8a..3eb7f98 100644
--- a/src/cpu/minor/dyn_inst.hh
+++ b/src/cpu/minor/dyn_inst.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014,2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -194,6 +194,9 @@
/** This instruction is in the LSQ, not a functional unit */
bool inLSQ;
+/** Translation fault in case of a mem ref */
+Fault translationFault;
+
/** The instruction has been sent to the store buffer */
bool inStoreBuffer;
@@ -233,9 +236,9 @@
staticInst(NULL), id(id_), traceData(NULL),
pc(TheISA::PCState(0)), fault(fault_),
triedToPredict(false), predictedTaken(false),
-fuIndex(0), inLSQ(false), inStoreBuffer(false),
-canEarlyIssue(false), predicate(true), memAccPredicate(true),
-instToWaitFor(0), extraCommitDelay(Cycles(0)),
+fuIndex(0), inLSQ(false), translationFault(NoFault),
+inStoreBuffer(false), canEarlyIssue(false), predicate(true),
+memAccPredicate(true), instToWaitFor(0),
extraCommitDelay(Cycles(0)),
extraCommitDelayExpr(NULL), minimumCommitCycle(Cycles(0))
{ }
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 9f6fce4..2cebb34 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -116,9 +116,9 @@
const std::vector& byteEnable =
std::vector())
override
{
-execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
-size, addr, flags, nullptr, nullptr, byteEnable);
-return NoFault;
+return execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
+size, addr, flags, nullptr,
+nullptr, byteEnable);
}
Fault
@@ -128,9 +128,8 @@
override
{
assert(byteEnable.empty() || byteEnable.size() == size);
-execute.getLSQ().pushRequest(inst, false /* store */, data,
+return execute.getLSQ().pushRequest(inst, false /* store */, data,
size, addr, flags, res, nullptr, byteEnable);
-return NoFault;
}
Fault
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 810ff11..c7fda48 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -337,19 +337,19 @@
* context predicate, otherwise, it will be set to false */
bool use_context_predicate = true;
-if (response->fault != NoFault) {
+if (inst->translationFault != NoFault) {
/* Invoke memory faults. */
DPRINTF(MinorMem, "Completing fault from DTLB access: %s\n",
-response->fault->name());
+inst->translationFault->name());
if (inst->staticInst->isPrefetch()) {
DPRINTF(MinorMem, "Not taking fault on prefetch: %s\n",
-response->fault->name());
+inst->translationFault->name());
/*
[gem5-dev] Change in gem5/gem5[master]: cpu: Fix the type of the effective mem request size
Hello Gabor Dozsa, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19175 to look at the new patch set (#2). Change subject: cpu: Fix the type of the effective mem request size .. cpu: Fix the type of the effective mem request size A memory request size can be larger than 255 bytes (e.g. SVE with 2048-bit vector length) which could cause overflow in the 'uint8_t effSize' variable. Change-Id: I77e0d02a49ea7f81cacfa5be7e4ae40434af3109 Reviewed-by: Giacomo Gabrielli Signed-off-by: Giacomo Gabrielli --- M src/cpu/base_dyn_inst.hh 1 file changed, 1 insertion(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19175 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I77e0d02a49ea7f81cacfa5be7e4ae40434af3109 Gerrit-Change-Number: 19175 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Gabor Dozsa Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Fix too strict assert condition in writeback()
Hello Gabor Dozsa, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19174 to look at the new patch set (#2). Change subject: cpu-o3: Fix too strict assert condition in writeback() .. cpu-o3: Fix too strict assert condition in writeback() The assert() in the LSQ writeback() only allowed ReExec faults. However, a SplitRequest which completed the translation in PartialFault state (i.e. any but the very first cacheline translation failed) may end up here. The assert() condition is extended accordingly. The patch also removes the superfluous/unused Complete/Squashed states from the LSQ request. (The completion of the request is recorded in the flags still.) Change-Id: Ie575f4d3b4d5295585828ad8c7d3f4c7c1fe15d0 Signed-off-by: Gabor Dozsa Reviewed-by: Giacomo Gabrielli --- M src/cpu/o3/lsq.hh M src/cpu/o3/lsq_impl.hh M src/cpu/o3/lsq_unit_impl.hh 3 files changed, 4 insertions(+), 6 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19174 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie575f4d3b4d5295585828ad8c7d3f4c7c1fe15d0 Gerrit-Change-Number: 19174 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Gabor Dozsa Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add SVE LD1RQ[BHWD]
Hello Javier, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19170 to look at the new patch set (#2). Change subject: arch-arm: Add SVE LD1RQ[BHWD] .. arch-arm: Add SVE LD1RQ[BHWD] Add both scalar+scalar and scalar+immediate versions. Change-Id: If5fa1a71ab0dab93f9d35b544ea0899ece858bea Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/isa/formats/sve_2nd_level.isa M src/arch/arm/isa/insts/sve_mem.isa M src/arch/arm/isa/operands.isa 3 files changed, 121 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19170 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: If5fa1a71ab0dab93f9d35b544ea0899ece858bea Gerrit-Change-Number: 19170 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Javier Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix decoding for SVE memory instructions
Hello Adria Armejach, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19169 to look at the new patch set (#2). Change subject: arch-arm: Fix decoding for SVE memory instructions .. arch-arm: Fix decoding for SVE memory instructions Some SVE memory instructions are missing the makeSP function for register operands that can be the SP register. This leads to segmentation faults on the application side as the wrong register is decoded. Change-Id: Ic71abc845e0786a60d665231b5f7b024d2955f4b Signed-off-by: Giacomo Gabrielli Reviewed-by: Giacomo Travaglini --- M src/arch/arm/isa/formats/sve_2nd_level.isa 1 file changed, 37 insertions(+), 30 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19169 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ic71abc845e0786a60d665231b5f7b024d2955f4b Gerrit-Change-Number: 19169 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Adria Armejach Gerrit-Reviewer: Giacomo Travaglini Gerrit-CC: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim: Add getter to fault virtual address
Hello Gabor Dozsa,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19176
to review the following change.
Change subject: sim: Add getter to fault virtual address
..
sim: Add getter to fault virtual address
Change-Id: Ifd493aee9e78b0b4ddcc71e90f48679543acb861
Signed-off-by: Giacomo Gabrielli
---
M src/sim/faults.cc
M src/sim/faults.hh
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index 0606080..6523834 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -49,6 +49,11 @@
}
}
+bool FaultBase::getFaultVAddr(Addr &va) const
+{
+return false;
+}
+
void UnimpFault::invoke(ThreadContext * tc, const StaticInstPtr &inst)
{
panic("Unimpfault: %s\n", panicStr.c_str());
@@ -76,7 +81,22 @@
}
-void GenericAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr
&inst)
+bool
+GenericPageTableFault::getFaultVAddr(Addr &va) const
+{
+va = vaddr;
+return true;
+}
+
+void
+GenericAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
panic("Alignment fault when accessing virtual address %#x\n", vaddr);
}
+
+bool
+GenericAlignmentFault::getFaultVAddr(Addr &va) const
+{
+va = vaddr;
+return true;
+}
diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index 7475971..f4ba81f 100644
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -47,6 +47,7 @@
virtual FaultName name() const = 0;
virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
+virtual bool getFaultVAddr(Addr &va) const;
virtual ~FaultBase() {};
};
@@ -99,6 +100,7 @@
GenericPageTableFault(Addr va) : vaddr(va) {}
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
+bool getFaultVAddr(Addr &va) const override;
};
class GenericAlignmentFault : public FaultBase
@@ -110,6 +112,7 @@
GenericAlignmentFault(Addr va) : vaddr(va) {}
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
+bool getFaultVAddr(Addr &va) const override;
};
#endif // __FAULTS_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19176
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ifd493aee9e78b0b4ddcc71e90f48679543acb861
Gerrit-Change-Number: 19176
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Gabrielli
Gerrit-Reviewer: Gabor Dozsa
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Disable value forwarding for stores with write strobes
Hello Gabor Dozsa, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19173 to look at the new patch set (#2). Change subject: cpu: Disable value forwarding for stores with write strobes .. cpu: Disable value forwarding for stores with write strobes Change-Id: I7cb50b80b70fcf43ab23eb9e7333d16328993fe1 Signed-off-by: Gabor Dozsa --- M src/cpu/minor/lsq.cc M src/cpu/o3/lsq_impl.hh M src/cpu/o3/lsq_unit.hh M src/cpu/utils.hh 4 files changed, 69 insertions(+), 21 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19173 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I7cb50b80b70fcf43ab23eb9e7333d16328993fe1 Gerrit-Change-Number: 19173 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Gabor Dozsa Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix tracing code for SVE gather
Hello Gabor Dozsa, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19171 to look at the new patch set (#2). Change subject: arch-arm: Fix tracing code for SVE gather .. arch-arm: Fix tracing code for SVE gather Printing the entire contents of the dest vecreg for each gather microop is suboptimal as it creates false positive differences between Atomic and O3 traces. This fix prints only the memory data which a microop loads from memory. Change-Id: Idd8e0b26a96f9c9cc0b69360174bedf6a9f6dcb5 Signed-off-by: Gabor Dozsa Reviewed-by: Giacomo Gabrielli --- M src/arch/arm/isa/templates/sve_mem.isa 1 file changed, 10 insertions(+), 4 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19171 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Idd8e0b26a96f9c9cc0b69360174bedf6a9f6dcb5 Gerrit-Change-Number: 19171 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Gabor Dozsa Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix reg dependency for SVE gather microops
Hello Gabor Dozsa, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19172 to look at the new patch set (#2). Change subject: arch-arm: Fix reg dependency for SVE gather microops .. arch-arm: Fix reg dependency for SVE gather microops The first microop of an SVE gather creates a copy of the source vecreg into AA64FpUreg0. The subsequent microops must refer to this copy as a source in order to establish the correct register dependencies. Change-Id: I84d8c331f9f9ebca609948a15f686a7cde67dc31 Signed-off-by: Gabor Dozsa Reviewed-by: Giacomo Gabrielli --- M src/arch/arm/isa/insts/sve_mem.isa 1 file changed, 12 insertions(+), 6 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19172 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I84d8c331f9f9ebca609948a15f686a7cde67dc31 Gerrit-Change-Number: 19172 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Gabor Dozsa Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
