[gem5-dev] Change in gem5/gem5[master]: mem-garnet: Use smart pointers for CrossbarSwitch's members
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24244 )
Change subject: mem-garnet: Use smart pointers for CrossbarSwitch's members
..
mem-garnet: Use smart pointers for CrossbarSwitch's members
Use smart pointers for the pointers managed by CrossbarSwitch.
Change-Id: I71958c72cde5981d730aa3f68bba0ffbe4c2506f
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24244
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/mem/ruby/network/garnet2.0/CrossbarSwitch.cc
M src/mem/ruby/network/garnet2.0/CrossbarSwitch.hh
2 files changed, 8 insertions(+), 13 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/garnet2.0/CrossbarSwitch.cc
b/src/mem/ruby/network/garnet2.0/CrossbarSwitch.cc
index fbaf25b..e3a5665 100644
--- a/src/mem/ruby/network/garnet2.0/CrossbarSwitch.cc
+++ b/src/mem/ruby/network/garnet2.0/CrossbarSwitch.cc
@@ -1,6 +1,7 @@
/*
- * Copyright (c) 2008 Princeton University
+ * Copyright (c) 2020 Inria
* Copyright (c) 2016 Georgia Institute of Technology
+ * Copyright (c) 2008 Princeton University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -33,13 +34,10 @@
#include "mem/ruby/network/garnet2.0/CrossbarSwitch.hh"
-#include "base/stl_helpers.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/network/garnet2.0/OutputUnit.hh"
#include "mem/ruby/network/garnet2.0/Router.hh"
-using m5::stl_helpers::deletePointers;
-
CrossbarSwitch::CrossbarSwitch(Router *router)
: Consumer(router)
{
@@ -48,11 +46,6 @@
m_crossbar_activity = 0;
}
-CrossbarSwitch::~CrossbarSwitch()
-{
-deletePointers(m_switch_buffer);
-}
-
void
CrossbarSwitch::init()
{
@@ -61,7 +54,7 @@
m_num_inports = m_router->get_num_inports();
m_switch_buffer.resize(m_num_inports);
for (int i = 0; i < m_num_inports; i++) {
-m_switch_buffer[i] = new flitBuffer();
+m_switch_buffer[i].reset(new flitBuffer());
}
}
diff --git a/src/mem/ruby/network/garnet2.0/CrossbarSwitch.hh
b/src/mem/ruby/network/garnet2.0/CrossbarSwitch.hh
index 9d4fee5..40d2f6b 100644
--- a/src/mem/ruby/network/garnet2.0/CrossbarSwitch.hh
+++ b/src/mem/ruby/network/garnet2.0/CrossbarSwitch.hh
@@ -1,6 +1,7 @@
/*
- * Copyright (c) 2008 Princeton University
+ * Copyright (c) 2020 Inria
* Copyright (c) 2016 Georgia Institute of Technology
+ * Copyright (c) 2008 Princeton University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -35,6 +36,7 @@
#define __MEM_RUBY_NETWORK_GARNET2_0_CROSSBARSWITCH_HH__
#include
+#include
#include
#include "mem/ruby/common/Consumer.hh"
@@ -48,7 +50,7 @@
{
public:
CrossbarSwitch(Router *router);
-~CrossbarSwitch();
+~CrossbarSwitch() = default;
void wakeup();
void init();
void print(std::ostream& out) const {};
@@ -66,7 +68,7 @@
int m_num_inports;
double m_crossbar_activity;
Router *m_router;
-std::vector m_switch_buffer;
+std::vector> m_switch_buffer;
std::vector m_output_unit;
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I71958c72cde5981d730aa3f68bba0ffbe4c2506f
Gerrit-Change-Number: 24244
Gerrit-PatchSet: 4
Gerrit-Owner: Daniel Carvalho
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: x86: Move local APIC initialization out of initCPU.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/24186 ) Change subject: x86: Move local APIC initialization out of initCPU. .. x86: Move local APIC initialization out of initCPU. The APIC can (and probably should) set its version register on its own. Also it already configures its CPUID register when associated with a CPU and doesn't need initCPU to do that. Change-Id: I4611563668d197c48caf2f23fcde9ec2ec101fe7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24186 Maintainer: Gabe Black Tested-by: kokoro Reviewed-by: Jason Lowe-Power --- M src/arch/x86/interrupts.cc M src/arch/x86/utility.cc 2 files changed, 2 insertions(+), 8 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Gabe Black: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc index 06bf41b..b447216 100644 --- a/src/arch/x86/interrupts.cc +++ b/src/arch/x86/interrupts.cc @@ -614,6 +614,8 @@ regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); ISRV = 0; IRRV = 0; + +regs[APIC_VERSION] = (5 << 16) | 0x14; } diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc index 13019e9..b00e686 100644 --- a/src/arch/x86/utility.cc +++ b/src/arch/x86/utility.cc @@ -84,14 +84,6 @@ // passed. No BIST actually runs, but software may still check this // register for errors. tc->setIntReg(INTREG_RAX, 0); - -Interrupts * interrupts = dynamic_cast( -tc->getCpuPtr()->getInterruptController(0)); -assert(interrupts); - -interrupts->setRegNoEffect(APIC_ID, cpuId << 24); - -interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14); } void startupCPU(ThreadContext *tc, int cpuId) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24186 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I4611563668d197c48caf2f23fcde9ec2ec101fe7 Gerrit-Change-Number: 24186 Gerrit-PatchSet: 3 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Brandon Potter Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: x86: Stop clearing RAX for BIST in initCPU.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24187 )
Change subject: x86: Stop clearing RAX for BIST in initCPU.
..
x86: Stop clearing RAX for BIST in initCPU.
This doesn't actually change any behavior since RAX was being zeroed
anyway, but since we don't and almost certainly never will have a BIST
and the BIST is optional even in real hardware, we can drop it and
simplify initCPU a little further.
This reduces x86's initCPU function to just an invocation of
InitInterrupt's invoke.
Change-Id: I56b1aae2c1a738ef7ffabcf648dd7d0fb819d4e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24187
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/arch/x86/utility.cc
1 file changed, 1 insertion(+), 10 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index b00e686..75f242d 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -74,16 +74,7 @@
void
initCPU(ThreadContext *tc, int cpuId)
{
-// This function is essentially performing a reset. The actual INIT
-// interrupt does a subset of this, so we'll piggyback on some of its
-// functionality.
-InitInterrupt init(0);
-init.invoke(tc);
-
-// Set integer register EAX to 0 to indicate that the optional BIST
-// passed. No BIST actually runs, but software may still check this
-// register for errors.
-tc->setIntReg(INTREG_RAX, 0);
+InitInterrupt(0).invoke(tc);
}
void startupCPU(ThreadContext *tc, int cpuId)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I56b1aae2c1a738ef7ffabcf648dd7d0fb819d4e0
Gerrit-Change-Number: 24187
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Another test commit
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24331 ) Change subject: misc: Another test commit .. misc: Another test commit This is a test commit to check the 'develop' branch can be pushed too. Change-Id: I5e41c94bd82ecc846664ccce2a506de059445700 --- A test2 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/test2 b/test2 new file mode 100644 index 000..b729d95 --- /dev/null +++ b/test2 @@ -0,0 +1 @@ +Test2 -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24331 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I5e41c94bd82ecc846664ccce2a506de059445700 Gerrit-Change-Number: 24331 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: x86: Move miscreg initialization to the ISA class.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24185 )
Change subject: x86: Move miscreg initialization to the ISA class.
..
x86: Move miscreg initialization to the ISA class.
The initCPU function was setting a lot of values to zero or other
initial values, but that's something the ISA object can do as part of
its clear() method. This gets rid of a lot of code that was
individually zeroing registers, and also centralizes responsibility
for those registers in the ISA.
Change-Id: Iafcffd3f9329c39f77009b38b1696f91c36c117e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24185
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/isa.cc
M src/arch/x86/utility.cc
2 files changed, 29 insertions(+), 106 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index d96a858..6577240 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -108,8 +108,29 @@
// Blank everything. 0 might not be an appropriate value for some
things,
// but it is for most.
memset(regVal, 0, NumMiscRegs * sizeof(RegVal));
+
+// If some state should be non-zero after a reset, set those values
here.
+regVal[MISCREG_CR0] = 0x6010ULL;
+
+regVal[MISCREG_MTRRCAP] = 0x0508;
+
+regVal[MISCREG_MCG_CAP] = 0x104;
+
+regVal[MISCREG_PAT] = 0x0007040600070406ULL;
+
+regVal[MISCREG_SYSCFG] = 0x20601;
+
+regVal[MISCREG_TOP_MEM] = 0x400;
+
regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
regVal[MISCREG_DR7] = 1 << 10;
+
+LocalApicBase lApicBase = 0;
+lApicBase.base = 0xFEE0 >> 12;
+lApicBase.enable = 1;
+// The "bsp" bit will be set when this register is read, since then
we'll
+// have a ThreadContext to check the contextId from.
+regVal[MISCREG_APIC_BASE] = lApicBase;
}
ISA::ISA(Params *p)
@@ -148,6 +169,12 @@
return insertBits(fsw, 13, 11, top);
}
+if (miscReg == MISCREG_APIC_BASE) {
+LocalApicBase base = regVal[MISCREG_APIC_BASE];
+base.bsp = (tc->contextId() == 0);
+return base;
+}
+
return readMiscRegNoEffect(miscReg);
}
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index b430124..13019e9 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -71,7 +71,8 @@
}
}
-void initCPU(ThreadContext *tc, int cpuId)
+void
+initCPU(ThreadContext *tc, int cpuId)
{
// This function is essentially performing a reset. The actual INIT
// interrupt does a subset of this, so we'll piggyback on some of its
@@ -79,109 +80,11 @@
InitInterrupt init(0);
init.invoke(tc);
-PCState pc = tc->pcState();
-pc.upc(0);
-pc.nupc(1);
-tc->pcState(pc);
-
-// These next two loops zero internal microcode and implicit registers.
-// They aren't specified by the ISA but are used internally by M5's
-// implementation.
-for (int index = 0; index < NumMicroIntRegs; index++) {
-tc->setIntReg(INTREG_MICRO(index), 0);
-}
-
-for (int index = 0; index < NumImplicitIntRegs; index++) {
-tc->setIntReg(INTREG_IMPLICIT(index), 0);
-}
-
// Set integer register EAX to 0 to indicate that the optional BIST
// passed. No BIST actually runs, but software may still check this
// register for errors.
tc->setIntReg(INTREG_RAX, 0);
-tc->setMiscReg(MISCREG_CR0, 0x6010ULL);
-tc->setMiscReg(MISCREG_CR8, 0);
-
-// TODO initialize x87, 64 bit, and 128 bit media state
-
-tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
-for (int i = 0; i < 8; i++) {
-tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
-tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
-}
-tc->setMiscReg(MISCREG_MTRR_FIX_64K_0, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_16K_8, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_16K_A, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_C, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_D, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_E, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_F, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
-
-tc->setMiscReg(MISCREG_DEF_TYPE, 0);
-
-tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
-tc->setMiscReg(MISCREG_MCG_STATUS, 0);
-tc->setMiscReg(MISCREG_MCG_CTL, 0);
-
-for (int i = 0; i < 5; i++) {
-tc->setMiscReg(MISCREG_MC_CTL(i), 0);
-tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
-tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
-tc->setMiscReg(MISCREG_MC_MISC(i), 0);
-}
-
-tc->setMiscReg(MISCREG_TSC, 0);
-
[gem5-dev] Change in gem5/gem5[develop]: misc: Test commit
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24330 ) Change subject: misc: Test commit .. misc: Test commit This is a test commit to check the 'develop' branch exists and can be pushed too. Change-Id: Ia1ab9e785094ceef74eaa77bebeecb4ce06205de --- A testfile.dat 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/testfile.dat b/testfile.dat new file mode 100644 index 000..9daeafb --- /dev/null +++ b/testfile.dat @@ -0,0 +1 @@ +test -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24330 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia1ab9e785094ceef74eaa77bebeecb4ce06205de Gerrit-Change-Number: 24330 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Stop checkpointing ARM TLB state
Similarly, the interrupts object checkpoints both an array of bools (interrupts), and a scalar bit vector (intStatus) which hold the same information. That information *does* need to be in the checkpoint as far as I can tell, but it doesn't need to be in there twice. Gabe On Mon, Jan 13, 2020 at 6:11 PM Gabe Black wrote: > Hi folks. I'm looking at checkpointing fast models, and one thing I'll > have to put into the checkpoint is something for the TLBs. I was looking at > what they checkpoint, and I think all of it should be removed from > checkpoints. > > As far as I know: > > _attr: A cached value which is an implementation detail and not > architecturally visible. > haveLPAE: A setting which is not architectural/software visible state. > directToStage2: Derived state which comes from miscregs. Can be recovered > on first use by updateMiscRegs if miscRegValid is false (which it is on > construction). > stage2Reg, stage2DescReq: Information about in flight translations? These > should not be in flight when a checkpoint is taken since state should have > drained. > > TLB entries which can be reloaded in the new TLB. The new TLB won't > necessarily have the same size as the old one, and so can't necessarily > have the same table of entries. The entries are not (as far as I know) > architecturally visible. > > All of this state can and should be removed from checkpoints as far as I > can tell. Please let me know if I'm wrong about some bit of this. > > Gabe > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Stop checkpointing ARM TLB state
Hi folks. I'm looking at checkpointing fast models, and one thing I'll have to put into the checkpoint is something for the TLBs. I was looking at what they checkpoint, and I think all of it should be removed from checkpoints. As far as I know: _attr: A cached value which is an implementation detail and not architecturally visible. haveLPAE: A setting which is not architectural/software visible state. directToStage2: Derived state which comes from miscregs. Can be recovered on first use by updateMiscRegs if miscRegValid is false (which it is on construction). stage2Reg, stage2DescReq: Information about in flight translations? These should not be in flight when a checkpoint is taken since state should have drained. TLB entries which can be reloaded in the new TLB. The new TLB won't necessarily have the same size as the old one, and so can't necessarily have the same table of entries. The entries are not (as far as I know) architecturally visible. All of this state can and should be removed from checkpoints as far as I can tell. Please let me know if I'm wrong about some bit of this. Gabe ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arm: A couple small fixes for the arm64 bootloader makefile.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24329 ) Change subject: arm: A couple small fixes for the arm64 bootloader makefile. .. arm: A couple small fixes for the arm64 bootloader makefile. First, remove a deprecated flag that gcc no longer recognizes. Second, disable suffix based implicit makefile rules. These, in combination with the %.o: boot.S rule, were tricking make into deleting it's own makefile. How, you might ask? make wants to update its makefile, since that's a thing it does automatically. This is useful if you, for instance, have computed header dependencies. make decides it can make a file called "makefile" from a file called "makefile.o" by doing a linking step. make decides it can make makefile.o from boot.S from the %.o: boot.S rule, which it does. It then attempts to link makefile.o into makefile, but that fails because it lacks a "main" function since it's using a built in rule which doesn't know not to expect main. The makefile is clobbered in the process. make then deletes makefile.o because it was an implicit target, eliminating all the evidence. Change-Id: Ib0dfc333dc554caf5772dd8468dba6ba821f98ac --- M system/arm/bootloader/arm64/makefile 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/system/arm/bootloader/arm64/makefile b/system/arm/bootloader/arm64/makefile index 4834cf5..fd5f69f 100644 --- a/system/arm/bootloader/arm64/makefile +++ b/system/arm/bootloader/arm64/makefile @@ -28,6 +28,8 @@ CC = $(CROSS_COMPILE)gcc LD = $(CROSS_COMPILE)ld +.SUFFIXES: + BUILDDIR = . DESTDIR = $(error Please set DESTDIR to wanted installation directory) @@ -37,7 +39,7 @@ -Dkernel=0x8008 \ -Dmbox=0x8000fff8 -Ddtb=0x8100 -LDFLAGS = -N -Ttext 0x0010 -non_shared -static +LDFLAGS = -N -Ttext 0x0010 -static .PHONY: all clean install mkdir -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24329 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib0dfc333dc554caf5772dd8468dba6ba821f98ac Gerrit-Change-Number: 24329 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: fastmodel: Set itstate when building a PCState from IRIS.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24328 ) Change subject: fastmodel: Set itstate when building a PCState from IRIS. .. fastmodel: Set itstate when building a PCState from IRIS. These bits are probably never going to be non-zero since we'd have to take a checkpoint part way through an if/then construct in thumb, but they're easy to extract and we might as well store them properly. Change-Id: Ifc5c34063dd23f72cc106c0d77d90c5e6ee871be --- M src/arch/arm/fastmodel/iris/thread_context.cc 1 file changed, 2 insertions(+), 0 deletions(-) diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc index f3b4c95..14c3b8c 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/thread_context.cc @@ -445,6 +445,8 @@ pc.aarch64(!cpsr.width); pc.nextAArch64(!cpsr.width); pc.illegalExec(false); +pc.itstate(itState(cpsr)); +pc.nextItstate(0); iris::ResourceReadResult result; call().resource_read(_instId, result, pcRscId); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24328 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ifc5c34063dd23f72cc106c0d77d90c5e6ee871be Gerrit-Change-Number: 24328 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: fastmodel: Ensure unset vec reg bits are zero/false.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/24327 )
Change subject: fastmodel: Ensure unset vec reg bits are zero/false.
..
fastmodel: Ensure unset vec reg bits are zero/false.
These bits won't be overwritten with values from IRIS, and so we should
make sure they're cleared and don't have old values or junk.
Change-Id: Ib81780ab523f00d6a4d31841d68a3d83924982a9
---
M src/arch/arm/fastmodel/iris/thread_context.cc
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc
b/src/arch/arm/fastmodel/iris/thread_context.cc
index f487ebc..f3b4c95 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -572,12 +572,14 @@
ThreadContext::readVecReg(const RegId _id) const
{
const RegIndex idx = reg_id.index();
+ArmISA::VecRegContainer = vecRegs.at(idx);
+reg.zero();
+
// Ignore accesses to registers which aren't architected. gem5 defines
a
// few extra registers which it uses internally in the implementation
of
// some instructions.
if (idx >= vecRegIds.size())
-return vecRegs.at(idx);
-ArmISA::VecRegContainer = vecRegs.at(idx);
+return reg;
iris::ResourceReadResult result;
call().resource_read(_instId, result, vecRegIds.at(idx));
@@ -598,10 +600,12 @@
ThreadContext::readVecPredReg(const RegId _id) const
{
RegIndex idx = reg_id.index();
-if (idx >= vecPredRegIds.size())
-return vecPredRegs.at(idx);
ArmISA::VecPredRegContainer = vecPredRegs.at(idx);
+reg.reset();
+
+if (idx >= vecPredRegIds.size())
+return reg;
iris::ResourceReadResult result;
call().resource_read(_instId, result, vecPredRegIds.at(idx));
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24327
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib81780ab523f00d6a4d31841d68a3d83924982a9
Gerrit-Change-Number: 24327
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: tests: Removed unneeded 02.insttest data
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24343 ) Change subject: tests: Removed unneeded 02.insttest data .. tests: Removed unneeded 02.insttest data This test has been migrated to be run via `./main.py`. Change-Id: Iab6dca56820a34ce6bfa1b7adfad3ae7d54bec63 --- D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini D
Re: [gem5-dev] silly aarch64 assembly question
Ok, thanks, I'll take a look! Gabe On Mon, Jan 13, 2020 at 2:47 AM Ciro Santilli wrote: > (you can then replace .double with .quad to load your own bit pattern > instead of having to work our the desired float, see: > > https://github.com/cirosantilli/linux-kernel-module-cheat/blob/657c59249e56d861bb0a437a1b1c757797281910/userland/arch/aarch64/gas_data_sizes.S#L26 > ) > > On Mon, Jan 13, 2020 at 10:41 AM Ciro Santilli > wrote: > > > > There is no silly question. > > > > I think the easiest thing is to put the desired bit patterns in memory > > use LD1 as shown here: > > > https://github.com/cirosantilli/linux-kernel-module-cheat/blob/657c59249e56d861bb0a437a1b1c757797281910/userland/arch/aarch64/fadd_vector.S#L21 > > > > This may also be of interest: > > > https://github.com/cirosantilli/linux-kernel-module-cheat/blob/657c59249e56d861bb0a437a1b1c757797281910/userland/arch/aarch64/gdb_tests/floating_registers.S > > > > On Mon, Jan 13, 2020 at 3:29 AM Gabe Black wrote: > > > > > > Hi folks. I do most of my aarch64 assembly level programming by > example, ie > > > by just doing what other code I can find is already doing. I'm trying > to > > > test some code I wrote to checkpoint the FP state in a fast model ARM > CPU, > > > and to do that I need to load known values into those registers to make > > > sure they end up in the right place in the checkpoint. > > > > > > What assembly instruction should I use to maximally load up those > registers > > > with a known bit pattern? Ideally it would be something where I could > tell > > > that the right bits ended up in the right register and in the right > part of > > > the register. > > > > > > This particular CPU (CortexA76) does not seem to have SVE, so this > would > > > need to be a neon type instruction. Sorry for the dumb question, but I > > > figure this might be a very easy question for somebody to answer which > > > would save me a lot of trial and error trying to find the right > instruction > > > and syntax to get it going. > > > > > > Thanks! > > > Gabe > > > ___ > > > gem5-dev mailing list > > > gem5-dev@gem5.org > > > http://m5sim.org/mailman/listinfo/gem5-dev > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: configs: Remove check for kernel in fs.py.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24284 )
Change subject: configs: Remove check for kernel in fs.py.
..
configs: Remove check for kernel in fs.py.
It is *not* true that a kernel is required in FS mode. For example,
in SPARC, gem5 is set up to run actual system firmware which will load
a kernel from the disk image. Other systems can run in a bare metal
mode where they also have no kernel.
If a configuration requires a kernel, it should check for it in C++
where there context lives, not globally in fs.py.
Change-Id: Ib094c29474c248f866bd08d4f975648a2c707a19
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24284
Reviewed-by: Daniel Carvalho
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M configs/example/fs.py
1 file changed, 0 insertions(+), 6 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 7efe433..e202d75 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -130,9 +130,6 @@
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
-else:
-print("Error: a kernel must be provided to run in full system
mode")
-sys.exit(1)
if options.script is not None:
test_sys.readfile = options.script
@@ -281,9 +278,6 @@
drive_sys.cpu.connectAllPorts(drive_sys.membus)
if options.kernel is not None:
drive_sys.kernel = binary(options.kernel)
-else:
-print("Error: a kernel must be provided to run in full system
mode")
-sys.exit(1)
if ObjectList.is_kvm_cpu(DriveCPUClass):
drive_sys.kvm_vm = KvmVM()
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24284
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib094c29474c248f866bd08d4f975648a2c707a19
Gerrit-Change-Number: 24284
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: sim: Add a unit test for the GuestABI mechanism.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/23197 )
Change subject: sim: Add a unit test for the GuestABI mechanism.
..
sim: Add a unit test for the GuestABI mechanism.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187
Change-Id: I76934d94b4c61570a4ca603388012c65280e2b7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23197
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/SConscript
A src/sim/guest_abi.test.cc
2 files changed, 278 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/SConscript b/src/sim/SConscript
index aacdb34..b27dc51 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -78,6 +78,7 @@
Source('mathexpr.cc')
GTest('byteswap.test', 'byteswap.test.cc', '../base/types.cc')
+GTest('guest_abi.test', 'guest_abi.test.cc')
if env['TARGET_ISA'] != 'null':
SimObject('InstTracer.py')
diff --git a/src/sim/guest_abi.test.cc b/src/sim/guest_abi.test.cc
new file mode 100644
index 000..ee536aa
--- /dev/null
+++ b/src/sim/guest_abi.test.cc
@@ -0,0 +1,277 @@
+/*
+ * Copyright 2019 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include
+
+#include
+#include
+
+#include "sim/guest_abi.hh"
+
+// Fake ThreadContext which holds data and captures results.
+class ThreadContext
+{
+ public:
+static const int ints[];
+static const double floats[];
+
+static const int DefaultIntResult;
+static const double DefaultFloatResult;
+
+int intResult = DefaultIntResult;
+double floatResult = DefaultFloatResult;
+};
+
+const int ThreadContext::ints[] = {
+0, 1, 2, 3, 4, 5, 6, 7
+};
+const double ThreadContext::floats[] = {
+10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0
+};
+
+const int ThreadContext::DefaultIntResult = 0;
+const double ThreadContext::DefaultFloatResult = 0.0;
+
+// ABI anchor for an ABI which has 1D progress. Conceptually, this could be
+// because integer and floating point arguments are stored in the same
+// registers.
+struct TestABI_1D
+{
+using Position = int;
+};
+
+// ABI anchor for an ABI which has 2D progress. Conceptually, this could be
+// because integer and floating point arguments are stored in separate
+// registers.
+struct TestABI_2D
+{
+using Position = std::pair;
+};
+
+namespace GuestABI
+{
+
+// Hooks for the 1D ABI arguments and return value. Add 1 or 1.0 to return
+// values so we can tell they went through the right set of hooks.
+template <>
+struct Argument
+{
+static int
+get(ThreadContext *tc, TestABI_1D::Position )
+{
+return tc->ints[position++];
+}
+};
+
+template
+struct Argument::value>::type>
+{
+static Arg
+get(ThreadContext *tc, TestABI_1D::Position )
+{
+return tc->floats[position++];
+}
+};
+
+template <>
+struct Result
+{
+static void
+store(ThreadContext *tc, const int )
+{
+tc->intResult = ret + 1;
+}
+};
+
+template
+struct Result::value>::type>
+{
+static void
+store(ThreadContext *tc, const Ret )
+{
+tc->floatResult = ret + 1.0;
+}
+};
+
+// Hooks for the 2D ABI arguments and return value. Add 2 or 2.0 to return
+// values so we can tell they went through the right set of hooks.
+
+template <>
+struct Argument
+{
+
[gem5-dev] Change in gem5/gem5[master]: sim: Implement a varargs like mechanism for GuestABI system.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/23195 )
Change subject: sim: Implement a varargs like mechanism for GuestABI system.
..
sim: Implement a varargs like mechanism for GuestABI system.
This will let a function called with a GuestABI emulate the ...
mechanism available in C. To make that possible without the functions
knowing anything about the ABI and to follow C++'s (sensible)
templating and virtual function rules, you have to tell VarArgs what
types you might want to extract from it, unlike the pure ... varargs
style mechanism.
Also unlike ..., there is no mechanism in place to force the varargs
to appear last in the argument list. It will pick up the progress
through the arguments at the point it's reached, and will ignore any
later arguments. It would be possible to be more rigorous about this
by changing the callFrom templates, but the overhead in complexity
is probably not worth it.
Also, retrieving arguments through a VarArgs happens live, meaning at
the point that the argument is asked for. If the ThreadContext or
memory the argument lives in is modified before that point, the
retrieved value will reflect that modification and not what the
function was originally called with. Care should be taken so that this
doesn't cause corrupted arguments.
Finally, this mechansim (and the Guest ABI mechanism in general) is
complex and should have tests written for it. That should be possible
since ThreadContext is forward declared and so the test can say it
works however it wants or even ignore it completely. If that changes
in the future, we may need a mock ThreadContext implementation.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187
Change-Id: I37484b50a3e8c0d259d9590e32fecbb5f76670c1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23195
Reviewed-by: Jason Lowe-Power
Reviewed-by: Bobby R. Bruce
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/sim/guest_abi.hh
1 file changed, 141 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/guest_abi.hh b/src/sim/guest_abi.hh
index 109c872..b2176a6 100644
--- a/src/sim/guest_abi.hh
+++ b/src/sim/guest_abi.hh
@@ -31,6 +31,7 @@
#define __SIM_GUEST_ABI_HH__
#include
+#include
#include
class ThreadContext;
@@ -90,6 +91,146 @@
/*
+ * These templates implement a variadic argument mechanism for guest ABI
+ * functions. A function might be written like this:
+ *
+ * void
+ * func(ThreadContext *tc, VarArgs varargs)
+ * {
+ * warn("Address = %#x, int = %d.",
+ * varargs.get(), varargs.get());
+ * }
+ *
+ * where an object of type VarArgs<...> is its last argument. The types
given
+ * to the template specify what types the function might need to retrieve
from
+ * varargs. The varargs object will then have get<> methods for each of
those
+ * types.
+ *
+ * Note that each get<> will happen live. If you modify values through the
+ * ThreadContext *tc and then run get<>(), you may alter one of your
arguments.
+ * If you're going to use tc to modify state, it would be a good idea to
use
+ * get<>() as soon as possible to avoid corrupting the functions arguments.
+ */
+
+// A recursive template which defines virtual functions to retrieve each
of the
+// requested types. This provides the ABI agnostic interface the function
uses.
+template
+class VarArgsBase;
+
+template
+class VarArgsBase : public VarArgsBase
+{
+ public:
+// The virtual function takes a reference parameter so that the
different
+// _getImpl methods can co-exist through overloading.
+virtual void _getImpl(First &) = 0;
+
+// Make sure base class _getImpl-es aren't hidden by this one.
+using VarArgsBase::_getImpl;
+};
+
+// The base case of the recursion.
+template <>
+class VarArgsBase<>
+{
+ protected:
+// This just gives the "using" statement in the non base case
something to
+// refer to.
+void _getImpl();
+};
+
+
+// A recursive template which defines the ABI specific implementation of
the
+// interface defined above.
+//
+// The types in Types are consumed one by one, and by
+// the time we get down to the base case we'd have lost track of the
complete
+// set we need to know what interface to inherit. The Base parameter keeps
+// track of that through the recursion.
+template
+class VarArgsImpl;
+
+template
+class VarArgsImpl :
+public VarArgsImpl
+{
+ protected:
+// Bring forward the base class constructor.
+using VarArgsImpl::VarArgsImpl;
+// Make sure base class _getImpl-es don't get hidden by ours.
+using VarArgsImpl::_getImpl;
+
+// Implement a version of _getImple, using the ABI specialized version
of
+// the Argument class.
+void
+
[gem5-dev] Change in gem5/gem5[master]: sim: Add a dumpSimcall mechanism to GuestABI.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/23460 )
Change subject: sim: Add a dumpSimcall mechanism to GuestABI.
..
sim: Add a dumpSimcall mechanism to GuestABI.
This dumps a signature for a simcall as if it was going to be invoked,
and can be used for debugging.
Change-Id: I6262b94ad4186bac8dc5a1469e9bb3b8ae9d34e1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23460
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/guest_abi.hh
M src/sim/guest_abi.test.cc
2 files changed, 82 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/guest_abi.hh b/src/sim/guest_abi.hh
index b2176a6..ff1464e 100644
--- a/src/sim/guest_abi.hh
+++ b/src/sim/guest_abi.hh
@@ -32,6 +32,7 @@
#include
#include
+#include
#include
class ThreadContext;
@@ -213,6 +214,14 @@
}
};
+template
+std::ostream &
+operator << (std::ostream , const VarArgs )
+{
+os << "...";
+return os;
+}
+
// The ABI independent hook which tells the GuestABI mechanism what to do
with
// a VarArgs argument. It constructs the underlying implementation which
knows
// about the ABI, and installs it in the VarArgs wrapper to give to the
@@ -301,6 +310,44 @@
callFrom(tc, position, partial);
}
+
+
+/*
+ * These functions are like the ones above, except they print the arguments
+ * a target function would be called with instead of actually calling it.
+ */
+
+// With no arguments to print, add the closing parenthesis and return.
+template
+static void
+dumpArgsFrom(int count, std::ostream , ThreadContext *tc,
+ typename ABI::Position )
+{
+os << ")";
+}
+
+// Recursively gather arguments for target from tc until we get to the base
+// case above, and append those arguments to the string stream being
+// constructed.
+template
+static void
+dumpArgsFrom(int count, std::ostream , ThreadContext *tc,
+ typename ABI::Position )
+{
+// Either open the parenthesis or add a comma, depending on where we
are
+// in the argument list.
+os << (count ? ", " : "(");
+
+// Extract the next argument from the thread context.
+NextArg next = Argument::get(tc, position);
+
+// Add this argument to the list.
+os << next;
+
+// Recursively handle any remaining arguments.
+dumpArgsFrom(count + 1, os, tc, position);
+}
+
} // namespace GuestABI
@@ -347,4 +394,32 @@
tc, std::function(target));
}
+
+// These functions also wrap a simulator level function. Instead of
running the
+// function, they return a string which shows what arguments the function
would
+// be invoked with if it were called from the given context.
+
+template
+std::string
+dumpSimcall(std::string name, ThreadContext *tc,
+std::function target=
+std::function())
+{
+auto position = typename ABI::Position();
+std::ostringstream ss;
+
+ss << name;
+GuestABI::dumpArgsFrom(0, ss, tc, position);
+return ss.str();
+}
+
+template
+std::string
+dumpSimcall(std::string name, ThreadContext *tc,
+Ret (*target)(ThreadContext *, Args...))
+{
+return dumpSimcall(
+name, tc, std::functionArgs...)>(target));
+}
+
#endif // __SIM_GUEST_ABI_HH__
diff --git a/src/sim/guest_abi.test.cc b/src/sim/guest_abi.test.cc
index ee536aa..19efb7d 100644
--- a/src/sim/guest_abi.test.cc
+++ b/src/sim/guest_abi.test.cc
@@ -275,3 +275,10 @@
EXPECT_EQ(tc.floatResult, DoubleRetValue + 2.0);
}
}
+
+TEST(GuestABI, dumpSimcall)
+{
+ThreadContext tc;
+std::string dump = dumpSimcall("test", , testIntVoid);
+EXPECT_EQ(dump, "test(0, 11, 2, 13, ...)");
+}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/23460
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I6262b94ad4186bac8dc5a1469e9bb3b8ae9d34e1
Gerrit-Change-Number: 23460
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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Re: [gem5-dev] silly aarch64 assembly question
(you can then replace .double with .quad to load your own bit pattern instead of having to work our the desired float, see: https://github.com/cirosantilli/linux-kernel-module-cheat/blob/657c59249e56d861bb0a437a1b1c757797281910/userland/arch/aarch64/gas_data_sizes.S#L26 ) On Mon, Jan 13, 2020 at 10:41 AM Ciro Santilli wrote: > > There is no silly question. > > I think the easiest thing is to put the desired bit patterns in memory > use LD1 as shown here: > https://github.com/cirosantilli/linux-kernel-module-cheat/blob/657c59249e56d861bb0a437a1b1c757797281910/userland/arch/aarch64/fadd_vector.S#L21 > > This may also be of interest: > https://github.com/cirosantilli/linux-kernel-module-cheat/blob/657c59249e56d861bb0a437a1b1c757797281910/userland/arch/aarch64/gdb_tests/floating_registers.S > > On Mon, Jan 13, 2020 at 3:29 AM Gabe Black wrote: > > > > Hi folks. I do most of my aarch64 assembly level programming by example, ie > > by just doing what other code I can find is already doing. I'm trying to > > test some code I wrote to checkpoint the FP state in a fast model ARM CPU, > > and to do that I need to load known values into those registers to make > > sure they end up in the right place in the checkpoint. > > > > What assembly instruction should I use to maximally load up those registers > > with a known bit pattern? Ideally it would be something where I could tell > > that the right bits ended up in the right register and in the right part of > > the register. > > > > This particular CPU (CortexA76) does not seem to have SVE, so this would > > need to be a neon type instruction. Sorry for the dumb question, but I > > figure this might be a very easy question for somebody to answer which > > would save me a lot of trial and error trying to find the right instruction > > and syntax to get it going. > > > > Thanks! > > Gabe > > ___ > > gem5-dev mailing list > > gem5-dev@gem5.org > > http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] silly aarch64 assembly question
There is no silly question. I think the easiest thing is to put the desired bit patterns in memory use LD1 as shown here: https://github.com/cirosantilli/linux-kernel-module-cheat/blob/657c59249e56d861bb0a437a1b1c757797281910/userland/arch/aarch64/fadd_vector.S#L21 This may also be of interest: https://github.com/cirosantilli/linux-kernel-module-cheat/blob/657c59249e56d861bb0a437a1b1c757797281910/userland/arch/aarch64/gdb_tests/floating_registers.S On Mon, Jan 13, 2020 at 3:29 AM Gabe Black wrote: > > Hi folks. I do most of my aarch64 assembly level programming by example, ie > by just doing what other code I can find is already doing. I'm trying to > test some code I wrote to checkpoint the FP state in a fast model ARM CPU, > and to do that I need to load known values into those registers to make > sure they end up in the right place in the checkpoint. > > What assembly instruction should I use to maximally load up those registers > with a known bit pattern? Ideally it would be something where I could tell > that the right bits ended up in the right register and in the right part of > the register. > > This particular CPU (CortexA76) does not seem to have SVE, so this would > need to be a neon type instruction. Sorry for the dumb question, but I > figure this might be a very easy question for somebody to answer which > would save me a lot of trial and error trying to find the right instruction > and syntax to get it going. > > Thanks! > Gabe > ___ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: configs, arch, sim: Move fixFuncEventAddr into the Workload class.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24287 ) Change subject: configs,arch,sim: Move fixFuncEventAddr into the Workload class. .. configs,arch,sim: Move fixFuncEventAddr into the Workload class. This is specialized per arch, and the Workload class is the only thing actually using it. It doesn't make any sense to dispatch those calls over to the System object, especially since that was, in most cases, the only reason an ISA specific system class even still existed. After this change, only ARM still has an architecture specific System class. Change-Id: I81b6c4db14b612bff8840157cfc56393370095e2 --- M configs/common/FSConfig.py D src/arch/alpha/AlphaSystem.py M src/arch/alpha/SConscript M src/arch/alpha/freebsd/fs_workload.cc M src/arch/alpha/fs_workload.cc M src/arch/alpha/fs_workload.hh M src/arch/alpha/linux/fs_workload.cc M src/arch/alpha/linux/fs_workload.hh D src/arch/alpha/system.cc D src/arch/alpha/system.hh M src/arch/arm/fs_workload.hh M src/arch/arm/system.hh D src/arch/mips/MipsSystem.py M src/arch/mips/SConscript D src/arch/mips/bare_iron/system.cc D src/arch/mips/bare_iron/system.hh D src/arch/mips/linux/system.cc D src/arch/mips/linux/system.hh D src/arch/mips/system.cc D src/arch/mips/system.hh D src/arch/riscv/RiscvSystem.py M src/arch/riscv/SConscript D src/arch/riscv/system.cc D src/arch/riscv/system.hh M src/arch/riscv/tlb.cc M src/arch/sparc/SConscript D src/arch/sparc/SparcSystem.py D src/arch/sparc/system.cc D src/arch/sparc/system.hh M src/arch/x86/SConscript D src/arch/x86/X86System.py M src/arch/x86/pagetable.hh M src/arch/x86/process.cc D src/arch/x86/system.cc D src/arch/x86/system.hh M src/arch/x86/tlb.hh M src/dev/alpha/AlphaBackdoor.py M src/dev/alpha/backdoor.cc M src/dev/alpha/backdoor.hh M src/dev/alpha/tsunami.cc M src/mem/multi_level_page_table.hh M src/sim/SConscript M src/sim/system.hh D src/sim/workload.cc M src/sim/workload.hh 45 files changed, 82 insertions(+), 1,202 deletions(-) diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index bfe4249..b161dad 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -99,7 +99,7 @@ ide = IdeController(disks=[Parent.disk0, Parent.disk2], pci_func=0, pci_dev=0, pci_bus=0) -self = AlphaSystem() +self = System() if not mdesc: # generic system mdesc = SysConfig() @@ -167,7 +167,7 @@ def childImage(self, ci): self.image.child.image_file = ci -self = SparcSystem() +self = System() if not mdesc: # generic system mdesc = SysConfig() @@ -431,7 +431,7 @@ ide = IdeController(disks=[Parent.disk0, Parent.disk2], pci_func=0, pci_dev=0, pci_bus=0) -self = LinuxMipsSystem() +self = System() if not mdesc: # generic system mdesc = SysConfig() @@ -525,7 +525,7 @@ def makeX86System(mem_mode, numCPUs=1, mdesc=None, workload=None, Ruby=False): -self = X86System() +self = System() if workload is None: workload = X86FsWorkload() diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py deleted file mode 100644 index cbce0b2..000 --- a/src/arch/alpha/AlphaSystem.py +++ /dev/null @@ -1,36 +0,0 @@ -# Copyright (c) 2007 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
[gem5-dev] Change in gem5/gem5[master]: riscv: Extract kernel information from System.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/24286 )
Change subject: riscv: Extract kernel information from System.
..
riscv: Extract kernel information from System.
Change-Id: Id2a9aa551e2e4cc2968cc194d0d8387ca8b21c19
---
A src/arch/riscv/RiscvFsWorkload.py
M src/arch/riscv/RiscvSystem.py
M src/arch/riscv/SConscript
A src/arch/riscv/bare_metal/fs_workload.cc
A src/arch/riscv/bare_metal/fs_workload.hh
M src/arch/riscv/faults.cc
A src/arch/riscv/fs_workload.hh
M src/arch/riscv/system.cc
M src/arch/riscv/system.hh
M src/arch/riscv/tlb.cc
10 files changed, 257 insertions(+), 93 deletions(-)
diff --git a/src/arch/riscv/RiscvFsWorkload.py
b/src/arch/riscv/RiscvFsWorkload.py
new file mode 100644
index 000..0537337
--- /dev/null
+++ b/src/arch/riscv/RiscvFsWorkload.py
@@ -0,0 +1,54 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2016 RISC-V Foundation
+# Copyright (c) 2016 The University of Virginia
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Alec Roelke
+# Robert Scheffel
+
+from m5.params import *
+
+from m5.objects.System import System
+from m5.objects.OsKernel import OsKernel
+
+class RiscvFsWorkload(OsKernel):
+type = 'RiscvFsWorkload'
+cxx_class = 'RiscvISA::FsWorkload'
+cxx_header = 'arch/riscv/fs_workload.hh'
+abstract = True
+
+bare_metal = Param.Bool(False, "Using Bare Metal Application?")
+reset_vect = Param.Addr(0x0, 'Reset vector')
+
+
+class RiscvBareMetal(RiscvFsWorkload):
+type = 'RiscvBareMetal'
+cxx_class = 'RiscvISA::BareMetal'
+cxx_header = 'arch/riscv/bare_metal/fs_workload.hh'
+bootloader = Param.String("File, that contains the bootloader code")
+
+bare_metal = True
diff --git a/src/arch/riscv/RiscvSystem.py b/src/arch/riscv/RiscvSystem.py
index ea1defd..2ef4db8 100644
--- a/src/arch/riscv/RiscvSystem.py
+++ b/src/arch/riscv/RiscvSystem.py
@@ -37,14 +37,3 @@
class RiscvSystem(System):
type = 'RiscvSystem'
cxx_header = 'arch/riscv/system.hh'
-bare_metal = Param.Bool(False, "Using Bare Metal Application?")
-reset_vect = Param.Addr(0x0, 'Reset vector')
-load_addr_mask = 0x
-
-
-class BareMetalRiscvSystem(RiscvSystem):
-type = 'BareMetalRiscvSystem'
-cxx_header = 'arch/riscv/bare_metal/system.hh'
-bootloader = Param.String("File, that contains the bootloader code")
-
-bare_metal = True
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 2ddba72..90a956c 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -62,8 +62,9 @@
Source('linux/process.cc')
Source('linux/linux.cc')
-Source('bare_metal/system.cc')
+Source('bare_metal/fs_workload.cc')
+SimObject('RiscvFsWorkload.py')
SimObject('RiscvInterrupts.py')
SimObject('RiscvISA.py')
SimObject('RiscvTLB.py')
diff --git a/src/arch/riscv/bare_metal/fs_workload.cc
b/src/arch/riscv/bare_metal/fs_workload.cc
new file mode 100644
index 000..1ce4f3a
--- /dev/null
+++ b/src/arch/riscv/bare_metal/fs_workload.cc
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2018 TU Dresden
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ *
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix EL2 target exception level for SP alignment fault.
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/24303 )
Change subject: arch-arm: Fix EL2 target exception level for SP alignment
fault.
..
arch-arm: Fix EL2 target exception level for SP alignment fault.
This commit fixes the target exception Level EL2 for alignmemt fault, it
is based on HCR_EL2.tge bit.
Change-Id: Ief78b2aa0c86f1c3d9a5d3ca00121d163a9d6a86
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 5a7b8e8..bd38fdc 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1541,6 +1541,14 @@
SPAlignmentFault::SPAlignmentFault()
{}
+bool
+SPAlignmentFault::routeToHyp(ThreadContext *tc) const
+{
+assert(from64);
+HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+return EL2Enabled(tc) && hcr.tge==1;
+}
+
SystemError::SystemError()
{}
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 3f61bc7..508fd03 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -571,6 +571,7 @@
{
public:
SPAlignmentFault();
+bool routeToHyp(ThreadContext *tc) const override;
};
/// System error (AArch64 only)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24303
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ief78b2aa0c86f1c3d9a5d3ca00121d163a9d6a86
Gerrit-Change-Number: 24303
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero
Gerrit-MessageType: newchange
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