(you can then replace .double with .quad to load your own bit pattern instead of having to work our the desired float, see: https://github.com/cirosantilli/linux-kernel-module-cheat/blob/657c59249e56d861bb0a437a1b1c757797281910/userland/arch/aarch64/gas_data_sizes.S#L26 )
On Mon, Jan 13, 2020 at 10:41 AM Ciro Santilli <[email protected]> wrote: > > There is no silly question. > > I think the easiest thing is to put the desired bit patterns in memory > use LD1 as shown here: > https://github.com/cirosantilli/linux-kernel-module-cheat/blob/657c59249e56d861bb0a437a1b1c757797281910/userland/arch/aarch64/fadd_vector.S#L21 > > This may also be of interest: > https://github.com/cirosantilli/linux-kernel-module-cheat/blob/657c59249e56d861bb0a437a1b1c757797281910/userland/arch/aarch64/gdb_tests/floating_registers.S > > On Mon, Jan 13, 2020 at 3:29 AM Gabe Black <[email protected]> wrote: > > > > Hi folks. I do most of my aarch64 assembly level programming by example, ie > > by just doing what other code I can find is already doing. I'm trying to > > test some code I wrote to checkpoint the FP state in a fast model ARM CPU, > > and to do that I need to load known values into those registers to make > > sure they end up in the right place in the checkpoint. > > > > What assembly instruction should I use to maximally load up those registers > > with a known bit pattern? Ideally it would be something where I could tell > > that the right bits ended up in the right register and in the right part of > > the register. > > > > This particular CPU (CortexA76) does not seem to have SVE, so this would > > need to be a neon type instruction. Sorry for the dumb question, but I > > figure this might be a very easy question for somebody to answer which > > would save me a lot of trial and error trying to find the right instruction > > and syntax to get it going. > > > > Thanks! > > Gabe > > _______________________________________________ > > gem5-dev mailing list > > [email protected] > > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
