[gem5-dev] Change in gem5/gem5[develop]: tests, base: Added GTests for base/amo.hh

2020-03-19 Thread Neil Natekar (Gerrit) 
Neil Natekar has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26944 )



Change subject: tests, base: Added GTests for base/amo.hh
..

tests, base: Added GTests for base/amo.hh

Change-Id: Ia915f9c8bd0732c6c918e8056253bd2fdcdf6b5d
---
M src/base/SConscript
A src/base/amo.test.cc
2 files changed, 234 insertions(+), 0 deletions(-)



diff --git a/src/base/SConscript b/src/base/SConscript
index f2fb91c..beb448a 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -32,6 +32,7 @@
 SimObject('CPA.py')
 Source('cp_annotate.cc')
 SimObject('Graphics.py')
+GTest('amo.test', 'amo.test.cc')
 Source('atomicio.cc')
 GTest('atomicio.test', 'atomicio.test.cc', 'atomicio.cc')
 Source('bitfield.cc')
diff --git a/src/base/amo.test.cc b/src/base/amo.test.cc
new file mode 100644
index 000..14d195a
--- /dev/null
+++ b/src/base/amo.test.cc
@@ -0,0 +1,233 @@
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include 
+
+#include 
+
+#include "base/amo.hh"
+
+void multiply2Op(int *b, int a)
+{
+*b *= a;
+}
+
+void multiply3Op(int *b, int a, int c)
+{
+*b *= a * c;
+}
+
+void addSubColumns(int *b, std::array a, std::array c)
+{
+*b += a[0] + c[0];
+*b -= a[1] + c[1];
+}
+
+TEST(AmoTest, AtomicOpMin)
+{
+// test with ints and strings
+int testIntSmaller = 5;
+int testIntBigger = 15;
+std::string testStringSmaller = "apple";
+std::string testStringBigger = "cat";
+
+TypedAtomicOpFunctor *amoOpInt = new AtomicOpMin(10);
+TypedAtomicOpFunctor *amoOpString =
+new AtomicOpMin("base");
+amoOpInt->execute(&testIntSmaller);
+amoOpInt->execute(&testIntBigger);
+amoOpString->execute(&testStringSmaller);
+amoOpString->execute(&testStringBigger);
+
+EXPECT_EQ(testIntSmaller, 5);
+EXPECT_EQ(testIntBigger, 10);
+EXPECT_EQ(testStringSmaller, "apple");
+EXPECT_EQ(testStringBigger, "base");
+}
+
+TEST(AmoTest, AtomicOpMax)
+{
+int testIntSmaller = 5;
+int testIntBigger = 15;
+std::string testStringSmaller = "apple";
+std::string testStringBigger = "cat";
+
+TypedAtomicOpFunctor *amoOpInt = new AtomicOpMax(10);
+TypedAtomicOpFunctor *amoOpString =
+new AtomicOpMax("base");
+amoOpInt->execute(&testIntSmaller);
+amoOpInt->execute(&testIntBigger);
+amoOpString->execute(&testStringSmaller);
+amoOpString->execute(&testStringBigger);
+
+EXPECT_EQ(testIntSmaller, 10);
+EXPECT_EQ(testIntBigger, 15);
+EXPECT_EQ(testStringSmaller, "base");
+EXPECT_EQ(testStringBigger, "cat");
+}
+
+TEST(AmoTest, AtomicOpDec)
+{
+int testInt = 10;
+char testChar = 'c';
+
+TypedAtomicOpFunctor *amoOpInt = new AtomicOpDec();
+TypedAtomicOpFunctor *amoOpChar = new AtomicOpDec();
+amoOpInt->execute(&testInt);
+amoOpChar->execute(&testChar);
+
+EXPECT_EQ(testInt, 9);
+EXPECT_EQ(testChar, 'b');
+}
+
+TEST(AmoTest, AtomicOpInc)
+{
+int testInt = 10;
+char testChar = 'c';
+
+TypedAtomicOpFunctor *amoOpInt = new AtomicOpInc();
+TypedAtomicOpFunctor *amoOpChar = new AtomicOpInc();
+amoOpInt->execute(&testInt);
+amoOpChar->execute(&testChar);
+
+EXPECT_EQ(testInt, 11);
+EXPECT_EQ(testChar, 'd');
+}
+
+TEST(AmoTest, AtomicOpSub)
+{
+int testInt = 10;
+char testChar = 'c';
+
+TypedAtomicOpFunctor *amoOpInt = new AtomicOpSub(2);
+TypedAtomicOpFunctor *amoOpChar = new AtomicOpSub('a');
+amoOpInt->execute(&testInt);
+amoOpChar->execute(&testChar);
+
+EXPECT_EQ(testInt, 8);
+EXPECT_EQ(testChar, 2);
+}
+
+TEST(AmoTest, AtomicOpAdd)
+{
+int testInt = 10;
+char testChar = 'c';
+
+TypedAtomic

[gem5-dev] Change in gem5/gem5[develop]: util: Add the ability to build a cross GDB to build_cross_gcc.py.

2020-03-19 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26765 )


Change subject: util: Add the ability to build a cross GDB to  
build_cross_gcc.py.

..

util: Add the ability to build a cross GDB to build_cross_gcc.py.

This is a very simple extension to what's already there.

Change-Id: I07e3711244e0de96b215f16ec05c660b19e462b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26765
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Reviewed-by: Bobby R. Bruce 
Maintainer: Gabe Black 
---
M util/build_cross_gcc/build_cross_gcc.py
1 file changed, 44 insertions(+), 1 deletion(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/util/build_cross_gcc/build_cross_gcc.py  
b/util/build_cross_gcc/build_cross_gcc.py

index 9388632..e8497c3 100755
--- a/util/build_cross_gcc/build_cross_gcc.py
+++ b/util/build_cross_gcc/build_cross_gcc.py
@@ -54,6 +54,7 @@
 '''2. gcc''',
 '''3. glibc''',
 '''4. linux kernel''',
+'''5. gdb''',
 '',
 '''
 The entire process can be configured with a series of settings
@@ -373,6 +374,18 @@
 def set_from_args(self, args):
 return self.set_arg(args.linux_src)

+class GdbSourceDir(SourceDirSetting):
+key = 'GDB_SRC_DIR'
+default = None
+pattern = 'gdb-*'
+project = 'gdb'
+
+def add_to_argparser(self, parser):
+parser.add_argument('--gdb-src', help=self.describe())
+
+def set_from_args(self, args):
+return self.set_arg(args.gdb_src)
+
 class Parallelism(Setting):
 key = 'J'
 default = None
@@ -646,10 +659,40 @@
 'make install',
 )

-class StandardCxxLib(Step):
+class BuildGdb(Step):
 number = 7

 def describe(self):
+return 'Build GDB.'
+
+def run(self):
+prefix = Prefix.setting()
+target = Target.setting()
+j = Parallelism.setting()
+source_dir = GdbSourceDir.setting()
+build_dir = setup_build_dir('gdb')
+
+if not all((prefix, target, j, source_dir, build_dir)):
+return False
+
+prefix = prefix.get()
+target = target.get()
+j = j.get()
+source_dir = os.path.abspath(source_dir.get())
+build_dir = os.path.abspath(build_dir)
+
+return run_commands(build_dir,
+'{configure} --prefix={prefix} --target={target} '
+'$MACHTYPE'.format(prefix=prefix, target=target,
+configure=os.path.join(source_dir, 'configure')),
+'make -j{j}'.format(j=j),
+'make install'
+)
+
+class StandardCxxLib(Step):
+number = 8
+
+def describe(self):
 return 'Install the standard C++ library.'

 def run(self):

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I07e3711244e0de96b215f16ec05c660b19e462b5
Gerrit-Change-Number: 26765
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sparc: Add the AT_RANDOM aux vector to the initial stack.

2020-03-19 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26824 )


Change subject: sparc: Add the AT_RANDOM aux vector to the initial stack.
..

sparc: Add the AT_RANDOM aux vector to the initial stack.

This is blindly used by at least modern glibc-s

Change-Id: I175ce5f1495e367badf0fab32f5837e3cdfa955a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26824
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Reviewed-by: Bobby R. Bruce 
Maintainer: Gabe Black 
---
M src/arch/sparc/process.cc
1 file changed, 14 insertions(+), 2 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index 816df4f..c55e9cb 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -251,6 +251,8 @@
 auxv.emplace_back(M5_AT_EGID, egid());
 // Whether to enable "secure mode" in the executable
 auxv.emplace_back(M5_AT_SECURE, 0);
+// The address of 16 "random" bytes.
+auxv.emplace_back(M5_AT_RANDOM, 0);
 }

 // Figure out how big the initial stack needs to be
@@ -262,6 +264,9 @@
 // It's purpose is to let the user space linker examine the original  
file.

 int file_name_size = filename.size() + 1;

+const int numRandomBytes = 16;
+int aux_data_size = numRandomBytes;
+
 int env_data_size = 0;
 for (int i = 0; i < envp.size(); ++i) {
 env_data_size += envp[i].size() + 1;
@@ -303,6 +308,7 @@

 int space_needed =
 info_block_size +
+aux_data_size +
 aux_padding +
 frame_size;

@@ -319,8 +325,8 @@
 IntType file_name_base = sentry_base - file_name_size;
 IntType env_data_base = file_name_base - env_data_size;
 IntType arg_data_base = env_data_base - arg_data_size;
-IntType auxv_array_base = arg_data_base -
-info_block_padding - aux_array_size - aux_padding;
+IntType aux_data_base = arg_data_base - info_block_padding -  
aux_data_size;

+IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
 IntType envp_array_base = auxv_array_base - envp_array_size;
 IntType argv_array_base = envp_array_base - argv_array_size;
 IntType argc_base = argv_array_base - argc_size;
@@ -356,6 +362,12 @@
 // Write the file name
 initVirtMem->writeString(file_name_base, filename.c_str());

+// Fix up the aux vectors which point to data.
+for (auto &aux: auxv) {
+if (aux.type == M5_AT_RANDOM)
+aux.val = aux_data_base;
+}
+
 // Copy the aux stuff
 Addr auxv_array_end = auxv_array_base;
 for (const auto &aux: auxv) {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I175ce5f1495e367badf0fab32f5837e3cdfa955a
Gerrit-Change-Number: 26824
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arm: Use a non-template indexed version of laneView in aapcs32.

2020-03-19 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26834 )


Change subject: arm: Use a non-template indexed version of laneView in  
aapcs32.

..

arm: Use a non-template indexed version of laneView in aapcs32.

The lane number is constant over its lifetime, but is computed with a
variable i which is not a compile time constant. It therefore can't be
used as a template parameter, and should be marked as const and not
constexpr.

Change-Id: Ie0b950311495831d5224a8fb397cf42d5cf5f25b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26834
Reviewed-by: Bobby R. Bruce 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/aapcs32.hh
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index 3e9ad54..bfeb553 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -572,12 +572,12 @@

 constexpr int lane_per_reg = 16 / sizeof(Elem);
 for (int i = 0; i < Count; i++) {
-constexpr int reg = i / lane_per_reg;
-constexpr int lane = i % lane_per_reg;
+const int reg = i / lane_per_reg;
+const int lane = i % lane_per_reg;

 RegId id(VecRegClass, reg);
 auto val = tc->readVecReg(id);
-val.laneView() = ha[i];
+val.laneView(lane) = ha[i];
 tc->setVecReg(id, val);
 }
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie0b950311495831d5224a8fb397cf42d5cf5f25b
Gerrit-Change-Number: 26834
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Convert the annotation methods to take actual arguments.

2020-03-19 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/24114 )


Change subject: base: Convert the annotation methods to take actual  
arguments.

..

base: Convert the annotation methods to take actual arguments.

Feed the arguments in from the decoder.

Change-Id: Ie2dcd09320a5de02bb91b8743fc643c446e506e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24114
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
---
M src/base/cp_annotate.cc
M src/base/cp_annotate.hh
2 files changed, 74 insertions(+), 91 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/cp_annotate.cc b/src/base/cp_annotate.cc
index 86416dc..472efa7 100644
--- a/src/base/cp_annotate.cc
+++ b/src/base/cp_annotate.cc
@@ -155,12 +155,11 @@
 }

 void
-CPA::swSmBegin(ThreadContext *tc)
+CPA::swSmBegin(ThreadContext *tc, Addr sm_string, int32_t sm_id, int32_t  
flags)

 {
 if (!enabled())
 return;

-Arguments args(tc);
 std::string st;
 Addr junk;
 char sm[50];
@@ -168,7 +167,7 @@
 debugSymbolTable->findNearestSymbol(
 tc->readIntReg(ReturnAddressReg), st, junk);

-tc->getVirtProxy().readString(sm, args[0], 50);
+tc->getVirtProxy().readString(sm, sm_string, 50);
 System *sys = tc->getSystemPtr();
 StringWrap name(sys->name());

@@ -176,9 +175,9 @@
 warn("Got null SM at tick %d\n", curTick());

 int sysi = getSys(sys);
-int smi = getSm(sysi, sm, args[1]);
+int smi = getSm(sysi, sm, sm_id);
 DPRINTF(Annotate,  "Starting machine: %s(%d) sysi: %d id: %#x\n", sm,
-smi, sysi, args[1]);
+smi, sysi, sm_id);
 DPRINTF(Annotate, "smMap[%d] = %d, %s, %#x\n", smi,
 smMap[smi-1].first, smMap[smi-1].second.first,
 smMap[smi-1].second.second);
@@ -187,12 +186,11 @@
 StackId sid = StackId(sysi, frame);

 // check if we need to link to the previous state machine
-int flags = args[2];
 if (flags & FL_LINK) {
 if (smStack[sid].size()) {
 int prev_smi = smStack[sid].back();
 DPRINTF(Annotate, "Linking from %d to state machine %s(%d)  
[%#x]\n",

-prev_smi, sm, smi, args[1]);
+prev_smi, sm, smi, sm_id);

 if (lnMap[smi])
 DPRINTF(Annotate, "LnMap already contains entry for %d  
of %d\n",

@@ -203,7 +201,7 @@
 add(OP_LINK, FL_NONE, tc->contextId(), prev_smi, smi);
 } else {
 DPRINTF(Annotate, "Not Linking to state machine %s(%d)  
[%#x]\n",

-sm, smi, args[1]);
+sm, smi, sm_id);
 }
 }

@@ -247,14 +245,13 @@
 }

 void
-CPA::swSmEnd(ThreadContext *tc)
+CPA::swSmEnd(ThreadContext *tc, Addr sm_string)
 {
 if (!enabled())
 return;

-Arguments args(tc);
 char sm[50];
-tc->getVirtProxy().readString(sm, args[0], 50);
+tc->getVirtProxy().readString(sm, sm_string, 50);
 System *sys = tc->getSystemPtr();
 doSwSmEnd(sys, tc->contextId(), sm, getFrame(tc));
 }
@@ -315,21 +312,20 @@


 void
-CPA::swExplictBegin(ThreadContext *tc)
+CPA::swExplictBegin(ThreadContext *tc, int32_t flags, Addr st_string)
 {
 if (!enabled())
 return;

-Arguments args(tc);
 char st[50];
-tc->getVirtProxy().readString(st, args[1], 50);
+tc->getVirtProxy().readString(st, st_string, 50);

 StringWrap name(tc->getSystemPtr()->name());
 DPRINTF(Annotate, "Explict begin of state %s\n", st);
-uint32_t flags = args[0];
 if (flags & FL_BAD)
 warn("BAD state encountered: at cycle %d: %s\n", curTick(), st);
-swBegin(tc->getSystemPtr(), tc->contextId(), st, getFrame(tc), true,  
args[0]);

+swBegin(tc->getSystemPtr(), tc->contextId(),
+st, getFrame(tc), true, flags);
 }

 void
@@ -418,16 +414,13 @@
 }

 void
-CPA::swQ(ThreadContext *tc)
+CPA::swQ(ThreadContext *tc, Addr id, Addr q_string, int32_t count)
 {
 if (!enabled())
 return;

 char q[50];
-Arguments args(tc);
-uint64_t id = args[0];
-tc->getVirtProxy().readString(q, args[1], 50);
-int32_t count = args[2];
+tc->getVirtProxy().readString(q, q_string, 50);
 System *sys = tc->getSystemPtr();

 int sysi = getSys(sys);
@@ -449,16 +442,13 @@
 }

 void
-CPA::swDq(ThreadContext *tc)
+CPA::swDq(ThreadContext *tc, Addr id, Addr q_string, int32_t count)
 {
 if (!enabled())
 return;

 char q[50];
-Arguments args(tc);
-uint64_t id = args[0];
-tc->getVirtProxy().readString(q, args[1], 50);
-int32_t count = args[2];
+tc->getVirtProxy().readString(q, q_string, 50);
 System *sys = tc->getSystemPtr();

 int sysi = getSys(sys);
@@ -478,17 +468,14 @@
 }

 void
-CPA::swPq(ThreadContext *tc)
+CPA::swPq(T

[gem5-dev] Change in gem5/gem5[develop]: arm, kern: Use GuestABI to call printk from the kernel.

2020-03-19 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/24113 )


Change subject: arm,kern: Use GuestABI to call printk from the kernel.
..

arm,kern: Use GuestABI to call printk from the kernel.

Change-Id: I07b0f1c01f5ec8d6761903fa4aa15b9e8ae35069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24113
Tested-by: kokoro 
Maintainer: Giacomo Travaglini 
Reviewed-by: Bobby R. Bruce 
---
M src/arch/arm/linux/fs_workload.cc
M src/arch/arm/linux/fs_workload.hh
M src/kern/linux/events.cc
M src/kern/linux/events.hh
M src/kern/linux/printk.cc
M src/kern/linux/printk.hh
6 files changed, 230 insertions(+), 197 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/linux/fs_workload.cc  
b/src/arch/arm/linux/fs_workload.cc

index c21ce09..fe023cc 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -168,6 +168,7 @@

 FsLinux::~FsLinux()
 {
+delete debugPrintk;
 delete skipUDelay;
 delete skipConstUDelay;
 delete kernelOops;
@@ -237,7 +238,13 @@
 "__const_udelay", "__const_udelay", 1000, 107374);
 }

-debugPrintk = addKernelFuncEvent>("dprintk");
+if (highestELIs64()) {
+debugPrintk = addKernelFuncEvent<
+DebugPrintk>("dprintk");
+} else {
+debugPrintk = addKernelFuncEvent<
+DebugPrintk>("dprintk");
+}
 }

 void
diff --git a/src/arch/arm/linux/fs_workload.hh  
b/src/arch/arm/linux/fs_workload.hh

index 73a006b..6ab3c6c 100644
--- a/src/arch/arm/linux/fs_workload.hh
+++ b/src/arch/arm/linux/fs_workload.hh
@@ -45,7 +45,10 @@
 #include 
 #include 

+#include "arch/arm/aapcs32.hh"
+#include "arch/arm/aapcs64.hh"
 #include "arch/arm/fs_workload.hh"
+#include "arch/arm/system.hh"
 #include "base/output.hh"
 #include "kern/linux/events.hh"
 #include "params/ArmFsLinux.hh"
@@ -54,7 +57,19 @@
 namespace ArmISA
 {

-class DumpStats;
+class SkipFuncLinux32 : public SkipFunc
+{
+  public:
+using SkipFunc::SkipFunc;
+using ABI = Aapcs32Vfp;
+};
+
+class SkipFuncLinux64 : public SkipFunc
+{
+  public:
+using SkipFunc::SkipFunc;
+using ABI = Aapcs64;
+};

 class FsLinux : public ArmISA::FsWorkload
 {
diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc
index be72671..e576a39 100644
--- a/src/kern/linux/events.cc
+++ b/src/kern/linux/events.cc
@@ -47,9 +47,7 @@
 #include "base/trace.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
-#include "debug/DebugPrintf.hh"
 #include "kern/linux/helpers.hh"
-#include "kern/linux/printk.hh"
 #include "kern/system_events.hh"
 #include "sim/arguments.hh"
 #include "sim/core.hh"
@@ -59,18 +57,6 @@
 {

 void
-onDebugPrintk(ThreadContext *tc)
-{
-if (DTRACE(DebugPrintf)) {
-std::stringstream ss;
-Arguments args(tc);
-Printk(ss, args);
-StringWrap name(tc->getSystemPtr()->name() + ".dprintk");
-DPRINTFN("%s", ss.str());
-}
-}
-
-void
 DmesgDump::process(ThreadContext *tc)
 {
 inform("Dumping kernel dmesg buffer to %s...\n", fname);
diff --git a/src/kern/linux/events.hh b/src/kern/linux/events.hh
index b4ee6db..c5a297b 100644
--- a/src/kern/linux/events.hh
+++ b/src/kern/linux/events.hh
@@ -41,13 +41,20 @@
 #ifndef __KERN_LINUX_EVENTS_HH__
 #define __KERN_LINUX_EVENTS_HH__

+#include 
+#include 
+
+#include "base/trace.hh"
+#include "debug/DebugPrintf.hh"
+#include "kern/linux/printk.hh"
 #include "kern/system_events.hh"
+#include "sim/guest_abi.hh"
+
+class ThreadContext;

 namespace Linux
 {

-void onDebugPrintk(ThreadContext *tc);
-
 template 
 class DebugPrintk : public Base
 {
@@ -56,7 +63,16 @@
 void
 process(ThreadContext *tc) override
 {
-onDebugPrintk(tc);
+if (DTRACE(DebugPrintf)) {
+std::string str;
+std::function func =
+[&str](ThreadContext *tc, Addr format_ptr,
+PrintkVarArgs args) -> int {
+return printk(str, tc, format_ptr, args);
+};
+invokeSimcall(tc, func);
+DPRINTFN("%s", str);
+}
 Base::process(tc);
 }
 };
diff --git a/src/kern/linux/printk.cc b/src/kern/linux/printk.cc
index 7b9e3c2..f6661df 100644
--- a/src/kern/linux/printk.cc
+++ b/src/kern/linux/printk.cc
@@ -31,168 +31,174 @@
 #include 

 #include 
+#include 
+#include 

-#include "base/trace.hh"
 #include "cpu/thread_context.hh"
-#include "sim/arguments.hh"
+#include "mem/port_proxy.hh"

-using namespace std;
-
-
-void
-Printk(stringstream &out, Arguments args)
+namespace Linux
 {
-char *p = (char *)args++;
+
+int
+printk(std::string &str, ThreadContext *tc, Addr format_ptr,
+PrintkVarArgs args)
+{
+std::string format;
+std::ostringstream out;
+tc->getVirtProxy().readString(format, format_p

[gem5-dev] Change in gem5/gem5[develop]: util: Add a script to help build cross compilers.

2020-03-19 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26763 )


Change subject: util: Add a script to help build cross compilers.
..

util: Add a script to help build cross compilers.

Cross compilers are very useful when working with gem5. The how-to this
script is based on assumed the compiler was targeting linux, so there
isn't any support for compilers targeting other or no OS. That might be
possible to add in the future.

Change-Id: I2cb30ecbdd4c6292146ea64940348c24385046f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26763
Reviewed-by: Bobby R. Bruce 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
A util/build_cross_gcc/build_cross_gcc.py
1 file changed, 793 insertions(+), 0 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/build_cross_gcc/build_cross_gcc.py  
b/util/build_cross_gcc/build_cross_gcc.py

new file mode 100755
index 000..9388632
--- /dev/null
+++ b/util/build_cross_gcc/build_cross_gcc.py
@@ -0,0 +1,793 @@
+#! /usr/bin/env python
+# Copyright 2020 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import abc
+import argparse
+import glob
+import multiprocessing
+import os
+import os.path
+import pickle
+import shutil
+import six
+import subprocess
+import textwrap
+
+SETTINGS_FILE = '.build_cross_gcc.settings'
+LOG_FILE = 'build_cross_gcc.log'
+
+all_settings = {}
+all_steps = {}
+
+description_paragraphs = [
+'''
+This script helps automate building a gcc based cross compiler.
+The process is broken down into a series of steps which can be
+executed one at a time or in arbtitrary sequences. It's assumed  
that

+you've already downloaded the following sources into the current
+directory:''',
+'',
+'''1. binutils''',
+'''2. gcc''',
+'''3. glibc''',
+'''4. linux kernel''',
+'',
+'''
+The entire process can be configured with a series of settings
+which are stored in a config file called {settings_file}. These
+settings can generally also be set from the command line, and at  
run

+time using step 0 of the process. Many will set themselves to
+reasonable defaults if no value was loaded from a previous
+configuration or a saved settings file.''',
+'',
+'''
+Prebaked config options can be loaded in from an external file to
+make it easier to build particular cross compilers without having  
to

+mess with a lot of options.'''
+'',
+'''
+When settings are listed, any setting which has a value which has
+failed validation or which hasn't been set and doesn't have a
+reasonable default will be marked with a X in the far left hand
+column. Settings will generally refuse to be set to invalid values,
+unless they were like that by default and the user refused to  
correct

+them.''',
+'',
+'''This script is based on the excellent how-to here:''',
+'''https://preshing.com/20141119/how-to-build-a-gcc-cross-compiler/''',
+'',
+'''
+Please view that webpage for a detailed explanation of what this
+script does.'''
+]
+
+def help_text_wrapper(text):
+width = shutil.get_terminal_size().columns
+text = textwrap.dedent(text)

[gem5-dev] Change in gem5/gem5[develop]: tests: Add --bin-path option to insttest regressions

2020-03-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26483 )


Change subject: tests: Add --bin-path option to insttest regressions
..

tests: Add --bin-path option to insttest regressions

Change-Id: I229f37782b1c3650dc71ee481823b41f6f67e590
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26483
Maintainer: Bobby R. Bruce 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M tests/gem5/insttest_se/test.py
1 file changed, 7 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/insttest_se/test.py b/tests/gem5/insttest_se/test.py
index e81f943..c3fa322 100644
--- a/tests/gem5/insttest_se/test.py
+++ b/tests/gem5/insttest_se/test.py
@@ -46,14 +46,19 @@
 'sparc' : ('linux',)
 }

+if config.bin_path:
+base_path = config.bin_path
+else:
+base_path = joinpath(absdirpath(__file__), '..', 'test-progs')
+
 urlbase = 'http://dist.gem5.org/dist/current/test-progs/insttest/bin/'
 for isa in test_progs:
 for binary in test_progs[isa]:
 for  operating_s in supported_os[isa]:
 import os
 url = urlbase + isa + '/' + operating_s + '/' + binary
-path = joinpath(absdirpath(__file__), '..', 'test-progs',  
binary,

-'bin', isa, operating_s)
+path = joinpath(base_path, isa, operating_s, binary)
+
 try:
 program = DownloadedProgram(url, path, binary)
 except:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I229f37782b1c3650dc71ee481823b41f6f67e590
Gerrit-Change-Number: 26483
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix ArmSystem::_resetAddr evalutation

2020-03-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26723 )


Change subject: arch-arm: Fix ArmSystem::_resetAddr evalutation
..

arch-arm: Fix ArmSystem::_resetAddr evalutation

With:

https://gem5-review.googlesource.com/c/public/gem5/+/26466

The ArmSystem reset address (_resetAddr) is always forced by the
workload:

 _resetAddr = workload->entry

So there is no possibility to manually specify a reset address.

This was not the case before:
The resetAddr was forced only if auto_reset_addr was true or if there
was an associated bootloader to the kernel image. In that case even if
auto_reset_addr was false, the reset address was determined by the
bootloader entry.
This was also not ideal (but it was working)

This patch is cleaning all of this:

If you want to have automatic detection (recommended), you would need to
set auto_reset_addr (now turned to true by default).  This will allow to
keep most fs script untouched.  If you don't want to use automatic
detection, set auto_reset_addr to False and provide your own reset
address.

Change-Id: I5d7a55fd9060b9973c7d5b5542bd199950e1073e
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26723
Tested-by: kokoro 
Reviewed-by: Gabe Black 
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/fs_workload.cc
M src/arch/arm/fs_workload.hh
M src/arch/arm/system.cc
4 files changed, 39 insertions(+), 18 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 1b5fc90..07fdad6 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -58,7 +58,7 @@
 have_lpae = Param.Bool(True, "True if LPAE is implemented")
 reset_addr = Param.Addr(0x0,
 "Reset address (ARMv8)")
-auto_reset_addr = Param.Bool(False,
+auto_reset_addr = Param.Bool(True,
 "Determine reset address from kernel entry point if no boot  
loader")

 highest_el_is_64 = Param.Bool(False,
 "True if the register width of the highest implemented exception  
level "

diff --git a/src/arch/arm/fs_workload.cc b/src/arch/arm/fs_workload.cc
index b3dd6b5..3d81156 100644
--- a/src/arch/arm/fs_workload.cc
+++ b/src/arch/arm/fs_workload.cc
@@ -69,7 +69,9 @@
 }
 }

-FsWorkload::FsWorkload(Params *p) : OsKernel(*p)
+FsWorkload::FsWorkload(Params *p)
+  : OsKernel(*p),
+kernelEntry((entry & loadAddrMask) + loadAddrOffset)
 {
 bootLoaders.reserve(p->boot_loader.size());
 for (const auto &bl : p->boot_loader) {
@@ -93,7 +95,6 @@
 if (bootldr) {
 bootldr->loadGlobalSymbols(debugSymbolTable);

-entry = bootldr->entryPoint();
 _highestELIs64 = (bootldr->getArch() == ObjectFile::Arm64);
 } else {
 _highestELIs64 = (obj->getArch() == ObjectFile::Arm64);
@@ -116,8 +117,6 @@

 auto *arm_sys = dynamic_cast(system);

-Addr kernel_entry = (obj->entryPoint() & loadAddrMask) +  
loadAddrOffset;

-
 if (bootldr) {
 bool is_gic_v2 =
  
arm_sys->getGIC()->supportsVersion(BaseGic::GicVersion::GIC_V2);

@@ -136,12 +135,12 @@

 for (auto tc: arm_sys->threadContexts) {
 if (!arm_sys->highestELIs64())
-tc->setIntReg(3, kernel_entry);
+tc->setIntReg(3, kernelEntry);
 if (is_gic_v2)
 tc->setIntReg(4, arm_sys->params()->gic_cpu_addr);
 tc->setIntReg(5, arm_sys->params()->flags_addr);
 }
-inform("Using kernel entry physical address at %#x\n",  
kernel_entry);
+inform("Using kernel entry physical address at %#x\n",  
kernelEntry);

 } else {
 // Set the initial PC to be at start of the kernel code
 if (!arm_sys->highestELIs64())
@@ -160,6 +159,16 @@
 return nullptr;
 }

+Addr
+FsWorkload::resetAddr() const
+{
+if (bootldr) {
+return bootldr->entryPoint();
+} else {
+return kernelEntry;
+}
+}
+
 } // namespace ArmISA

 ArmISA::FsWorkload *
diff --git a/src/arch/arm/fs_workload.hh b/src/arch/arm/fs_workload.hh
index 5e97bba..6e1af08 100644
--- a/src/arch/arm/fs_workload.hh
+++ b/src/arch/arm/fs_workload.hh
@@ -76,6 +76,13 @@
 bool _highestELIs64 = true;

 /**
+ * This differs from entry since it takes into account where
+ * the kernel is loaded in memory (with loadAddrMask and
+ * loadAddrOffset).
+ */
+Addr kernelEntry = 0;
+
+/**
  * Get a boot loader that matches the kernel.
  *
  * @param obj Kernel binary
@@ -96,6 +103,14 @@

 void initState() override;

+/**
+ * Returns the reset address to be used by an ArmSystem.
+ * It the workload is using a bootloader, it will return
+ * the bootloader entry point.
+ * @returns Arm reset address
+ */
+Addr rese

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: SMMUv3, single interconnect attachment

2020-03-19 Thread Adrian Herrera (Gerrit) 
Adrian Herrera has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26923 )


Change subject: dev-arm: SMMUv3, single interconnect attachment
..

dev-arm: SMMUv3, single interconnect attachment

The attachment (port binding) of the SMMUv3 master and control
ports is independent of the connection of device masters to it.

This behaviour is now moved from SMMUv3::connect to
RealView::attachSmmu, as it is a responsibility of the Platform
designer.

This fixes crashes when connecting multiple device masters.

Change-Id: If1e8f55d51876fe761f881e3044ffec637c21b09
Reviewed-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26923
Maintainer: Giacomo Travaglini 
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

---
M src/dev/arm/RealView.py
M src/dev/arm/SMMUv3.py
2 files changed, 6 insertions(+), 6 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 40ed468..0eaeb82 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1075,10 +1075,13 @@

 self.smmu = SMMUv3(reg_map=AddrRange(0x2b40, size=0x0002))

+self.smmu.master = bus.slave
+self.smmu.control = bus.master
+
 dma_ports = []
 for dev in devices:
 self._attach_device(dev, bus, dma_ports)
-self.smmu.connect(dev, bus)
+self.smmu.connect(dev)

 def setupBootLoader(self, cur_sys, boot_loader):
 super(VExpress_GEM5_Base, self).setupBootLoader(
diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index 9d50540..5be09de 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2013, 2018-2019 ARM Limited
+# Copyright (c) 2013, 2018-2020 ARM Limited
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -182,7 +182,7 @@
 node.appendPhandle(self)
 yield node

-def connect(self, device, bus):
+def connect(self, device):
 """
 Helper method used to connect the SMMU. The master could
 be either a dma port (if the SMMU is attached directly to a
@@ -190,9 +190,6 @@
 is attached to a bridge).
 """

-self.master = bus.slave
-self.control = bus.master
-
 slave_interface = SMMUv3SlaveInterface()

 if hasattr(device, "master"):

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If1e8f55d51876fe761f881e3044ffec637c21b09
Gerrit-Change-Number: 26923
Gerrit-PatchSet: 2
Gerrit-Owner: Adrian Herrera 
Gerrit-Reviewer: Adrian Herrera 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-CC: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: SMMUv3, single interconnect attachment

2020-03-19 Thread Adrian Herrera (Gerrit) 

Hello Giacomo Travaglini,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/26923

to review the following change.


Change subject: dev-arm: SMMUv3, single interconnect attachment
..

dev-arm: SMMUv3, single interconnect attachment

The attachment (port binding) of the SMMUv3 master and control
ports is independent of the connection of device masters to it.

This behaviour is now moved from SMMUv3::connect to
RealView::attachSmmu, as it is a responsibility of the Platform
designer.

This fixes crashes when connecting multiple device masters.

Change-Id: If1e8f55d51876fe761f881e3044ffec637c21b09
Reviewed-by: Giacomo Travaglini 
---
M src/dev/arm/RealView.py
M src/dev/arm/SMMUv3.py
2 files changed, 6 insertions(+), 6 deletions(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 40ed468..0eaeb82 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1075,10 +1075,13 @@

 self.smmu = SMMUv3(reg_map=AddrRange(0x2b40, size=0x0002))

+self.smmu.master = bus.slave
+self.smmu.control = bus.master
+
 dma_ports = []
 for dev in devices:
 self._attach_device(dev, bus, dma_ports)
-self.smmu.connect(dev, bus)
+self.smmu.connect(dev)

 def setupBootLoader(self, cur_sys, boot_loader):
 super(VExpress_GEM5_Base, self).setupBootLoader(
diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index 9d50540..5be09de 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2013, 2018-2019 ARM Limited
+# Copyright (c) 2013, 2018-2020 ARM Limited
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -182,7 +182,7 @@
 node.appendPhandle(self)
 yield node

-def connect(self, device, bus):
+def connect(self, device):
 """
 Helper method used to connect the SMMU. The master could
 be either a dma port (if the SMMU is attached directly to a
@@ -190,9 +190,6 @@
 is attached to a bridge).
 """

-self.master = bus.slave
-self.control = bus.master
-
 slave_interface = SMMUv3SlaveInterface()

 if hasattr(device, "master"):

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If1e8f55d51876fe761f881e3044ffec637c21b09
Gerrit-Change-Number: 26923
Gerrit-PatchSet: 1
Gerrit-Owner: Adrian Herrera 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Implement Virtual Memory Area API

2020-03-19 Thread Matthew Poremba (Gerrit) 
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25365 )


Change subject: sim-se: Implement Virtual Memory Area API
..

sim-se: Implement Virtual Memory Area API

Virtual memory areas are used to track regions of memory which may
change over the course of execution, such as heap, stack, and mmap. It
is a high-level mimicry of Linux' memory management. VMAs are intended
to be used to support lazy allocation of physical pages to valid VMAs
as the virtual addresses are touched. Lazy allocation increases speed
of simulation for SE mode processes which, for example, mmap large
files.

The VMAs can also be queried to generate a map of the process' memory
which is used in some libraries such as pthreads.

This changeset only adds APIs for virtual memory areas. These are used
in a subsequent changeset.

Change-Id: Ibbdce5be79a95e3231d2e1c9ee8f397b4503f0fb
Signed-off-by: Brandon Potter 
Signed-off-by: Michael LeBeane 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25365
Reviewed-by: Giacomo Travaglini 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/SConscript
A src/sim/vma.cc
A src/sim/vma.hh
3 files changed, 355 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/SConscript b/src/sim/SConscript
index 30f0487..06b0822 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -90,6 +90,7 @@
 Source('pseudo_inst.cc')
 Source('syscall_emul.cc')
 Source('syscall_desc.cc')
+Source('vma.cc')

 if env['TARGET_ISA'] != 'x86':
 Source('microcode_rom.cc')
@@ -117,5 +118,6 @@
 DebugFlag('ClockDomain')
 DebugFlag('VoltageDomain')
 DebugFlag('DVFS')
+DebugFlag('Vma')

 CompoundFlag('SyscallAll', [ 'SyscallBase', 'SyscallVerbose'])
diff --git a/src/sim/vma.cc b/src/sim/vma.cc
new file mode 100644
index 000..6f6306c
--- /dev/null
+++ b/src/sim/vma.cc
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2017-2020 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sim/vma.hh"
+
+#include 
+#include 
+
+#include "base/types.hh"
+#include "config/the_isa.hh"
+
+void
+VMA::fillMemPages(Addr start, Addr size, PortProxy &port) const
+{
+auto offset = start - _addrRange.start();
+
+/**
+ * Try to copy a full page, but don't overrun the size of the file.
+ */
+if (offset < _hostBufLen) {
+auto size = std::min(_hostBufLen - offset, _pageBytes);
+port.writeBlob(start, (uint8_t*)_hostBuf + offset, size);
+}
+}
+
+bool
+VMA::isStrictSuperset(const AddrRange &r) const
+{
+return (r.start() > _addrRange.start() && r.end() < _addrRange.end());
+}
+
+void
+VMA::sliceRegionRight(Addr slice_addr)
+{
+if (hasHostBuf()) {
+auto nonoverlap_len = slice_addr - _addrRange.start();
+_hostBufLen = std::min(_hostBufLen, nonoverlap_len);
+}
+
+_addrRange = AddrRange(_addrRange.start(), slice_addr);
+
+DPRINTF(Vma, "slice right vma start %#x end %#x\n", _addrRange.start(),
+_addrRange.end());
+
+sanityCheck();
+}
+
+void
+VMA::sliceRegionLeft(Addr slice_addr)
+{
+if (hasHostBuf()) {
+auto overlap_len = slice_addr - _addrRange.start();
+
+if (overlap_len >= _hostBufLen) {
+_hostBufLe

Re: [gem5-dev] SE and modeling page access

2020-03-19 Thread Gabe Black 
In this case I think the translation is doing what it should and what you
want, but when the mappings are set up in the first place they aren't being
marked as read only, or if they are that marking isn't making it into the
TLB. I think it's most likely the loader and/or the process setup code
isn't doing anything special for read only segments and is just mapping
them in as normal. Most of the time it doesn't matter, so I don't think
anyone has put in serious effort to make sure that's wired up correctly.

Gabe

On Thu, Mar 19, 2020 at 2:58 AM Boris Shingarov 
wrote:

> To add to my previous message re: "buried very far behind the
> functionality of the MMU", I wouldn't say the old SE address translation
> went very far in terms of basic fidelity, and I am wondering whether the
> new design is making things better.
>
> For example.  Consider the following:
>
> char *hello = "Hello";
> main() {
>   hello[0] = 'A';
>   return hello[0];
> }
>
> This will compile to something like
>
> .section rodata
> hello:
>   .string "Hello"
>
> On every machine I tried this (of various ISAs including ppc32, mips32,
> amd64 and riscv64), the segment gets loaded into a R/O page, resulting in
> segfault.  gem5's SE treats all memory as R/W, so the above program happily
> exits with code 65.
>
> For me, this has been a problem for a while (illegal page access is one of
> the most critical elements of our guest workload), so I've been doing
> various workarounds but have always looking towards one day implementing a
> trap returning an actual "S05" to the controlling GDB.  So I'd like to
> understand.  Is this latest change, in tune with allowing to mark those
> pages that are marked r/o in the ELF as r/o for the proxy's translation?
> In which place in the code should this marking be added?
>
>
>
>
> ___
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Re: [gem5-dev] Page tables in the new SE translating proxy

2020-03-19 Thread Boris Shingarov 
Thanks Gabe -- that was easy!


-"gem5-dev"  wrote: -
To: "gem5 Developer List" 
From: "Gabe Black" 
Sent by: "gem5-dev" 
Date: 03/19/2020 05:34AM
Subject: Re: [gem5-dev] Page tables in the new SE translating proxy

Hi Boris. If you need to get at the page table, you should be able to use
tc->getProcessPtr() and then access it from the process object. That's what
the SETranslatingPortProxy was doing.

Gabe

On Thu, Mar 19, 2020 at 2:31 AM Boris Shingarov 
wrote:

> Gabe,
>
> I must confess the new concept how the SE translating proxy is supposed to
> work in the new version, is escaping me.
>
> Here is what I am trying to do:  I have a non-standard extension to the
> GDB RSP protocol which allows the gdb client to read/write the inferior's
> memory without sending M packets over the RSP socket, by SHMEM IPC with the
> backing store in gem5.  For that, the GDB client needs to know which
> virtual addresses in the guest map to which backing store address.
>
> In the old SETranslatingProxy this was easy: the pTable contained exactly
> that.  See
>
> https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_shingarov_gem5_commit_b21074a9835ebe52e8f023e588bcad6a608d738e&d=DwIGaQ&c=sPZ6DeHLiehUHQWKIrsNwWp3t7snrE-az24ztT0w7Jc&r=ecC5uu6ubGhPt6qQ8xWcSQh1QUJ8B1-CG4B9kRM0nd4&m=Cdy7Zi-4Jya7noa139CDOG5_L3JTAAiqqAx6SBbx1_8&s=M7UCkltnDUGWnJLy-l7_pkxGKiP74Ensk-IG60aC3t0&e=
>
> Now with the new design, I am scratching my head how to do something
> equivalent.  It looks like the translation is buried very far behind the
> functionality of the MMU.  Do you think there is still a way to get at it?
>
> Boris
>
>
>
>
>
>
> ___
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[gem5-dev] SE and modeling page access

2020-03-19 Thread Boris Shingarov 
To add to my previous message re: "buried very far behind the functionality of 
the MMU", I wouldn't say the old SE address translation went very far in terms 
of basic fidelity, and I am wondering whether the new design is making things 
better.

For example.  Consider the following:

char *hello = "Hello";
main() {
  hello[0] = 'A';
  return hello[0];
}

This will compile to something like

.section rodata
hello:
  .string "Hello"

On every machine I tried this (of various ISAs including ppc32, mips32, amd64 
and riscv64), the segment gets loaded into a R/O page, resulting in segfault.  
gem5's SE treats all memory as R/W, so the above program happily exits with 
code 65.

For me, this has been a problem for a while (illegal page access is one of the 
most critical elements of our guest workload), so I've been doing various 
workarounds but have always looking towards one day implementing a trap 
returning an actual "S05" to the controlling GDB.  So I'd like to understand.  
Is this latest change, in tune with allowing to mark those pages that are 
marked r/o in the ELF as r/o for the proxy's translation?  In which place in 
the code should this marking be added?




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Re: [gem5-dev] Page tables in the new SE translating proxy

2020-03-19 Thread Gabe Black 
Hi Boris. If you need to get at the page table, you should be able to use
tc->getProcessPtr() and then access it from the process object. That's what
the SETranslatingPortProxy was doing.

Gabe

On Thu, Mar 19, 2020 at 2:31 AM Boris Shingarov 
wrote:

> Gabe,
>
> I must confess the new concept how the SE translating proxy is supposed to
> work in the new version, is escaping me.
>
> Here is what I am trying to do:  I have a non-standard extension to the
> GDB RSP protocol which allows the gdb client to read/write the inferior's
> memory without sending M packets over the RSP socket, by SHMEM IPC with the
> backing store in gem5.  For that, the GDB client needs to know which
> virtual addresses in the guest map to which backing store address.
>
> In the old SETranslatingProxy this was easy: the pTable contained exactly
> that.  See
>
> https://github.com/shingarov/gem5/commit/b21074a9835ebe52e8f023e588bcad6a608d738e
>
> Now with the new design, I am scratching my head how to do something
> equivalent.  It looks like the translation is buried very far behind the
> functionality of the MMU.  Do you think there is still a way to get at it?
>
> Boris
>
>
>
>
>
>
> ___
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[gem5-dev] Page tables in the new SE translating proxy

2020-03-19 Thread Boris Shingarov 
Gabe,

I must confess the new concept how the SE translating proxy is supposed to work 
in the new version, is escaping me.

Here is what I am trying to do:  I have a non-standard extension to the GDB RSP 
protocol which allows the gdb client to read/write the inferior's memory 
without sending M packets over the RSP socket, by SHMEM IPC with the backing 
store in gem5.  For that, the GDB client needs to know which virtual addresses 
in the guest map to which backing store address.

In the old SETranslatingProxy this was easy: the pTable contained exactly that. 
 See
https://github.com/shingarov/gem5/commit/b21074a9835ebe52e8f023e588bcad6a608d738e

Now with the new design, I am scratching my head how to do something 
equivalent.  It looks like the translation is buried very far behind the 
functionality of the MMU.  Do you think there is still a way to get at it?

Boris






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[gem5-dev] Change in gem5/gem5[develop]: arch, cpu, mem, sim: Reimplement the SE translating proxy using the FS one.

2020-03-19 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26550 )


Change subject: arch,cpu,mem,sim: Reimplement the SE translating proxy  
using the FS one.

..

arch,cpu,mem,sim: Reimplement the SE translating proxy using the FS one.

The only functional difference between them was that the SE one might
have optionally fixed up missing translations for demand paging.

This lets us get rid of some code recreating the proxy ports in
setProcessPtr since the SE translating port no longer keeps a copy of
the process object pointer.

Change-Id: Id97df1874f1de138ffd4f2dbb5846dda79d9e4ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26550
Tested-by: kokoro 
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
---
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/process.cc
M src/arch/mips/process.cc
M src/arch/power/process.cc
M src/arch/riscv/process.cc
M src/arch/sparc/process.cc
M src/arch/x86/process.cc
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
M src/mem/fs_translating_port_proxy.cc
M src/mem/fs_translating_port_proxy.hh
M src/mem/se_translating_port_proxy.cc
M src/mem/se_translating_port_proxy.hh
M src/sim/process.cc
M src/sim/process.hh
15 files changed, 122 insertions(+), 216 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc  
b/src/arch/arm/fastmodel/iris/thread_context.cc

index 85171fc..516565e 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -410,8 +410,7 @@
 virtProxy.reset(new FSTranslatingPortProxy(tc));
 } else {
 assert(!virtProxy);
-virtProxy.reset(new SETranslatingPortProxy(
-_cpu->getSendFunctional(), getProcessPtr(),
+virtProxy.reset(new SETranslatingPortProxy(this,
 SETranslatingPortProxy::NextPage));
 }
 }
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 9cfa431..3d041ee 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -404,16 +404,16 @@

 //Write out the sentry void *
 IntType sentry_NULL = 0;
-initVirtMem.writeBlob(sentry_base, &sentry_NULL, sentry_size);
+initVirtMem->writeBlob(sentry_base, &sentry_NULL, sentry_size);

 //Fix up the aux vectors which point to other data
 for (int i = auxv.size() - 1; i >= 0; i--) {
 if (auxv[i].type == M5_AT_PLATFORM) {
 auxv[i].val = platform_base;
-initVirtMem.writeString(platform_base, platform.c_str());
+initVirtMem->writeString(platform_base, platform.c_str());
 } else if (auxv[i].type == M5_AT_EXECFN) {
 auxv[i].val = aux_data_base;
-initVirtMem.writeString(aux_data_base, filename.c_str());
+initVirtMem->writeString(aux_data_base, filename.c_str());
 } else if (auxv[i].type == M5_AT_RANDOM) {
 auxv[i].val = aux_random_base;
 // Just leave the value 0, we don't want randomness
@@ -423,20 +423,20 @@
 //Copy the aux stuff
 Addr auxv_array_end = auxv_array_base;
 for (const auto &aux: auxv) {
-initVirtMem.write(auxv_array_end, aux, GuestByteOrder);
+initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
 auxv_array_end += sizeof(aux);
 }
 //Write out the terminating zeroed auxillary vector
 const AuxVector zero(0, 0);
-initVirtMem.write(auxv_array_end, zero);
+initVirtMem->write(auxv_array_end, zero);
 auxv_array_end += sizeof(zero);

 copyStringArray(envp, envp_array_base, env_data_base,
-LittleEndianByteOrder, initVirtMem);
+LittleEndianByteOrder, *initVirtMem);
 copyStringArray(argv, argv_array_base, arg_data_base,
-LittleEndianByteOrder, initVirtMem);
+LittleEndianByteOrder, *initVirtMem);

-initVirtMem.writeBlob(argc_base, &guestArgc, intSize);
+initVirtMem->writeBlob(argc_base, &guestArgc, intSize);

 ThreadContext *tc = system->getThreadContext(contextIds[0]);
 //Set the stack pointer register
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index afeef8b..c388087 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -159,24 +159,24 @@

 argc = htole((IntType)argc);

-initVirtMem.writeBlob(memState->getStackMin(), &argc, intSize);
+initVirtMem->writeBlob(memState->getStackMin(), &argc, intSize);

 copyStringArray(argv, argv_array_base, arg_data_base,
-LittleEndianByteOrder, initVirtMem);
+LittleEndianByteOrder, *initVirtMem);

 copyStringArray(envp, envp_array_base, env_data_base,
-LittleEndianByteOrder, initVirtMem);
+Littl

[gem5-dev] Change in gem5/gem5[develop]: arch, base, cpu, dev, kern, mem, sim: Drop FS from FSTranslatingPortProxy.

2020-03-19 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26551 )


Change subject: arch,base,cpu,dev,kern,mem,sim: Drop FS from  
FSTranslatingPortProxy.

..

arch,base,cpu,dev,kern,mem,sim: Drop FS from FSTranslatingPortProxy.

This translating proxy can be used in FS, or in SE with a failure
handing case in place.

Change-Id: I2e6421f52529fa833e42f8d3e64d4341c282634f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26551
Tested-by: kokoro 
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
---
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/freebsd/fs_workload.cc
M src/arch/arm/linux/fs_workload.cc
M src/arch/arm/stacktrace.cc
M src/arch/arm/system.cc
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/utility.cc
M src/arch/mips/stacktrace.cc
M src/arch/mips/utility.cc
M src/arch/sparc/utility.cc
M src/arch/x86/stacktrace.cc
M src/base/remote_gdb.cc
M src/cpu/simple_thread.cc
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
M src/dev/arm/gic_v3_redistributor.cc
M src/kern/linux/helpers.cc
M src/mem/SConscript
M src/mem/se_translating_port_proxy.cc
M src/mem/se_translating_port_proxy.hh
R src/mem/translating_port_proxy.cc
R src/mem/translating_port_proxy.hh
M src/sim/arguments.hh
M src/sim/vptr.hh
24 files changed, 32 insertions(+), 57 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc  
b/src/arch/arm/fastmodel/iris/thread_context.cc

index 516565e..9aed27b 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -32,8 +32,8 @@
 #include "arch/arm/utility.hh"
 #include "iris/detail/IrisCppAdapter.h"
 #include "iris/detail/IrisObjects.h"
-#include "mem/fs_translating_port_proxy.hh"
 #include "mem/se_translating_port_proxy.hh"
+#include "mem/translating_port_proxy.hh"

 namespace Iris
 {
@@ -407,7 +407,7 @@
 assert(!physProxy && !virtProxy);
 physProxy.reset(new PortProxy(_cpu->getSendFunctional(),
   _cpu->cacheLineSize()));
-virtProxy.reset(new FSTranslatingPortProxy(tc));
+virtProxy.reset(new TranslatingPortProxy(tc));
 } else {
 assert(!virtProxy);
 virtProxy.reset(new SETranslatingPortProxy(this,
diff --git a/src/arch/arm/freebsd/fs_workload.cc  
b/src/arch/arm/freebsd/fs_workload.cc

index 33e0126..dbadb4b 100644
--- a/src/arch/arm/freebsd/fs_workload.cc
+++ b/src/arch/arm/freebsd/fs_workload.cc
@@ -43,7 +43,6 @@
 #include "cpu/thread_context.hh"
 #include "debug/Loader.hh"
 #include "kern/freebsd/events.hh"
-#include "mem/fs_translating_port_proxy.hh"
 #include "mem/physical.hh"
 #include "sim/stat_control.hh"

diff --git a/src/arch/arm/linux/fs_workload.cc  
b/src/arch/arm/linux/fs_workload.cc

index 9390a46..c21ce09 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -55,7 +55,6 @@
 #include "kern/linux/events.hh"
 #include "kern/linux/helpers.hh"
 #include "kern/system_events.hh"
-#include "mem/fs_translating_port_proxy.hh"
 #include "mem/physical.hh"
 #include "sim/stat_control.hh"

diff --git a/src/arch/arm/stacktrace.cc b/src/arch/arm/stacktrace.cc
index 4604524..b5a9976 100644
--- a/src/arch/arm/stacktrace.cc
+++ b/src/arch/arm/stacktrace.cc
@@ -35,7 +35,7 @@
 #include "base/trace.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
+#include "mem/port_proxy.hh"
 #include "sim/system.hh"

 namespace ArmISA
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 9053a5c..97c3c5f 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -49,7 +49,6 @@
 #include "cpu/thread_context.hh"
 #include "dev/arm/fvp_base_pwr_ctrl.hh"
 #include "dev/arm/gic_v2.hh"
-#include "mem/fs_translating_port_proxy.hh"
 #include "mem/physical.hh"

 using namespace std;
diff --git a/src/arch/arm/tracers/tarmac_parser.cc  
b/src/arch/arm/tracers/tarmac_parser.cc

index a5fc32d..96678b0 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -48,8 +48,8 @@
 #include "config/the_isa.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
 #include "mem/packet.hh"
+#include "mem/port_proxy.hh"
 #include "sim/core.hh"
 #include "sim/faults.hh"
 #include "sim/sim_exit.hh"
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 393f141..7c70def 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -46,7 +46,7 @@
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
+#include "mem/port_proxy.hh"
 #include "sim/full_system.hh"

 namespace ArmISA
diff --git a/src/arch/mips/sta

[gem5-dev] Change in gem5/gem5[develop]: mem: Add a Request::Flags parameter to the translating port proxies.

2020-03-19 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26623 )


Change subject: mem: Add a Request::Flags parameter to the translating port  
proxies.

..

mem: Add a Request::Flags parameter to the translating port proxies.

These flags will be given to the Request object which is used to do the
translation.

Change-Id: I21755f5f9369311e2f2d5be73ebd4f5865f73265
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26623
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
---
M src/mem/se_translating_port_proxy.cc
M src/mem/se_translating_port_proxy.hh
M src/mem/translating_port_proxy.cc
M src/mem/translating_port_proxy.hh
4 files changed, 14 insertions(+), 9 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/se_translating_port_proxy.cc  
b/src/mem/se_translating_port_proxy.cc

index 458b2fa..8af628f 100644
--- a/src/mem/se_translating_port_proxy.cc
+++ b/src/mem/se_translating_port_proxy.cc
@@ -44,8 +44,8 @@
 #include "sim/system.hh"

 SETranslatingPortProxy::SETranslatingPortProxy(
-ThreadContext *tc, AllocType alloc) :
-TranslatingPortProxy(tc), allocating(alloc)
+ThreadContext *tc, AllocType alloc, Request::Flags _flags) :
+TranslatingPortProxy(tc, _flags), allocating(alloc)
 {}

 bool
diff --git a/src/mem/se_translating_port_proxy.hh  
b/src/mem/se_translating_port_proxy.hh

index 1b6be8a..0fe3212 100644
--- a/src/mem/se_translating_port_proxy.hh
+++ b/src/mem/se_translating_port_proxy.hh
@@ -60,7 +60,8 @@
 bool fixupAddr(Addr addr, BaseTLB::Mode mode) const override;

   public:
-SETranslatingPortProxy(ThreadContext *tc, AllocType alloc);
+SETranslatingPortProxy(ThreadContext *tc, AllocType alloc,
+   Request::Flags _flags=0);
 };

 #endif // __MEM_SE_TRANSLATING_PORT_PROXY_HH__
diff --git a/src/mem/translating_port_proxy.cc  
b/src/mem/translating_port_proxy.cc

index c44ff5f..8bb93cc 100644
--- a/src/mem/translating_port_proxy.cc
+++ b/src/mem/translating_port_proxy.cc
@@ -50,10 +50,12 @@
 #include "cpu/thread_context.hh"
 #include "sim/system.hh"

-TranslatingPortProxy::TranslatingPortProxy(ThreadContext *tc) :
+TranslatingPortProxy::TranslatingPortProxy(
+ThreadContext *tc, Request::Flags _flags) :
 PortProxy(tc->getCpuPtr()->getSendFunctional(),
   tc->getSystemPtr()->cacheLineSize()), _tc(tc),
-  pageBytes(tc->getSystemPtr()->getPageBytes())
+  pageBytes(tc->getSystemPtr()->getPageBytes()),
+  flags(_flags)
 {}

 bool
@@ -81,7 +83,7 @@
  gen.next())
 {
 auto req = std::make_shared(
-gen.addr(), gen.size(), 0, Request::funcMasterId, 0,
+gen.addr(), gen.size(), flags, Request::funcMasterId, 0,
 _tc->contextId());

 if (!tryTLBs(req, BaseTLB::Read))
@@ -103,7 +105,7 @@
  gen.next())
 {
 auto req = std::make_shared(
-gen.addr(), gen.size(), 0, Request::funcMasterId, 0,
+gen.addr(), gen.size(), flags, Request::funcMasterId, 0,
 _tc->contextId());

 if (!tryTLBs(req, BaseTLB::Write))
@@ -123,7 +125,7 @@
  gen.next())
 {
 auto req = std::make_shared(
-gen.addr(), gen.size(), 0, Request::funcMasterId, 0,
+gen.addr(), gen.size(), flags, Request::funcMasterId, 0,
 _tc->contextId());

 if (!tryTLBs(req, BaseTLB::Write))
diff --git a/src/mem/translating_port_proxy.hh  
b/src/mem/translating_port_proxy.hh

index 1e17c64..a5dfe7f 100644
--- a/src/mem/translating_port_proxy.hh
+++ b/src/mem/translating_port_proxy.hh
@@ -62,6 +62,8 @@
 ThreadContext* _tc;
 const Addr pageBytes;

+Request::Flags flags;
+
 virtual bool
 fixupAddr(Addr addr, BaseTLB::Mode mode) const
 {
@@ -70,7 +72,7 @@

   public:

-TranslatingPortProxy(ThreadContext* tc);
+TranslatingPortProxy(ThreadContext *tc, Request::Flags _flags=0);

 /** Version of tryReadblob that translates virt->phys and deals
   * with page boundries. */

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I21755f5f9369311e2f2d5be73ebd4f5865f73265
Gerrit-Change-Number: 26623
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged