[gem5-dev] Re: [gem5-users] Garnet Network Interface connection to Protocol Controllers

2020-04-23 Thread Arun Mishra via gem5-dev 
The topology file route seems easy.

Thanks a lot for your help.
Arun Mishra

On Thu, Apr 23, 2020 at 11:38 PM Krishna, Tushar 
wrote:

> Hmm this info might be available when you see the config file - am not
> entirely sure. Alternately, there should be a way to snoop the Msg going
> out of / in to the NIC and display the name of the controller.
> Note that the order in which you connect the controllers in the topology
> file is the order in which the NI IDs get created.
> For eg., if you were to use MOESI_hammer protocol with
> MeshDirCorners_XY.py for say a 8x8 mesh, NIs 0 to 63 correspond to cache
> controllers and NIs 64 to 67 correspond to directory controllers.
>
> Tushar
> On Apr 23, 2020, 11:32 PM -0400, Arun Mishra ,
> wrote:
>
> That makes things a lot easier. Thank you.
>
> A follow up question :
> Where should I look if I want to identify the specific Controller connected
> to a NI. I would like to identify a NI's corresponding controller by a name
> and a number, e.g. CPCntrl0, L3Cntrl1 etc.
>
> Regards,
> Arun Mishra
>
>
> 
>  Virus-free.
> www.avg.com
> 
> <#m_7959105470972059657_DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2>
>
> On Thu, Apr 23, 2020 at 11:12 PM Krishna, Tushar 
> wrote:
>
>> Each controller creates one NI. Multiple NIs connect to the same router
>> within the NoC.
>> So you can collect controller specific network stats from the NI it is
>> connected to.
>>
>> Best,
>> Tushar
>>
>> On Apr 23, 2020, 11:09 PM -0400, Arun Mishra via gem5-users <
>> gem5-us...@gem5.org>, wrote:
>>
>> Hi All,
>>
>> In Garnet, is a single Network Interface object (NI) connected to a
>> single Protocol Controller (e.g. Directory Controller, Cache Ctrl, Core
>> pair Ctrl) or is connection to multiple controllers possible ?
>>
>> I am asking this because I need to collect some controller specific
>> network stats and I want to know if there is a way to separate out the
>> stats based on the NI it is connected with. Otherwise, is there a better
>> way of collecting per controller network stats ?
>>
>> Thank You,
>> Arun Mishra
>>
>>
>> 
>>  Virus-free.
>> www.avg.com
>> 
>> <#m_7959105470972059657_m_834811408002905730_DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2>
>>
>>
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[gem5-dev] Re: [gem5-users] Garnet Network Interface connection to Protocol Controllers

2020-04-23 Thread Krishna, Tushar via gem5-dev 
Hmm this info might be available when you see the config file - am not entirely 
sure. Alternately, there should be a way to snoop the Msg going out of / in to 
the NIC and display the name of the controller.
Note that the order in which you connect the controllers in the topology file 
is the order in which the NI IDs get created.
For eg., if you were to use MOESI_hammer protocol with MeshDirCorners_XY.py for 
say a 8x8 mesh, NIs 0 to 63 correspond to cache controllers and NIs 64 to 67 
correspond to directory controllers.

Tushar
On Apr 23, 2020, 11:32 PM -0400, Arun Mishra , 
wrote:
That makes things a lot easier. Thank you.

A follow up question :
Where should I look if I want to identify the specific Controller connected
to a NI. I would like to identify a NI's corresponding controller by a name
and a number, e.g. CPCntrl0, L3Cntrl1 etc.

Regards,
Arun Mishra

[https://ipmcdn.avast.com/images/icons/icon-envelope-tick-green-avg-v1.png]
 Virus-free. 
www.avg.com

On Thu, Apr 23, 2020 at 11:12 PM Krishna, Tushar 
mailto:tus...@ece.gatech.edu>> wrote:
Each controller creates one NI. Multiple NIs connect to the same router within 
the NoC.
So you can collect controller specific network stats from the NI it is 
connected to.

Best,
Tushar

On Apr 23, 2020, 11:09 PM -0400, Arun Mishra via gem5-users 
mailto:gem5-us...@gem5.org>>, wrote:
Hi All,

In Garnet, is a single Network Interface object (NI) connected to a single 
Protocol Controller (e.g. Directory Controller, Cache Ctrl, Core pair Ctrl) or 
is connection to multiple controllers possible ?

I am asking this because I need to collect some controller specific network 
stats and I want to know if there is a way to separate out the stats based on 
the NI it is connected with. Otherwise, is there a better way of collecting per 
controller network stats ?

Thank You,
Arun Mishra

[https://ipmcdn.avast.com/images/icons/icon-envelope-tick-green-avg-v1.png]
 Virus-free. 
www.avg.com
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[gem5-dev] Re: [gem5-users] Garnet Network Interface connection to Protocol Controllers

2020-04-23 Thread Arun Mishra via gem5-dev 
 That makes things a lot easier. Thank you.

A follow up question :
Where should I look if I want to identify the specific Controller connected
to a NI. I would like to identify a NI's corresponding controller by a name
and a number, e.g. CPCntrl0, L3Cntrl1 etc.

Regards,
Arun Mishra


Virus-free.
www.avg.com

<#DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2>

On Thu, Apr 23, 2020 at 11:12 PM Krishna, Tushar 
wrote:

> Each controller creates one NI. Multiple NIs connect to the same router
> within the NoC.
> So you can collect controller specific network stats from the NI it is
> connected to.
>
> Best,
> Tushar
>
> On Apr 23, 2020, 11:09 PM -0400, Arun Mishra via gem5-users <
> gem5-us...@gem5.org>, wrote:
>
> Hi All,
>
> In Garnet, is a single Network Interface object (NI) connected to a single
> Protocol Controller (e.g. Directory Controller, Cache Ctrl, Core pair Ctrl)
> or is connection to multiple controllers possible ?
>
> I am asking this because I need to collect some controller specific
> network stats and I want to know if there is a way to separate out the
> stats based on the NI it is connected with. Otherwise, is there a better
> way of collecting per controller network stats ?
>
> Thank You,
> Arun Mishra
>
>
> 
>  Virus-free.
> www.avg.com
> 
> <#m_834811408002905730_DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2>
>
>
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[gem5-dev] Re: [gem5-users] Garnet Network Interface connection to Protocol Controllers

2020-04-23 Thread Krishna, Tushar via gem5-dev 
Each controller creates one NI. Multiple NIs connect to the same router within 
the NoC.
So you can collect controller specific network stats from the NI it is 
connected to.

Best,
Tushar

On Apr 23, 2020, 11:09 PM -0400, Arun Mishra via gem5-users 
, wrote:
Hi All,

In Garnet, is a single Network Interface object (NI) connected to a single 
Protocol Controller (e.g. Directory Controller, Cache Ctrl, Core pair Ctrl) or 
is connection to multiple controllers possible ?

I am asking this because I need to collect some controller specific network 
stats and I want to know if there is a way to separate out the stats based on 
the NI it is connected with. Otherwise, is there a better way of collecting per 
controller network stats ?

Thank You,
Arun Mishra

[https://ipmcdn.avast.com/images/icons/icon-envelope-tick-green-avg-v1.png]
 Virus-free. 
www.avg.com
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[gem5-dev] Garnet Network Interface connection to Protocol Controllers

2020-04-23 Thread Arun Mishra via gem5-dev 
Hi All,

In Garnet, is a single Network Interface object (NI) connected to a single
Protocol Controller (e.g. Directory Controller, Cache Ctrl, Core pair Ctrl)
or is connection to multiple controllers possible ?

I am asking this because I need to collect some controller specific network
stats and I want to know if there is a way to separate out the stats based
on the NI it is connected with. Otherwise, is there a better way of
collecting per controller network stats ?

Thank You,
Arun Mishra


Virus-free.
www.avg.com

<#DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2>
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[gem5-dev] Mailing List problems experienced this afternoon. Now resolved

2020-04-23 Thread Bobby Bruce via gem5-dev 
Dear all,

This afternoon we found out our mailing list was not sending emails to
everyone who had subscribed to them. It seems this primarily affected those
with Microsoft-based email addresses (outlook et al.). I've been told some
filters were activated due to the high volume of email from our lists.
After some back and forth with our new provider, I have been told this
issue is now resolved. If you've asked a question on gem5-users/gem5-dev
and have yet to hear a response, I'd advise waiting a little bit (say,
until tomorrow) and perhaps asking again. I am unsure if the backlog of
mail sent out during this time will eventually be delivered, so I'd say
it's best to wait and see. I'd also advise list members to check their Spam
folder for any mail that may have been misclassified during this time.

We've also had reports of real spam being sent to the lists. I apologize
for this, I believe this was due to a misconfiguration on our mailman
server which has since been fixed. If anyone notices any additional spam
emails from now on, please email me and I'll tighten up the rules on the
mailing list to prevent them.

I apologize to everyone for this. It really shouldn't have happened and
caught us a bit off guard. I hope the mailing list services are back to a
usable state. Please let me know directly about any additional problems,
big or small, you encounter when using these lists.

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net
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[gem5-dev] Test

2020-04-23 Thread Bobby Bruce via gem5-dev 
This is a test for the mailing lists.
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net
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[gem5-dev] Call for help: gem5-20 release

2020-04-23 Thread Jason Lowe-Power via gem5-dev 
Hi everyone!

I'm super excited to say that we're getting close to our first new release:
gem5-20! However, there's a ton of work left for us to have a successful
release. Anything you (anyone and everyone!) can do to help would be
greatly appreciated!

As some of you may have noticed, our Gerrit review system has a large
volume of outstanding reviews (
https://gem5-review.googlesource.com/q/status:open). At the time of writing
we have around 200 changesets that have been updated since our gem5 19
release but have yet to be incorporated into the code base. Reviewing
patches in a timely manner has always been a problem for us, but this
problem has become more pressing due to our upcoming gem5 20 staging branch
release (next Friday, May 1st). Any changes not fully incorporated to the
develop branch by then will not be included in gem5 20. It'd be unfortunate
for members of our community, who've dedicated significant time to
improving gem5, to not see their contributions included in the upcoming
release due to our reviewing bottleneck.

I'm therefore writing to politely ask those of you with any spare time over
the next week to lend a hand in helping us to review these outstanding
changes. At this stage, help with reviewing is the most good a gem5
community member can do. We suspect the number of changesets pushed to
Gerrit will spike over the coming week due to the encroaching Friday
cut-off, so additional help is needed more than ever.

Additionally there are still many open issues (75 as of today) tagged for
gem5-20 release on Jira (
https://gem5.atlassian.net/issues/?jql=fixVersion%20%3D%20%22gem5%2020.0%22).
Most of these are small (e.g., fix a failing test). If you see anything
there you can help out with, please feel free to assign yourself or make a
comment tagging Bobby to see if help is needed.

As always, thank you all for the contributions you've made, and continue to
make, to the gem5 project. gem5 20 would simply not be possible without
your support.

Cheers,
Jason & Bobby
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[gem5-dev] Pseudo instruction based gem5 ops on ARM

2020-04-23 Thread Gabe Black via gem5-dev 
Hi ARM gem5 folks. I've been trying to develop some tests for the various
forms of calling gem5 ops, and am trying to run them on QEMU as an easy way
to (approximately) run them on other architectures. I've run into a few
problems which I've been discussing with the QEMU folks, and outside of a
few small shortcomings of QEMU, one problem that they pointed out that our
implementation has is that form 32 bit ARM we're using accesses to a
coprocessor which isn't supposed to exist as our pseudo instructions.

That kind of works, except that that coprocessor may actually exist, and it
does exist in the QEMU implementation to support very old ARM binaries.
Changing to some other instructions at this point would be very difficult,
but I'm slightly concerned that the instructions we picked aren't
necessarily actually unused, outside of the difficulty that causes with
QEMU.

Do any ARM folks have an opinion on what we should do here? Is 32 bit ARM
out of the mainstream enough where we could change it and not cause
everyone huge headaches? I think we can keep the hooks for it in its
current location but move the official instructions somewhere new, if we
wanted.

Gabe
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[gem5-dev] Change in gem5/gem5[develop]: configs: Specify cache, dir, and mem cntrl interleaving

2020-04-23 Thread Anthony Gutierrez (Gerrit) via gem5-dev 

Hello Tony Gutierrez, Onur Kayıran,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28134

to review the following change.


Change subject: configs: Specify cache, dir, and mem cntrl interleaving
..

configs: Specify cache, dir, and mem cntrl interleaving

This changeset allows setting a variable for interleaving.
That value is used together with the number of directories to
calculate numa_high_bit, which is in turn used to set up
cache, directory, and memory controller interleaving.
A similar approach is used to set xor_low_bit, and calculate
xor_high_bit for address hashing.

Change-Id: Ia342c77c59ca2e3438db218b5c399c3373618320
---
M configs/common/MemConfig.py
M configs/ruby/Ruby.py
2 files changed, 24 insertions(+), 6 deletions(-)



diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 9443520..3461a9e 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -40,7 +40,8 @@
 from common import ObjectList
 from common import HMC

-def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
+def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size,\
+xor_low_bit):
 """
 Helper function for creating a single memoy controller from the given
 options.  This function is invoked multiple times in config_mem  
function

@@ -55,7 +56,10 @@
 # the details of the caches here, make an educated guess. 4 MByte
 # 4-way associative with 64 byte cache lines is 6 offset bits and
 # 14 index bits.
-xor_low_bit = 20
+if (xor_low_bit):
+xor_high_bit = xor_low_bit + intlv_bits - 1
+else:
+xor_high_bit = 0

 # Create an instance so we can figure out the address
 # mapping and row-buffer size
@@ -81,8 +85,7 @@
 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
   intlvHighBit = \
   intlv_low_bit + intlv_bits - 1,
-  xorHighBit = \
-  xor_low_bit + intlv_bits - 1,
+  xorHighBit = xor_high_bit,
   intlvBits = intlv_bits,
   intlvMatch = i)
 return ctrl
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index e69784f..9bceaa3 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -76,6 +76,15 @@
 parser.add_option("--numa-high-bit", type="int", default=0,
   help="high order address bit to use for numa  
mapping. " \

"0 = highest bit, not specified = lowest bit")
+parser.add_option("--interleaving-bits", type="int", default=0,
+  help="number of bits to specify interleaving " \
+   "in directory, memory controllers and caches. "
+   "0 = not specified")
+parser.add_option("--xor-low-bit", type="int", default=20,
+  help="hashing bit for channel selection" \
+   "see MemConfig for explanation of the default"\
+   "parameter. If set to 0, xor_high_bit is also"\
+   "set to 0.")

 parser.add_option("--recycle-latency", type="int", default=10,
   help="Recycle latency for ruby controller input  
buffers")

@@ -86,7 +95,13 @@
 Network.define_options(parser)

 def setup_memory_controllers(system, ruby, dir_cntrls, options):
-ruby.block_size_bytes = options.cacheline_size
+if (options.numa_high_bit):
+block_size_bits = options.numa_high_bit + 1 - \
+  int(math.log(options.num_dirs, 2))
+ruby.block_size_bytes = 2 ** (block_size_bits)
+else:
+ruby.block_size_bytes = options.cacheline_size
+
 ruby.memory_size_bits = 48

 index = 0
@@ -117,7 +132,7 @@
 mem_type = ObjectList.mem_list.get(options.mem_type)
 mem_ctrl = MemConfig.create_mem_ctrl(mem_type, r, index,
 options.num_dirs, int(math.log(options.num_dirs, 2)),
-intlv_size)
+intlv_size, options.xor_low_bit)

 if options.access_backing_store:
 mem_ctrl.kvm_map=False

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28134
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia342c77c59ca2e3438db218b5c399c3373618320
Gerrit-Change-Number: 28134
Gerrit-PatchSet: 1
Gerrit-Owner: Anthony Gutierrez 
Gerrit-Reviewer: Onur Kayıran 
Gerrit-Reviewer: Tony Gutierrez 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs: add option to set the timeouts for the TCPs and SQCs

2020-04-23 Thread Anthony Gutierrez (Gerrit) via gem5-dev 

Hello Tony Gutierrez,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28129

to review the following change.


Change subject: configs: add option to set the timeouts for the TCPs and  
SQCs

..

configs: add option to set the timeouts for the TCPs and SQCs

Change-Id: Icff2bd0237ddcc0d21db17208df8e53ff6f43e86
---
M configs/ruby/GPU_RfO.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/GPU_VIPER_Baseline.py
M configs/ruby/GPU_VIPER_Region.py
4 files changed, 63 insertions(+), 0 deletions(-)



diff --git a/configs/ruby/GPU_RfO.py b/configs/ruby/GPU_RfO.py
index cf2fdbd..26bea0c 100644
--- a/configs/ruby/GPU_RfO.py
+++ b/configs/ruby/GPU_RfO.py
@@ -168,6 +168,11 @@
 self.coalescer.max_outstanding_requests = options.simds_per_cu * \
   options.wfs_per_simd * \
   options.wf_size
+if options.tcp_deadlock_threshold:
+  self.coalescer.deadlock_threshold = \
+options.tcp_deadlock_threshold
+self.coalescer.max_coalesces_per_cycle = \
+options.max_coalesces_per_cycle

 self.sequencer = RubySequencer()
 self.sequencer.version = self.seqCount()
@@ -240,6 +245,10 @@
 self.sequencer.support_data_reqs = False
 self.sequencer.is_cpu_sequencer = False

+if options.sqc_deadlock_threshold:
+  self.sequencer.deadlock_threshold = \
+options.sqc_deadlock_threshold
+
 self.ruby_system = ruby_system

 if options.recycle_latency:
@@ -416,6 +425,8 @@
   help="number of TCC directories and banks in the  
GPU")

 parser.add_option("--TCP_latency", type="int", default=4,
   help="TCP latency")
+parser.add_option("--tcp-deadlock-threshold", type='int',
+  help="Set the TCP deadlock threshold to some value")
 parser.add_option("--TCC_latency", type="int", default=16,
   help="TCC latency")
 parser.add_option("--tcc-size", type='string', default='256kB',
@@ -424,6 +435,10 @@
   help="tcp size")
 parser.add_option("--tcc-dir-factor", type='int', default=4,
   help="TCCdir size = factor *(TCPs + TCC)")
+parser.add_option("--sqc-deadlock-threshold", type='int',
+  help="Set the SQC deadlock threshold to some value")
+parser.add_option("--max-coalesces-per-cycle", type="int", default=1,
+  help="Maximum insts that may coalesce in a cycle");

 def create_system(options, full_system, system, dma_devices, bootmem,
   ruby_system):
diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index 71238ae..f4ecc41 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -153,6 +153,11 @@
 self.coalescer.ruby_system = ruby_system
 self.coalescer.support_inst_reqs = False
 self.coalescer.is_cpu_sequencer = False
+if options.tcp_deadlock_threshold:
+  self.coalescer.deadlock_threshold = \
+  options.tcp_deadlock_threshold
+self.coalescer.max_coalesces_per_cycle = \
+options.max_coalesces_per_cycle

 self.sequencer = RubySequencer()
 self.sequencer.version = self.seqCount()
@@ -227,6 +232,9 @@
 self.sequencer.ruby_system = ruby_system
 self.sequencer.support_data_reqs = False
 self.sequencer.is_cpu_sequencer = False
+if options.sqc_deadlock_threshold:
+  self.sequencer.deadlock_threshold = \
+options.sqc_deadlock_threshold

 self.ruby_system = ruby_system

@@ -370,6 +378,9 @@
   help = "SQC cache size")
 parser.add_option("--sqc-assoc", type = 'int', default = 8,
   help = "SQC cache assoc")
+parser.add_option("--sqc-deadlock-threshold", type='int',
+  help="Set the SQC deadlock threshold to some value")
+
 parser.add_option("--WB_L1", action = "store_true", default = False,
   help = "writeback L1")
 parser.add_option("--WB_L2", action = "store_true", default = False,
@@ -386,6 +397,11 @@
   help = "tcp size")
 parser.add_option("--tcp-assoc", type = 'int', default = 16,
   help = "tcp assoc")
+parser.add_option("--tcp-deadlock-threshold", type='int',
+  help="Set the TCP deadlock threshold to some value")
+parser.add_option("--max-coalesces-per-cycle", type="int", default=1,
+  help="Maximum insts that may coalesce in a cycle");
+
 parser.add_option("--noL1", action = "store_true", default = False,
   help = "bypassL1")

diff --git a/configs/ruby/GPU_VIPER_Baseline.py  
b/configs/ruby/GPU_VIPER_Baseline.py

index

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: ignore cache config desc cpu id func

2020-04-23 Thread Anthony Gutierrez (Gerrit) via gem5-dev 

Hello Tony Gutierrez,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28131

to review the following change.


Change subject: arch-x86: ignore cache config desc cpu id func
..

arch-x86: ignore cache config desc cpu id func

Change-Id: If07ae8f48e31dd5bdf21dd1e7385e389e01ca5cd
---
M src/arch/x86/cpuid.cc
1 file changed, 8 insertions(+), 0 deletions(-)



diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index 64d4544..0efd83b 100644
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -35,6 +35,9 @@
 enum StandardCpuidFunction {
 VendorAndLargestStdFunc,
 FamilyModelStepping,
+ProcessorConfigDescriptors,
+ProcessorSerialNums,
+CacheConfigDescriptors,
 CacheAndTLB,
 SerialNumber,
 CacheParams,
@@ -162,6 +165,11 @@
 result = CpuidResult(0x00020f51, 0x0805,
  0xe7dbfbff, 0x0209);
 break;
+  case CacheConfigDescriptors:
+warn("x86 cpuid family 0x: unimplemented function %u "
+"returning 0x0, 0x0, 0x0, 0x0.", funcNum);
+result = CpuidResult(0x0, 0x0, 0x0, 0x0);
+break;
   case ExtendedFeatures:
 result = CpuidResult(0x, 0x0180,
  0x, 0x);

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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add slicc stm to defer enqueueing a message

2020-04-23 Thread Anthony Gutierrez (Gerrit) via gem5-dev 

Hello Tony Gutierrez, Tuan Ta,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28132

to review the following change.


Change subject: mem-ruby: add slicc stm to defer enqueueing a message
..

mem-ruby: add slicc stm to defer enqueueing a message

This patch enables cache controllers to make response
messages in advance, store them in a per-address saved
map in an output message buffer and enqueue them altogether
in the future. This patch introduces new slicc statement
called defer_enqueueing. This patch would help simplify
the logic of state machines that deal with coalesing
multiple requests from different requestors.

Change-Id: I566d4004498b367764238bb251260483c5a1a5e5
---
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/MessageBuffer.hh
M src/mem/ruby/protocol/RubySlicc_Types.sm
A src/mem/slicc/ast/DeferEnqueueingStatementAST.py
M src/mem/slicc/ast/__init__.py
M src/mem/slicc/parser.py
6 files changed, 145 insertions(+), 1 deletion(-)



diff --git a/src/mem/ruby/network/MessageBuffer.cc  
b/src/mem/ruby/network/MessageBuffer.cc

index f5562dc..6e14de1 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -395,6 +395,36 @@
 }

 void
+MessageBuffer::deferEnqueueingMessage(Addr addr, MsgPtr message)
+{
+DPRINTF(RubyQueue, "Deferring enqueueing message: %s, Address %#x\n",
+*(message.get()), addr);
+(m_deferred_msg_map[addr]).push_back(message);
+}
+
+void
+MessageBuffer::enqueueDeferredMessages(Addr addr, Tick curTime, Tick delay)
+{
+assert(!isDeferredMsgMapEmpty(addr));
+std::vector& msg_vec = m_deferred_msg_map[addr];
+assert(msg_vec.size() > 0);
+
+// enqueue all deferred messages associated with this address
+for (MsgPtr m : msg_vec) {
+enqueue(m, curTime, delay);
+}
+
+msg_vec.clear();
+m_deferred_msg_map.erase(addr);
+}
+
+bool
+MessageBuffer::isDeferredMsgMapEmpty(Addr addr) const
+{
+return m_deferred_msg_map.count(addr) == 0;
+}
+
+void
 MessageBuffer::print(ostream& out) const
 {
 ccprintf(out, "[MessageBuffer: ");
diff --git a/src/mem/ruby/network/MessageBuffer.hh  
b/src/mem/ruby/network/MessageBuffer.hh

index 0e11529..01c0767 100644
--- a/src/mem/ruby/network/MessageBuffer.hh
+++ b/src/mem/ruby/network/MessageBuffer.hh
@@ -51,6 +51,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 

 #include "base/trace.hh"
@@ -113,6 +114,19 @@

 void enqueue(MsgPtr message, Tick curTime, Tick delta);

+// Defer enqueueing a message to a later cycle by putting it aside and  
not

+// enqueueing it in this cycle
+// The corresponding controller will need to explicitly enqueue the
+// deferred message into the message buffer. Otherwise, the message  
will

+// be lost.
+void deferEnqueueingMessage(Addr addr, MsgPtr message);
+
+// enqueue all previously deferred messages that are associated with  
the

+// input address
+void enqueueDeferredMessages(Addr addr, Tick curTime, Tick delay);
+
+bool isDeferredMsgMapEmpty(Addr addr) const;
+
 //! Updates the delay cycles of the message at the head of the queue,
 //! removes it from the queue and returns its total delay.
 Tick dequeue(Tick current_time, bool decrement_messages = true);
@@ -192,6 +206,14 @@
 StallMsgMapType m_stall_msg_map;

 /**
+ * A map from line addresses to corresponding vectors of messages that
+ * are deferred for enqueueing. Messages in this map are waiting to be
+ * enqueued into the message buffer.
+ */
+typedef std::unordered_map>  
DeferredMsgMapType;

+DeferredMsgMapType m_deferred_msg_map;
+
+/**
  * Current size of the stall map.
  * Track the number of messages held in stall map lists. This is used  
to
  * ensure that if the buffer is finite-sized, it blocks further  
requests
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm  
b/src/mem/ruby/protocol/RubySlicc_Types.sm

index fd76289..ccf881c 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -37,9 +37,13 @@
 //

 external_type(MessageBuffer, buffer="yes", inport="yes", outport="yes");
-external_type(OutPort, primitive="yes");
 external_type(Scalar, primitive="yes");

+structure(OutPort, external = "yes", primitive="yes") {
+void enqueueDeferredMessages(Addr addr, Tick curTime, Tick delay);
+bool isDeferredMsgMapEmpty(Addr addr);
+}
+
 structure(InPort, external = "yes", primitive="yes") {
   bool isReady(Tick current_time);
   Tick dequeue(Tick current_time);
diff --git a/src/mem/slicc/ast/DeferEnqueueingStatementAST.py  
b/src/mem/slicc/ast/DeferEnqueueingStatementAST.py

new file mode 100644
index 000..40b9a4c
--- /dev/null
+++ b/src/mem/slicc/ast/DeferEnqueueingStatementAST.py
@@ -0,0 +1,82 @@
+#
+# Copyright (c) 2017 Advanced Micro Devices, Inc.

[gem5-dev] Change in gem5/gem5[develop]: dev-hsa: Add HSA device and HSA packet processor

2020-04-23 Thread Anthony Gutierrez (Gerrit) via gem5-dev 

Hello Tony Gutierrez,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28128

to review the following change.


Change subject: dev-hsa: Add HSA device and HSA packet processor
..

dev-hsa: Add HSA device and HSA packet processor

This change adds support for HSA devices, which are
DMA devices that have an HSA packet processor (HSAPP).

An HSA packet processor model is also included. The
HSAPP is a DMA device that matains AQL packet queues
and handles extraction of AQL packets, scheduling
of AQL queues, and initiates kernel launch for HSA
devices.

Because these devices directly interact with low-level
software and aid in the implementation of the HSA ABI
we also include some headers from the ROCm runtime:
the hsa.h and kfd_ioctl.h headers. These aid with
support ROCm for the HSA devices and drivers.

Change-Id: I24305e0337edc6fa555d436697b4e607a1e097d5
---
M MAINTAINERS
A src/dev/hsa/HSADevice.py
A src/dev/hsa/HSADriver.py
A src/dev/hsa/SConscript
A src/dev/hsa/hsa.h
A src/dev/hsa/hsa_device.cc
A src/dev/hsa/hsa_device.hh
A src/dev/hsa/hsa_driver.cc
A src/dev/hsa/hsa_driver.hh
A src/dev/hsa/hsa_packet.hh
A src/dev/hsa/hsa_packet_processor.cc
A src/dev/hsa/hsa_packet_processor.hh
A src/dev/hsa/hsa_queue.hh
A src/dev/hsa/hw_scheduler.cc
A src/dev/hsa/hw_scheduler.hh
A src/dev/hsa/kfd_ioctl.h
16 files changed, 8,419 insertions(+), 0 deletions(-)




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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Generate address with masking cacheline bits

2020-04-23 Thread Anthony Gutierrez (Gerrit) via gem5-dev 

Hello Tony Gutierrez, Onur Kayıran,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28135

to review the following change.


Change subject: mem-ruby: Generate address with masking cacheline bits
..

mem-ruby: Generate address with masking cacheline bits

makeLineAddress function uses m_block_size_bits to create
masked addresses. m_block_size_bits is used to specify
cache, directory, and memory controller interleaving,
and it can be larger than the cache line size.
To generate addresses that can align with the cache line
rather than the interleaving granularity, a version of
makeLineAddress is created to specify bits that need to
be masked.

Change-Id: I06deec4949da7fa46f1d6f7575334f18ee61c786
---
M src/mem/ruby/common/Address.cc
M src/mem/ruby/common/Address.hh
2 files changed, 7 insertions(+), 0 deletions(-)



diff --git a/src/mem/ruby/common/Address.cc b/src/mem/ruby/common/Address.cc
index 40ce0fe..39de974 100644
--- a/src/mem/ruby/common/Address.cc
+++ b/src/mem/ruby/common/Address.cc
@@ -56,6 +56,12 @@
 return mbits(addr, 63, RubySystem::getBlockSizeBits());
 }

+Addr
+makeLineAddress(Addr addr, int cacheLineBits)
+{
+return maskLowOrderBits(addr, cacheLineBits);
+}
+
 // returns the next stride address based on line address
 Addr
 makeNextStrideAddress(Addr addr, int stride)
diff --git a/src/mem/ruby/common/Address.hh b/src/mem/ruby/common/Address.hh
index 30682fa..e5e320f 100644
--- a/src/mem/ruby/common/Address.hh
+++ b/src/mem/ruby/common/Address.hh
@@ -40,6 +40,7 @@
 Addr maskLowOrderBits(Addr addr, unsigned int number);
 Addr getOffset(Addr addr);
 Addr makeLineAddress(Addr addr);
+Addr makeLineAddress(Addr addr, int cacheLineBits);
 Addr makeNextStrideAddress(Addr addr, int stride);
 std::string printAddress(Addr addr);


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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Add files for arch gcn3 (GPU machine ISA)

2020-04-23 Thread Anthony Gutierrez (Gerrit) via gem5-dev 

Hello Tony Gutierrez,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28127

to review the following change.


Change subject: arch-gcn3: Add files for arch gcn3 (GPU machine ISA)
..

arch-gcn3: Add files for arch gcn3 (GPU machine ISA)

Decoder: gpu_decoder.hh and decoder.cc:
The decoder is defined in these files. The decoder
is implemented as a lookup table of function pointers
where each decode function will decode to a unique
ISA instruction, or do some sub-decoding to infer
the next decode function to call.

The format for each OP encoding is defined in the
header file.

Registers:
registers.[hh|cc] define the special registers and
operand selector values, which are used to map
operands to registers/special values. many
convenience functions are also provides to determine
the source/type of an operand, for example vector
vs. scalar, register operand vs. constant, etc.

GPU ISA:
Some special GPU ISA state is maintained in gpu_isa.hh
and isa.cc. This class is used to hold some special
registers and values that can be used as operands
by ISA instructions. Eventually more ISA-specific
state should be moved here, and out of the WF class.

Vector Operands:
The operands for GCN3 instructions are defined in
operand.hh. This file defines both scalar and
vector operands wth GCN3 specific semantics. The
vector operand class is desgned around the generic
vec_reg.hh that is already present in gem5.

Instructions:
The GCN3 instructions are defined and implemented
throughout gpu_static_inst.[hh|cc], instructions.[hh|cc],
op_encodings.[hh|cc], and inst_util.hh. GCN3 instructions
all fall under one of the OP encoding types; for example
scalar memory operands are of the type SMEM, vector
ALU instructions can be VOP3, VOP2, etc. The base code
common to all instructions of a certain OP encoding type
is implemented in the OP encodings files, which includes
operand information, disassembly methods, encoding type,
etc.

Each individual ISA isntruction is implemented as
a class object in instructions.[hh|cc] and are derived
from one of the OP encoding types. The instructions.cc
file is primarily for the execute() methods of each
individual instruction, and the header file provides
the class definition and a few instruction specific
API calls.

Note that these instruction classes were auto-generated
but not using the gem5 ISA description language. A
custom ISA description was used and that cannot be released
publicly, therefore we are providing them already in C++.

Change-Id: I14d2a02d6b87109f41341c8f50a69a2cca9f3d14
---
M MAINTAINERS
A src/arch/gcn3/SConscript
A src/arch/gcn3/SConsopts
A src/arch/gcn3/decoder.cc
A src/arch/gcn3/gpu_decoder.hh
A src/arch/gcn3/gpu_isa.hh
A src/arch/gcn3/gpu_types.hh
A src/arch/gcn3/insts/gpu_static_inst.cc
A src/arch/gcn3/insts/gpu_static_inst.hh
A src/arch/gcn3/insts/inst_util.hh
A src/arch/gcn3/insts/instructions.cc
A src/arch/gcn3/insts/instructions.hh
A src/arch/gcn3/insts/op_encodings.cc
A src/arch/gcn3/insts/op_encodings.hh
A src/arch/gcn3/isa.cc
A src/arch/gcn3/operand.hh
A src/arch/gcn3/registers.cc
A src/arch/gcn3/registers.hh
M util/git-commit-msg.py
19 files changed, 139,749 insertions(+), 7 deletions(-)




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[gem5-dev] Change in gem5/gem5[develop]: misc: Add build opts for GCN3 GPU ISA

2020-04-23 Thread Anthony Gutierrez (Gerrit) via gem5-dev 

Hello Tony Gutierrez,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28130

to review the following change.


Change subject: misc: Add build opts for GCN3 GPU ISA
..

misc: Add build opts for GCN3 GPU ISA

Change-Id: I5f2662fe72d876b7bf816b0353aaefb85fc6c1c9
---
A build_opts/GCN3_X86
1 file changed, 5 insertions(+), 0 deletions(-)



diff --git a/build_opts/GCN3_X86 b/build_opts/GCN3_X86
new file mode 100644
index 000..21e3cf0
--- /dev/null
+++ b/build_opts/GCN3_X86
@@ -0,0 +1,5 @@
+PROTOCOL = 'GPU_VIPER'
+TARGET_ISA = 'x86'
+TARGET_GPU_ISA = 'gcn3'
+BUILD_GPU = True
+CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU'

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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add function to check for stalled msgs of addr

2020-04-23 Thread Anthony Gutierrez (Gerrit) via gem5-dev 

Hello Tony Gutierrez, Tuan Ta,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28133

to review the following change.


Change subject: mem-ruby: add function to check for stalled msgs of addr
..

mem-ruby: add function to check for stalled msgs of addr

This patch allows a cache controller to check if there
is any stalled message of a specific address in the
stall_map of an input message buffer.

Change-Id: Id2f9bb98a9201a562f2a8cc371e9bb896ac836af
---
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/MessageBuffer.hh
M src/mem/ruby/protocol/RubySlicc_Types.sm
3 files changed, 9 insertions(+), 1 deletion(-)



diff --git a/src/mem/ruby/network/MessageBuffer.cc  
b/src/mem/ruby/network/MessageBuffer.cc

index 6e14de1..3db8515 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -394,6 +394,12 @@
 m_stall_count++;
 }

+bool
+MessageBuffer::hasStalledMsg(Addr addr) const
+{
+return (m_stall_msg_map.count(addr) != 0);
+}
+
 void
 MessageBuffer::deferEnqueueingMessage(Addr addr, MsgPtr message)
 {
diff --git a/src/mem/ruby/network/MessageBuffer.hh  
b/src/mem/ruby/network/MessageBuffer.hh

index 01c0767..8abf3bd 100644
--- a/src/mem/ruby/network/MessageBuffer.hh
+++ b/src/mem/ruby/network/MessageBuffer.hh
@@ -74,6 +74,8 @@
 void reanalyzeMessages(Addr addr, Tick current_time);
 void reanalyzeAllMessages(Tick current_time);
 void stallMessage(Addr addr, Tick current_time);
+// return true if the stall map has a message of this address
+bool hasStalledMsg(Addr addr) const;

 // TRUE if head of queue timestamp <= SystemTime
 bool isReady(Tick current_time) const;
@@ -124,7 +126,6 @@
 // enqueue all previously deferred messages that are associated with  
the

 // input address
 void enqueueDeferredMessages(Addr addr, Tick curTime, Tick delay);
-
 bool isDeferredMsgMapEmpty(Addr addr) const;

 //! Updates the delay cycles of the message at the head of the queue,
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm  
b/src/mem/ruby/protocol/RubySlicc_Types.sm

index ccf881c..599a056 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -51,6 +51,7 @@
   bool isEmpty();
   bool isStallMapEmpty();
   int getStallMapSize();
+  bool hasStalledMsg(Addr addr);
 }

 external_type(NodeID, default="0", primitive="yes");

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: SVE instructions do not use AHP format

2020-04-23 Thread Giacomo Travaglini (Gerrit) via gem5-dev 

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28108

to review the following change.


Change subject: arch-arm: SVE instructions do not use AHP format
..

arch-arm: SVE instructions do not use AHP format

SVE half-precision floating-point instructions support only IEEE
754-2008 half-precision format and ignore the value of the FPCR.AHP bit,
behaving as if it has an Effective value of 0.

This patch is addressing this by masking the FPSCR.AHB bit before
passing it to fplib.

Change-Id: I1432fc3f7fefb81445fe042ae7d681f5cec40e64
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/isa/insts/sve.isa
M src/arch/arm/miscregs.hh
2 files changed, 11 insertions(+), 9 deletions(-)



diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b4c7fe5..deb12bc 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -2949,7 +2949,7 @@
 if (sub_i) {
 elt2_i = fplibNeg(elt2_i);
 }
-fpscr =  (FPSCR) FpscrExc;
+fpscr = FpscrExc & ~FpscrAhpMask;
 acc_r = fplibAdd(acc_r, elt2_i, fpscr);
 FpscrExc = fpscr;
 }
@@ -2957,7 +2957,7 @@
 if (sub_r) {
 elt2_r = fplibNeg(elt2_r);
 }
-fpscr =  (FPSCR) FpscrExc;
+fpscr = FpscrExc & ~FpscrAhpMask;
 acc_i = fplibAdd(acc_i, elt2_r, fpscr);
 FpscrExc = fpscr;
 }
@@ -3015,7 +3015,7 @@
 if (neg_r) {
 elt2_a = fplibNeg(elt2_a);
 }
-fpscr =  (FPSCR) FpscrExc;
+fpscr = FpscrExc & ~FpscrAhpMask;
 addend_r = fplibMulAdd(addend_r, elt1_a, elt2_a,  
fpscr);

 FpscrExc = fpscr;'''
 if predType != PredType.NONE:
@@ -3028,7 +3028,7 @@
 if (neg_i) {
 elt2_b = fplibNeg(elt2_b);
 }
-fpscr =  (FPSCR) FpscrExc;
+fpscr = FpscrExc & ~FpscrAhpMask;
 addend_i = fplibMulAdd(addend_i, elt1_a, elt2_b,  
fpscr);

 FpscrExc = fpscr;'''
 if predType != PredType.NONE:
@@ -3466,7 +3466,7 @@
 sveExtInst('ext', 'Ext', 'SimdAluOp')
 # FABD
 fpOp = '''
-FPSCR fpscr = (FPSCR) FpscrExc;
+FPSCR fpscr = FpscrExc & ~FpscrAhpMask;
 destElem = %s;
 FpscrExc = fpscr;
 '''
@@ -3497,7 +3497,7 @@
 sveBinInst('fadd', 'FaddUnpred', 'SimdFloatAddOp', floatTypes,  
faddCode)

 # FADDA
 fpAddaOp = '''
-FPSCR fpscr = (FPSCR) FpscrExc;
+FPSCR fpscr = FpscrExc & ~FpscrAhpMask;
 destElem = fplibAdd(destElem, srcElem1, fpscr);
 FpscrExc = FpscrExc | fpscr;
 '''
@@ -3505,7 +3505,7 @@
 fpAddaOp)
 # FADDV
 fpReduceOp = '''
-FPSCR fpscr = (FPSCR) FpscrExc;
+FPSCR fpscr = FpscrExc & ~FpscrAhpMask;
 destElem = fplib%s(srcElem1, srcElem2, fpscr);
 FpscrExc = FpscrExc | fpscr;
 '''
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 3900a4c..550b51c 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1936,10 +1936,12 @@
 // This mask selects bits of the FPSCR that actually go in the  
FpCondCodes

 // integer register to allow renaming.
 static const uint32_t FpCondCodesMask = 0xF000;
-// This mask selects the cumulative FP exception flags of the FPSCR.
-static const uint32_t FpscrExcMask = 0x009F;
 // This mask selects the cumulative saturation flag of the FPSCR.
 static const uint32_t FpscrQcMask = 0x0800;
+// This mask selects the AHP bit of the FPSCR.
+static const uint32_t FpscrAhpMask = 0x0400;
+// This mask selects the cumulative FP exception flags of the FPSCR.
+static const uint32_t FpscrExcMask = 0x009F;

 /**
  * Check for permission to read coprocessor registers.

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I1432fc3f7fefb81445fe042ae7d681f5cec40e64
Gerrit-Change-Number: 28108
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Do not increment exponent if FPSCR.FZ in fplib

2020-04-23 Thread Giacomo Travaglini (Gerrit) via gem5-dev 

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28107

to review the following change.


Change subject: arch-arm: Do not increment exponent if FPSCR.FZ in fplib
..

arch-arm: Do not increment exponent if FPSCR.FZ in fplib

If flushing to zero, the exponent shouldn't be incremented since
we are supposed to produce a 0 value and not a denormal number

Change-Id: Ib6dd594a6555b2fd9a20a52b59cbf1f5f94c2eb5
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/insts/fplib.cc
1 file changed, 25 insertions(+), 15 deletions(-)



diff --git a/src/arch/arm/insts/fplib.cc b/src/arch/arm/insts/fplib.cc
index 84ebe6d..a97943f 100644
--- a/src/arch/arm/insts/fplib.cc
+++ b/src/arch/arm/insts/fplib.cc
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2012-2013, 2017-2018 ARM Limited
+* Copyright (c) 2012-2013, 2017-2018, 2020 ARM Limited
 * Copyright (c) 2020 Metempsy Technology Consulting
 * All rights reserved
 *
@@ -393,14 +393,18 @@
 *exp = FP16_EXP(x);
 *mnt = FP16_MANT(x);

-// Handle subnormals:
 if (*exp) {
 *mnt |= 1ULL << FP16_MANT_BITS;
 } else {
-++*exp;
+// Handle subnormals:
 // IDC (Input Denormal) is not set in this case.
-if (mode & FPLIB_FZ16)
-*mnt = 0;
+if (*mnt) {
+if (mode & FPLIB_FZ16) {
+*mnt = 0;
+} else {
+++*exp;
+}
+}
 }
 }

@@ -412,14 +416,17 @@
 *exp = FP32_EXP(x);
 *mnt = FP32_MANT(x);

-// Handle subnormals:
 if (*exp) {
 *mnt |= 1ULL << FP32_MANT_BITS;
 } else {
-++*exp;
-if ((mode & FPLIB_FZ) && *mnt) {
-*flags |= FPLIB_IDC;
-*mnt = 0;
+// Handle subnormals:
+if (*mnt) {
+if (mode & FPLIB_FZ) {
+*flags |= FPLIB_IDC;
+*mnt = 0;
+} else {
+++*exp;
+}
 }
 }
 }
@@ -434,14 +441,17 @@
 *exp = FP64_EXP(x);
 *mnt = FP64_MANT(x);

-// Handle subnormals:
 if (*exp) {
 *mnt |= 1ULL << FP64_MANT_BITS;
 } else {
-++*exp;
-if ((mode & FPLIB_FZ) && *mnt) {
-*flags |= FPLIB_IDC;
-*mnt = 0;
+// Handle subnormals:
+if (*mnt) {
+if (mode & FPLIB_FZ) {
+*flags |= FPLIB_IDC;
+*mnt = 0;
+} else {
+++*exp;
+}
 }
 }
 }

--
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Gerrit-Change-Id: Ib6dd594a6555b2fd9a20a52b59cbf1f5f94c2eb5
Gerrit-Change-Number: 28107
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch: Fix VecReg container alignement to 128bits view

2020-04-23 Thread Jordi Vaquero (Gerrit) via gem5-dev 
Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27968 )


Change subject: arch: Fix VecReg container alignement to 128bits view
..

arch: Fix VecReg container alignement to 128bits view

This Patch will fix the alignment problem that appears sometimes
when we try to create a view of 128 bits over the VecRegContainer
object.

That container is initially created as std::array, so
there is no obligation to be aligned to 16 bytes. This patches forces
all containers to be aligned to 16 bytes.

The problem has been observed in the Jira Issue:
https://gem5.atlassian.net/browse/GEM5-320

Change-Id: Id9fdd427bd7a4dc904edd519f31cc29c5b29c5e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27968
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Ciro Santilli 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/generic/vec_reg.hh
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Ciro Santilli: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index 4156ac5..e26cf8b 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -279,7 +279,8 @@
 static constexpr inline size_t size() { return SIZE; };
 using Container = std::array;
   private:
-Container container;
+// 16-byte aligned to support 128bit element view
+alignas(16) Container container;
 using MyClass = VecRegContainer;

   public:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id9fdd427bd7a4dc904edd519f31cc29c5b29c5e6
Gerrit-Change-Number: 27968
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: Victor Soria 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Add an example workloads module

2020-04-23 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27969 )


Change subject: configs: Add an example workloads module
..

configs: Add an example workloads module

This will be a collection of Workload types.
At the moment we provide the following:

* ArmBaremetal: modelling a simple baremetal workload
* ArmTrustedFirmware: modelling the arm trusted firmware workload

Change-Id: Ib46286c03a1c952f981b172c1ea6aa4a6668757e
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Ciro Santilli 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27969
Tested-by: kokoro 
---
A configs/example/arm/workloads.py
1 file changed, 85 insertions(+), 0 deletions(-)

Approvals:
  Ciro Santilli: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/arm/workloads.py  
b/configs/example/arm/workloads.py

new file mode 100644
index 000..61e57f6
--- /dev/null
+++ b/configs/example/arm/workloads.py
@@ -0,0 +1,85 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+from __future__ import print_function
+from __future__ import absolute_import
+
+import m5
+from m5.objects import *
+from m5.options import *
+
+from common.SysPaths import binary, disk
+
+class ArmBaremetal(ArmFsWorkload):
+""" Baremetal workload """
+atags_addr = 0
+
+def __init__(self, obj, system, **kwargs):
+super(ArmBaremetal, self).__init__(**kwargs)
+
+self.object_file = obj
+
+class ArmTrustedFirmware(ArmFsWorkload):
+"""
+Arm Trusted Firmware (TFA) workload.
+
+It models the firmware design described at:
+
+ 
https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html

+
+The Workload is expecting to find a set of firmare images under
+the M5_PATH/binaries path. Those images are:
+* bl1.bin (BL1 = Stage 1 Bootloader)
+* fip.bin (FIP = Firmware Image Package):
+BL2, BL31, BL33 binaries compiled under a singe package
+
+These are the results of the compilation of Arm Trusted Firmware.
+https://github.com/ARM-software/arm-trusted-firmware
+
+"""
+atags_addr = 0
+
+def __init__(self, obj, system, **kwargs):
+super(ArmTrustedFirmware, self).__init__(**kwargs)
+
+self.extras = [ binary('bl1.bin'), binary('fip.bin'), ]
+self.extras_addrs = [
+system.realview.bootmem.range.start,
+system.realview.flash0.range.start
+]
+
+# Arm Trusted Firmware will provide a PSCI implementation
+system._have_psci = True

--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Use workloads.py in baremetal.py

2020-04-23 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27971 )


Change subject: configs: Use workloads.py in baremetal.py
..

configs: Use workloads.py in baremetal.py

Change-Id: I806b771df448241a7a61f496ac22c29d5bc6b84c
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27971
Reviewed-by: Daniel Carvalho 
Tested-by: kokoro 
---
M configs/example/arm/baremetal.py
1 file changed, 9 insertions(+), 3 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 00a350a..24f40ec 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -57,6 +57,7 @@
 from common.cores.arm import HPI

 import devices
+import workloads

 # Pre-defined CPU configurations. Each tuple must be ordered as :  
(cpu_class,
 # l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any  
of

@@ -100,9 +101,6 @@
   args.mem_size,
   platform=platform(),
   mem_mode=mem_mode,
-  workload=ArmFsWorkload(
-  atags_addr=0,
-  object_file=args.kernel),
   readfile=args.readfile)

 MemConfig.config_mem(args, system)
@@ -162,6 +160,10 @@
 system.have_virtualization = True
 system.have_security = True

+workload_class = workloads.workload_list.get(args.workload)
+system.workload = workload_class(
+args.kernel, system)
+
 return system

 def run(args):
@@ -190,6 +192,10 @@
 parser.add_argument("--kernel", type=str,
 default=None,
 help="Binary to run")
+parser.add_argument("--workload", type=str,
+default="ArmBaremetal",
+choices=workloads.workload_list.get_names(),
+help="Workload type")
 parser.add_argument("--disk-image", type=str,
 default=None,
 help="Disk to instantiate")

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I806b771df448241a7a61f496ac22c29d5bc6b84c
Gerrit-Change-Number: 27971
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Produce list of workload types in workloads.py

2020-04-23 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27970 )


Change subject: configs: Produce list of workload types in workloads.py
..

configs: Produce list of workload types in workloads.py

Change-Id: I3f585e006704e671775af8d66d241e555d34cb08
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27970
Reviewed-by: Daniel Carvalho 
Tested-by: kokoro 
---
M configs/example/arm/workloads.py
1 file changed, 11 insertions(+), 0 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/arm/workloads.py  
b/configs/example/arm/workloads.py

index 61e57f6..6952a4a 100644
--- a/configs/example/arm/workloads.py
+++ b/configs/example/arm/workloads.py
@@ -37,10 +37,12 @@
 from __future__ import print_function
 from __future__ import absolute_import

+import inspect
 import m5
 from m5.objects import *
 from m5.options import *

+from common.ObjectList import ObjectList
 from common.SysPaths import binary, disk

 class ArmBaremetal(ArmFsWorkload):
@@ -83,3 +85,12 @@

 # Arm Trusted Firmware will provide a PSCI implementation
 system._have_psci = True
+
+class _WorkloadList(ObjectList):
+def _add_objects(self):
+"""Add all sub-classes of the base class in the object  
hierarchy."""

+modname = sys.modules[__name__]
+for name, cls in inspect.getmembers(modname, self._is_obj_class):
+self._sub_classes[name] = cls
+
+workload_list = _WorkloadList(getattr(m5.objects, 'ArmFsWorkload', None))

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3f585e006704e671775af8d66d241e555d34cb08
Gerrit-Change-Number: 27970
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Add hsub instructions to x86

2020-04-23 Thread Mahyar Samani (Gerrit) via gem5-dev 
Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26123 )


Change subject: arch-x86: Add hsub instructions to x86
..

arch-x86: Add hsub instructions to x86

Implemented hsubpd and hsubps instructions from x86.

Issue-on: https://gem5.atlassian.net/browse/GEM5-181
Change-Id: I62919017d3c00119123bda89b2f99cb3bf0b55a8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26123
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M  
src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py

2 files changed, 49 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa  
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa

index c7c62c2..28affdb 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -691,7 +691,7 @@
 // operand size (0x66)
 0x1: decode OPCODE_OP_BOTTOM3 {
 0x4: HADDPD(Vo,Wo);
-0x5: WarnUnimpl::hsubpd_Vo_Wo();
+0x5: HSUBPD(Vo, Wo);
 0x6: MOVD(Edp,Vd);
 0x7: MOVDQA(Wo,Vo);
 default: UD2();
@@ -699,7 +699,7 @@
 // repne (0xF2)
 0x8: decode OPCODE_OP_BOTTOM3 {
 0x4: HADDPS(Vo,Wo);
-0x5: WarnUnimpl::hsubps_Vo_Wo();
+0x5: HSUBPS(Vo, Wo);
 default: UD2();
 }
 default: UD2();
diff --git  
a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py  
b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py

index a629ecd..43523c1 100644
---  
a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py
+++  
b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py

@@ -34,6 +34,51 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 microcode = '''
-# HSUBPS
-# HSUBPD
+def macroop HSUBPS_XMM_XMM {
+shuffle ufp1, xmml, xmmh, ext=((0 << 0) | (2 << 2)), size=4
+shuffle ufp2, xmml, xmmh, ext=((1 << 0) | (3 << 2)), size=4
+shuffle ufp3, xmmlm, xmmhm, ext=((0 << 0) | (2 << 2)), size=4
+shuffle ufp4, xmmlm, xmmhm, ext=((1 << 0) | (3 << 2)), size=4
+msubf xmml, ufp1, ufp2, size=4
+msubf xmmh, ufp3, ufp4, size=4
+};
+def macroop HSUBPS_XMM_M {
+ldfp ufp1, seg, sib, disp, dataSize=8
+ldfp ufp2, seg, sib, "DISPLACEMENT+8", dataSize=8
+shuffle ufp3, xmml, xmmh, ext=((0 << 0) | (2 << 2)), size=4
+shuffle ufp4, xmml, xmmh, ext=((1 << 0) | (3 << 2)), size=4
+shuffle ufp5, ufp1, ufp2, ext=((0 << 0) | (2 << 2)), size=4
+shuffle ufp6, ufp1, ufp2, ext=((1 << 0) | (3 << 2)), size=4
+msubf xmml, ufp3, ufp4, size=4
+msubf xmmh, ufp5, ufp6, size=4
+};
+def macroop HSUBPS_XMM_P {
+rdip t7
+ldfp ufp1, seg, riprel, disp, dataSize=8
+ldfp ufp2, seg, riprel, "DISPLACEMENT+8", dataSize=8
+shuffle ufp3, xmml, xmmh, ext=((0 << 0) | (2 << 2)), size=4
+shuffle ufp4, xmml, xmmh, ext=((1 << 0) | (3 << 2)), size=4
+shuffle ufp5, ufp1, ufp2, ext=((0 << 0) | (2 << 2)), size=4
+shuffle ufp6, ufp1, ufp2, ext=((1 << 0) | (3 << 2)), size=4
+msubf xmml, ufp3, ufp4, size=4
+msubf xmmh, ufp5, ufp6, size=4
+};
+def macroop HSUBPD_XMM_XMM {
+msubf ufp1, xmmh , xmml, size=8, ext=Scalar
+msubf xmmh, xmmlm, xmmhm, size=8, ext=Scalar
+movfp xmml, ufp1
+};
+def macroop HSUBPD_XMM_M {
+ldfp ufp1, seg, sib, disp, dataSize=8
+ldfp ufp2, seg, sib, "DISPLACEMENT+8", dataSize=8
+msubf xmml, xmml, xmmh, size=8, ext=Scalar
+msubf xmmh, ufp1, ufp2, size=8, ext=Scalar
+};
+def macroop HSUBPD_XMM_P {
+rdip t7
+ldfp ufp1, seg, riprel, disp, dataSize=8
+ldfp ufp2, seg, riprel, "DISPLACEMENT+8", dataSize=8
+msubf xmml, xmml, xmmh, size=8, ext=Scalar
+msubf xmmh, ufp1, ufp2, size=8, ext=Scalar
+};
 '''

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I62919017d3c00119123bda89b2f99cb3bf0b55a8
Gerrit-Change-Number: 26123
Gerrit-PatchSet: 8
Gerrit-Owner: Mahyar Samani 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Mahyar Samani 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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