[gem5-dev] Build failed in Jenkins: compiler-checks #558

2023-03-29 Thread jenkins-no-reply--- via gem5-dev 
See 


Changes:

[Bobby R. Bruce] tests: Fix Replacement Policy Tests

[Bobby R. Bruce] tests: Fix the Weekly arm-boot-tests

[Bobby R. Bruce] tests: Check if ARM/gem5.opt not built in test_hdf5.py

[Bobby R. Bruce] tests: Disable the looppoint checkpoint tests

[Bobby R. Bruce] tests: Add "run threads" optional parameter to weekly.sh

[huxuan0307] ext: Update softfloat to 3d full version

[gabe.black] base,cpu,dev,sim: Pull common logic into ListenSocket::listen().

[gabe.black] base: Make ListenSocket::listen(int port) protected.


--
[...truncated 1.03 KB...]
 > git checkout -f 7c614d225be30439d1912872128b79c5a3e0c85f # timeout=10
Commit message: "base: Make ListenSocket::listen(int port) protected."
 > git rev-list --no-walk 8dfaec0e104c8802c96573784e784811d5940262 # timeout=10
[Checks API] No suitable checks publisher found.
[compiler-checks] $ /bin/sh -xe /tmp/jenkins15902625868685756583.sh
+ ./tests/compiler-tests.sh -j 16
Starting build tests with 'gcc-version-12'...
'gcc-version-12' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-12'...
Done.
  * Building target 'GCN3_X86.opt' with 'gcc-version-12'...
Done.
  * Building target 'GCN3_X86.fast' with 'gcc-version-12'...
Done.
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-12'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-12'...
Done.
  * Building target 'SPARC.opt' with 'gcc-version-12'...
Done.
  * Building target 'SPARC.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-12'...
Done.
  * Building target 'MIPS.opt' with 'gcc-version-12'...
Done.
  * Building target 'MIPS.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.fast' with 'gcc-version-12'...
Done.
  * Building target 'Garnet_standalone.opt' with 'gcc-version-12'...
Done.
  * Building target 'Garnet_standalone.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-12'...
Done.
  * Building target 'POWER.opt' with 'gcc-version-12'...
Done.
  * Building target 'POWER.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM.fast' with 'gcc-version-12'...
Done.
  * Building target 'ALL.opt' with 'gcc-version-12'...
  ! Failed with exit code 137.
  * Building target 'ALL.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-12'...
Done.
  * Building target 'X86.opt' with 'gcc-version-12'...
Done.
  * Building target 'X86.fast' with 'gcc-version-12'...
Done.
  * Building target 'RISCV.opt' with 'gcc-version-12'...
Done.
  * Building target 'RISCV.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL.fast' with 'gcc-version-12'...
Done.
  * Building target 'X86_MI_example.opt' with 'gcc-version-12'...
Done.
  * Building target 'X86_MI_example.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-12'...
Done.
Starting build tests with 'gcc-version-11'...
  * Building target 'NULL.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL.fast' with 'gcc-version-11'...
Done.
Starting build tests with 'gcc-version-10'...
  * Building target 'X86_MI_example.opt' with 'gcc-version-10'...
Done.
  * Building target 'X86_MI_example.fast' with 'gcc-version-10'...
Done.
Starting build tests with 'gcc-version-9'...
  * Building target 'POWER.opt' with 'gcc-version-9'...
Done.
  * Building target 'POWER.fast' with 'gcc-version-9'...
Done.
Starting build tests with 'gcc-version-8'...
  * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-8'...
Done.
  * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-8'...
Done.
Starting build tests with 'gcc-version-7'...
  * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-7'...
Done.
  * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-7'...

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: This commit fix incorrect ARM isa implementation

2023-03-29 Thread Marco Chen (Gerrit) via gem5-dev 
Marco Chen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69318?usp=email )


Change subject: arch-arm: This commit fix incorrect ARM isa implementation
..

arch-arm: This commit fix incorrect ARM isa implementation

When running 500.perlbench_r of specint 2017, the system will raise an
 assertion error. For function bits of src/base/bitfield.hh (line 76),
 the parameter First is smaller than Last. This is caused by incorrect
 implementation of uqrshl in src/arch/arm/isa/insts/neon64.isa

When shiftAmt equals 0, which mean uqrshl is actually not shift the
 value stored in register. sizeof(Element) * 8 - 1 will be smaller than
 sizeof(Element) * 8 - shiftAmt, thus will raise the assertion error.

This commit added this special condition.

No Jira issue has been submitted to report this error

Change-Id: I4162ac3ddb62f162619db400f214f33209b23c19
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69318
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
---
M src/arch/arm/isa/insts/neon64.isa
1 file changed, 3 insertions(+), 2 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa/insts/neon64.isa  
b/src/arch/arm/isa/insts/neon64.isa

index d867907..e0083c9 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -3255,8 +3255,9 @@
 destElem = 0;
 }
 } else {
-if (bits(srcElem1, sizeof(Element) * 8 - 1,
-sizeof(Element) * 8 - shiftAmt)) {
+if (shiftAmt != 0 &&
+bits(srcElem1, sizeof(Element) * 8 - 1,
+   sizeof(Element) * 8 -  
shiftAmt)) {

 destElem = mask(sizeof(Element) * 8);
 fpscr.qc = 1;
 } else {

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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I4162ac3ddb62f162619db400f214f33209b23c19
Gerrit-Change-Number: 69318
Gerrit-PatchSet: 2
Gerrit-Owner: Marco Chen 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Marco Chen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: Small fix in stdlib spec2006 script The call to processor swi...

2023-03-29 Thread humza jahangir ikram (Gerrit) via gem5-dev 
humza jahangir ikram has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69357?usp=email )



Change subject: stdlib: Small fix in stdlib spec2006 script The call to  
processor switch from KVM to TIMING was removed in an earlier commit. This  
change fixes that. Also, get_roi_ticks() doesn't work because spec2006 does  
not have work_begin and work_exit annotations. This change uses  
get_tick_stopwatch() to calculate the roi ticks.

..

stdlib: Small fix in stdlib spec2006 script
The call to processor switch from KVM to TIMING was
removed in an earlier commit. This change fixes that.
Also, get_roi_ticks() doesn't work because spec2006
does not have work_begin and work_exit annotations.
This change uses get_tick_stopwatch() to calculate
the roi ticks.

Change-Id: I55efe28ebd686cb4e6c88a528533127fb73c88ed
---
M configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
1 file changed, 6 insertions(+), 1 deletion(-)



diff --git a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py  
b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py

index a681eca..e7a9e82 100644
--- a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
@@ -272,6 +272,7 @@
 print("Done bootling Linux")
 print("Resetting stats at the start of ROI!")
 m5.stats.reset()
+processor.switch()
 yield False  # E.g., continue the simulation.
 print("Dump stats at the end of the ROI!")
 m5.stats.dump()
@@ -304,7 +305,11 @@

 print("Performance statistics:")

-print("Simulated time: " + ((str(simulator.get_roi_ticks()[0]
+roi_begin_ticks = simulator.get_tick_stopwatch()[0][1]
+roi_end_ticks = simulator.get_tick_stopwatch()[0][1]
+
+print("roi simulated ticks: " + str(roi_end_ticks - roi_begin_ticks))
+
 print(
 "Ran a total of", simulator.get_current_tick() / 1e12, "simulated  
seconds"

 )

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Gerrit-Change-Number: 69357
Gerrit-PatchSet: 1
Gerrit-Owner: humza jahangir ikram 
Gerrit-MessageType: newchange
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[gem5-dev] [L] Change in gem5/gem5[develop]: mem: Add DRAMSys wrapper as a memory object

2023-03-29 Thread Derek C. (Gerrit) via gem5-dev 
Derek C. has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/62912?usp=email )


Change subject: mem: Add DRAMSys wrapper as a memory object
..

mem: Add DRAMSys wrapper as a memory object

Add a DRAMSys wrapper to the gem5 memory source that
instantiates the DRAMSys simulator.
Another DRAMSys SimObject implements the AbstractMemory
interface and exposes the tlm target socket.

Change-Id: I8a95e729905e0924453043e5e7744df7a7ce4548
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62912
Tested-by: kokoro 
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
---
M ext/dramsys/SConscript
A src/mem/DRAMSys.py
M src/mem/SConscript
A src/mem/dramsys.hh
A src/mem/dramsys_wrapper.cc
A src/mem/dramsys_wrapper.hh
A src/python/gem5/components/memory/dramsys.py
7 files changed, 426 insertions(+), 24 deletions(-)

Approvals:
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved




diff --git a/ext/dramsys/SConscript b/ext/dramsys/SConscript
index d771b9c..d6ea27e 100644
--- a/ext/dramsys/SConscript
+++ b/ext/dramsys/SConscript
@@ -1,32 +1,28 @@
-# Copyright (c) 2022, Fraunhofer IESE
-# All rights reserved.
+# Copyright (c) 2022 Fraunhofer IESE
+# All rights reserved
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
-# met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-#this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright
-#notice, this list of conditions and the following disclaimer in the
-#documentation and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-#contributors may be used to endorse or promote products derived from
-#this software without specific prior written permission.
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
 #
 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A  
PARTICULAR

-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 import os

diff --git a/src/mem/DRAMSys.py b/src/mem/DRAMSys.py
new file mode 100644
index 000..c7d69a0
--- /dev/null
+++ b/src/mem/DRAMSys.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2022 Fraunhofer IESE
+# All rights reserved
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software

[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Add DRAMSys compilation and scripts to Weekly tests

2023-03-29 Thread Derek C. (Gerrit) via gem5-dev 
Derek C. has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69200?usp=email )


Change subject: tests: Add DRAMSys compilation and scripts to Weekly tests
..

tests: Add DRAMSys compilation and scripts to Weekly tests

Change-Id: I4353843e4e5f6db6f6d576dec4a34c3d403da1cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69200
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
---
M tests/weekly.sh
1 file changed, 36 insertions(+), 0 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/weekly.sh b/tests/weekly.sh
index d07cc8b..9c7ebdf 100755
--- a/tests/weekly.sh
+++ b/tests/weekly.sh
@@ -398,3 +398,39 @@

 # delete Pannotia datasets we downloaded and output files it created
 rm -f coAuthorsDBLP.graph 1k_128k.gr result.out
+
+# Run tests to ensure the DRAMSys integration is still functioning  
correctly.

+if [ -d "${gem5_root}/ext/dramsys/DRAMSys" ]; then
+rm -r "${gem5_root}/ext/dramsys/DRAMSys"
+fi
+
+cd "${gem5_root}/ext/dramsys"
+git clone --recursive g...@github.com:tukl-msd/DRAMSys.git DRAMSys
+cd DRAMSys
+git checkout -b gem5 09f6dcbb91351e6ee7cadfc7bc8b29d97625db8f
+cd "${gem5_root}"
+
+rm -rf "${gem5_root}/build/ALL"
+
+docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
+"${gem5_root}" --memory="${docker_mem_limit}" --rm \
+gcr.io/gem5-test/ubuntu-22.04_all-dependencies:${tag} \
+   scons build/ALL/gem5.opt -j${threads}
+
+docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
+"${gem5_root}" --memory="${docker_mem_limit}" --rm \
+gcr.io/gem5-test/ubuntu-22.04_all-dependencies:${tag} \
+   ./build/ALL/gem5.opt \
+   configs/example/gem5_library/dramsys/arm-hello-dramsys.py
+
+docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
+"${gem5_root}" --memory="${docker_mem_limit}" --rm \
+gcr.io/gem5-test/ubuntu-22.04_all-dependencies:${tag} \
+   ./build/ALL/gem5.opt \
+   configs/example/gem5_library/dramsys/dramsys-traffic.py
+
+docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
+"${gem5_root}" --memory="${docker_mem_limit}" --rm \
+gcr.io/gem5-test/ubuntu-22.04_all-dependencies:${tag} \
+   ./build/ALL/gem5.opt \
+   configs/example/dramsys.py

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4353843e4e5f6db6f6d576dec4a34c3d403da1cc
Gerrit-Change-Number: 69200
Gerrit-PatchSet: 4
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Derek C. 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: configs: Add DRAMSys config example

2023-03-29 Thread Derek C. (Gerrit) via gem5-dev 
Derek C. has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/62913?usp=email )


Change subject: configs: Add DRAMSys config example
..

configs: Add DRAMSys config example

Add an example configuration for gem5 that runs the
DRAMSys simulator with a TrafficGenerator initiator.

Change-Id: If90f49fcc05b73905b2f9dc8b7aadfdbd866340a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62913
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
A configs/example/dramsys.py
1 file changed, 63 insertions(+), 0 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/dramsys.py b/configs/example/dramsys.py
new file mode 100755
index 000..934ff17
--- /dev/null
+++ b/configs/example/dramsys.py
@@ -0,0 +1,63 @@
+# Copyright (c) 2022 Fraunhofer IESE
+# All rights reserved
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import m5
+
+from m5.objects import *
+
+traffic_gen = PyTrafficGen()
+system = System()
+vd = VoltageDomain(voltage="1V")
+
+system.mem_mode = "timing"
+
+system.cpu = traffic_gen
+
+dramsys = DRAMSys(
+configuration="ext/dramsys/DRAMSys/DRAMSys/"
+"library/resources/simulations/ddr4-example.json",
+resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
+)
+
+system.target = dramsys
+system.transactor = Gem5ToTlmBridge32()
+system.clk_domain = SrcClockDomain(clock="1.5GHz", voltage_domain=vd)
+
+# Connect everything:
+system.transactor.gem5 = system.cpu.port
+system.transactor.tlm = system.target.tlm
+
+kernel = SystemC_Kernel(system=system)
+root = Root(full_system=False, systemc_kernel=kernel)
+
+m5.instantiate()
+idle = traffic_gen.createIdle(10)
+linear = traffic_gen.createLinear(1000, 0, 16777216, 64, 500, 1500,  
65, 0)
+random = traffic_gen.createRandom(1000, 0, 16777216, 64, 500, 1500,  
65, 0)

+traffic_gen.start([linear, idle, random])
+
+cause = m5.simulate(2000).getCause()
+print(cause)

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Gerrit-Project: public/gem5
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Gerrit-Change-Number: 62913
Gerrit-PatchSet: 9
Gerrit-Owner: Derek C. 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Derek C. 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib,configs: Add DRAMSys to the gem5 standard library

2023-03-29 Thread Derek C. (Gerrit) via gem5-dev 
Derek C. has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/62914?usp=email )


Change subject: stdlib,configs: Add DRAMSys to the gem5 standard library
..

stdlib,configs: Add DRAMSys to the gem5 standard library

Add DRAMSys as a new AbstractMemorySystem to the gem5 stdlib.
Also, provide convenient subclasses with predefined DRAMSys
configurations.

Add two new stdlib examples:
- dramsys-traffic.py: Demonstrates the usage of DRAMSys
  using the stdlib TrafficGenerators
- arm-hello-dramsys.py: A variant of the arm-hello.py
  script that uses DRAMSys as it's memory.

These DRAMSys memory components are only compiled into the standard
library if DRAMSys is not compiled into gem5.

Change-Id: I9db87c41fbd9c28bc44e9d6bde13fc225dc16be9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62914
Tested-by: kokoro 
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
---
A configs/example/gem5_library/dramsys/arm-hello-dramsys.py
A configs/example/gem5_library/dramsys/dramsys-traffic.py
M src/mem/dramsys_wrapper.hh
M src/python/SConscript
M src/python/gem5/components/memory/__init__.py
M src/python/gem5/components/memory/dramsys.py
6 files changed, 241 insertions(+), 7 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/dramsys/arm-hello-dramsys.py  
b/configs/example/gem5_library/dramsys/arm-hello-dramsys.py

new file mode 100644
index 000..8b25a36
--- /dev/null
+++ b/configs/example/gem5_library/dramsys/arm-hello-dramsys.py
@@ -0,0 +1,92 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This gem5 configuation script creates a simple board to run an ARM
+"hello world" binary using the DRAMSys simulator.
+
+**Important Note**: DRAMSys must be compiled into the gem5 binary to use  
the

+DRRAMSys simulator. Please consult 'ext/dramsys/README' on how to compile
+correctly. If this is not done correctly this script will run with error.
+"""
+
+from gem5.isas import ISA
+from gem5.utils.requires import requires
+from gem5.resources.resource import Resource
+from gem5.components.memory import DRAMSysDDR3_1600
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.boards.simple_board import SimpleBoard
+from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy  
import (

+PrivateL1CacheHierarchy,
+)
+from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.simulate.simulator import Simulator
+
+# This check ensures the gem5 binary is compiled to the ARM ISA target. If  
not,

+# an exception will be thrown.
+requires(isa_required=ISA.ARM)
+
+# We need a cache as DRAMSys only accepts requests with the size of a  
cache line

+cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="32kB", l1i_size="32kB")
+
+# We use a single channel DDR3_1600 memory system
+memory = DRAMSysDDR3_1600(recordable=True)
+
+# We use a simple Timing processor with one core.
+processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.ARM,  
num_cores=1)

+
+# The gem5 library simble board which can be used to run simple SE-mode
+# simulations.
+board = SimpleBoard(
+clk_freq="3GHz",
+processor=processor,
+memory=memory,
+cache_hierarchy=cache_hierarchy,
+)
+
+# Here we set the workload. In this case we want

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Use get_mem_ports in incorporate caches

2023-03-29 Thread Derek C. (Gerrit) via gem5-dev 
Derek C. has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68482?usp=email )


Change subject: stdlib: Use get_mem_ports in incorporate caches
..

stdlib: Use get_mem_ports in incorporate caches

Make use of get_mem_ports() method of the AbstractMemorySystem
interface when incorporating caches to prevent the usage of the
hard-coded memory port name "port" as some memory controllers do
not have a port with this exact name.

Change-Id: Ic7480166b257c6d356027234758b65b0a97995e3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68482
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
---
M src/python/gem5/components/cachehierarchies/classic/no_cache.py
M  
src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
M  
src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
M  
src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py

4 files changed, 8 insertions(+), 8 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git  
a/src/python/gem5/components/cachehierarchies/classic/no_cache.py  
b/src/python/gem5/components/cachehierarchies/classic/no_cache.py

index f3bbdcd..51b5d30 100644
--- a/src/python/gem5/components/cachehierarchies/classic/no_cache.py
+++ b/src/python/gem5/components/cachehierarchies/classic/no_cache.py
@@ -119,8 +119,8 @@
 # Set up the system port for functional access from the simulator.
 board.connect_system_port(self.membus.cpu_side_ports)

-for cntr in board.get_memory().get_memory_controllers():
-cntr.port = self.membus.mem_side_ports
+for _, port in board.get_memory().get_mem_ports():
+self.membus.mem_side_ports = port

 def _setup_coherent_io_bridge(self, board: AbstractBoard) -> None:
 """Create a bridge from I/O back to membus"""
diff --git  
a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py

index dc44c9e..42ff183 100644
---  
a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py

@@ -90,8 +90,8 @@
 # Set up the system port for functional access from the simulator.
 board.connect_system_port(self.membus.cpu_side_ports)

-for cntr in board.get_memory().get_memory_controllers():
-cntr.port = self.membus.mem_side_ports
+for _, port in board.get_memory().get_mem_ports():
+self.membus.mem_side_ports = port

 self.l1icaches = [
 L1ICache(size=self._l1i_size)
diff --git  
a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

index f10828b..8b60aef 100644
---  
a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

@@ -115,8 +115,8 @@
 # Set up the system port for functional access from the simulator.
 board.connect_system_port(self.membus.cpu_side_ports)

-for cntr in board.get_memory().get_memory_controllers():
-cntr.port = self.membus.mem_side_ports
+for _, port in board.get_memory().get_mem_ports():
+self.membus.mem_side_ports = port

 self.l1icaches = [
 L1ICache(size=self._l1i_size)
diff --git  
a/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py

index 602c99c..72df1a5 100644
---  
a/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py

@@ -111,8 +111,8 @@
 # Set up the system port for functional access from the simulator.
 board.connect_system_port(self.membus.cpu_side_ports)

-for cntr in board.get_memory().get_memory_controllers():
-cntr.port = self.membus.mem_side_ports
+for _, port in board.get_memory().get_mem_ports():
+self.membus.mem_side_ports = port

 self.l1icaches = [
 L1ICache(

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/68482?usp=email
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic7480166b257c6d356027234758b65b0a97995e3

[gem5-dev] [M] Change in gem5/gem5[develop]: ext: Add DRAMSys integration instructions

2023-03-29 Thread Derek C. (Gerrit) via gem5-dev 
Derek C. has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/62911?usp=email )


Change subject: ext: Add DRAMSys integration instructions
..

ext: Add DRAMSys integration instructions

Add instructions to add the DRAMSys memory simulator
to gem5 in the ext/ directory.
The provided SConscript file compiles DRAMSys.

Change-Id: If5c723db61a3151c9155190f968c66927d7bfaa3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62911
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
A ext/dramsys/README
A ext/dramsys/SConscript
2 files changed, 110 insertions(+), 0 deletions(-)

Approvals:
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved




diff --git a/ext/dramsys/README b/ext/dramsys/README
new file mode 100644
index 000..477da52
--- /dev/null
+++ b/ext/dramsys/README
@@ -0,0 +1,10 @@
+Follow these steps to get DRAMSys as part of gem5
+
+1. Go to ext/dramsys (this directory)
+2. Clone DRAMSys: 'git clone --recursive  
g...@github.com:tukl-msd/DRAMSys.git DRAMSys'

+3. Change directory to DRAMSys: 'cd DRAMSys'
+4. Checkout the correct commit: 'git checkout -b gem5  
09f6dcbb91351e6ee7cadfc7bc8b29d97625db8f'

+
+If you wish to run a simulation using the gem5 processor cores, make sure  
to enable the storage mode in DRAMSys.
+This is done by setting the value of the "StoreMode" key to "Store" in the  
base configuration file.
+Those configuration file can be found  
in 'DRAMSys/library/resources/configs/simulator'.

diff --git a/ext/dramsys/SConscript b/ext/dramsys/SConscript
new file mode 100644
index 000..d771b9c
--- /dev/null
+++ b/ext/dramsys/SConscript
@@ -0,0 +1,100 @@
+# Copyright (c) 2022, Fraunhofer IESE
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+#this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+#notice, this list of conditions and the following disclaimer in the
+#documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+#contributors may be used to endorse or promote products derived from
+#this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A  
PARTICULAR

+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+
+Import('env')
+
+build_root = Dir('../..').abspath
+src_root = Dir('DRAMSys/DRAMSys/library').srcnode().abspath
+
+# See if we got a cloned DRAMSys repo as a subdirectory and set the
+# HAVE_DRAMSys flag accordingly
+if not os.path.exists(Dir('.').srcnode().abspath + '/DRAMSys'):
+env['HAVE_DRAMSYS'] = False
+Return()
+
+env['HAVE_DRAMSYS'] = True
+
+dramsys_files = []
+dramsys_configuration_files = []
+
+dramsys_files.extend(Glob("%s/*.cpp" % f"{src_root}/src/controller"))
+for root, dirs, files in os.walk(f"{src_root}/src/controller",  
topdown=False):

+for dir in dirs:
+dramsys_files.extend(Glob("%s/*.cpp" % os.path.join(root, dir)))
+
+dramsys_files.extend(Glob("%s/*.cpp" % f"{src_root}/src/simulation"))
+for root, dirs, files in os.walk(f"{src_root}/src/simulation",  
topdown=False):

+for dir in dirs:
+dramsys_files.extend(Glob("%s/*.cpp" % os.path.join(root, dir)))
+
+dramsys_files.extend(Glob("%s/*.cpp" % f"{src_root}/src/configuration"))
+for root, dirs, files in os.walk(f"{src_root}/src/configuration",  
topdown=False):

+for dir in dirs:
+dramsys_files.extend(Glob("%s/*.cpp" % os.path.join(root, dir)))
+
+dramsys_files.extend(Glob("%s/*.cpp" % f"{src_root}/src/error"))
+dramsys_files.extend(Glob(f"{src_root}/src/error/ECC/Bit.cpp"))
+dramsys_files.extend(Glob(f"{src_root}/src/error/ECC/ECC.cpp"))
+dramsys_files.extend(Glob(f"{src_root}/src/error/ECC/Word.cpp"))
+
+dramsys_files.extend(Glob("%s/*.cpp" % f"{src_root}/src/common"))
+dramsys_files.extend(Glob("%s/*.cpp" %  
f"{src_root}/src/common/configuration"))

[gem5-dev] Build failed in Jenkins: weekly #114

2023-03-29 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[yazakram] stdlib: Small fix in mesi three level component

[Bobby R. Bruce] util-docker: Update systemc docker image to use 22.04

[Bobby R. Bruce] tests: Fix Replacement Policy Tests

[Bobby R. Bruce] tests: Fix the Weekly arm-boot-tests

[Bobby R. Bruce] tests: Check if ARM/gem5.opt not built in test_hdf5.py

[Bobby R. Bruce] tests: Disable the looppoint checkpoint tests

[Bobby R. Bruce] tests: Add "run threads" optional parameter to weekly.sh


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 [SO

[gem5-dev] Build failed in Jenkins: nightly #559

2023-03-29 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[huxuan0307] ext: Update softfloat to 3d full version

[gabe.black] base,cpu,dev,sim: Pull common logic into ListenSocket::listen().

[gabe.black] base: Make ListenSocket::listen(int port) protected.


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 [ TRACING]  -> ALL_MSI/debug/Writeback.cc
 [ CXX] ALL_MSI/debug/StoreSet.cc -> .o
 [ CXX] ALL_MSI/debug/Writeback.cc -> .o
 [ TRACING]  -> ALL_MSI/debug/O3CPUAll.cc
 [ TRACING]  -> ALL_MSI/debug/O3CPUAll.hh
 [ CXX] ALL_MSI/cpu/o3/BaseO3Checker.py.cc -> .o
 [ CXX] ALL_MSI/debug/O3CPUAll.cc -> .o
 [SO Param] m5.objects.BaseO3Checker, BaseO3Checker -> 
ALL_MSI/python/_m5/param_BaseO3Checker.cc
 [ CXX] ALL_MSI/cpu/o3/checker.cc -> .o
 [ CXX] ALL_MSI/cpu/o3/O3CPU.py.cc -> .o
 [ CXX] ALL_MSI/cpu/o3/O3Checker.py.cc -> .o
 [ CXX] ALL_MSI/cpu/o3/probe/SimpleTrace.py.cc -> .o
 [SO Param] m5.objects.SimpleTrace, SimpleTrace -> 
ALL_MSI/python/_m5/param_SimpleTrace.cc
 [SO Param] m5.objects.BaseO3Checker, BaseO3Checker -> 
ALL_MSI/params/BaseO3Checker.hh
 [ TRACING]  -> ALL_MSI/debug/SimpleTrace.hh
 [SO Param] m5.objects.SimpleTrace, SimpleTrace -> ALL_MSI/params/SimpleTrace.hh
 [ TRACING]  -> ALL_MSI/debug/SimpleTrace.cc
 [ CXX] ALL_MSI/cpu/o3/probe/ElasticTrace.py.cc -> .o
 [ CXX] ALL_MSI/python/_m5/param_BaseO3Checker.cc -> .o
 [ CXX] ALL_MSI/debug/SimpleTrace.cc -> .o
 [SO Param] m5.objects.ElasticTrace, ElasticTrace -> 
ALL_MSI/python/_m5/param_ElasticTrace.cc
 [ CXX] ALL_MSI/cpu/o3/probe/simple_trace.cc -> .o
 [SO Param] m5.objects.ElasticTrace, ElasticTrace -> 
ALL_MSI/params/ElasticTrace.hh
 [  PROTOC] ALL_MSI/proto/inst_dep_record.proto -> 
ALL_MSI/proto/inst_dep_record.pb.cc, ALL_MSI/proto/inst_dep_record.pb.h
 [  PROTOC] ALL_MSI/proto/packet.proto -> ALL_MSI/proto/packet.pb.cc, 
ALL_MSI/proto/packet.pb.h
 [ CXX] ALL_MSI/python/_m5/param_SimpleTrace.cc -> .o
 [ TRACING]  -> ALL_MSI/debug/ElasticTrace.hh
 [ TRACING]  -> ALL_MSI/debug/ElasticTrace.cc
 [ CXX] ALL_MSI/cpu/trace/TraceCPU.py.cc -> .o
 [SO Param] m5.objects.TraceCPU, TraceCPU -> 
ALL_MSI/python/_m5/param_TraceCPU.cc
 [ CXX] ALL_MSI/debug/ElasticTrace.cc -> .o
 [ CXX] ALL_MSI/cpu/o3/probe/elastic_trace.cc -> .o
 [SO Param] m5.objects.TraceCPU, TraceCPU -> ALL_MSI/params/TraceCPU.hh
 [ TRACING]  -> ALL_MSI/debug/TraceCPUData.hh
 [ TRACING]  -> ALL_MSI/debug/TraceCPUInst.hh
 [ CXX] ALL_MSI/python/_m5/param_ElasticTrace.cc -> .o
 [ CXX] ALL_MSI/python/_m5/param_TraceCPU.cc -> .o
 [ CXX] ALL_MSI/cpu/trace/trace_cpu.cc -> .o
 [ TRACING]  -> ALL_MSI/debug/TraceCPUData.cc
 [ CXX] ALL_MSI/debug/TraceCPUData.cc -> .o
 [ TRACING]  -> ALL_MSI/debug/TraceCPUInst.cc
 [ CXX] ALL_MSI/debug/TraceCPUInst.cc -> .o
 [ CXX] ALL_MSI/cpu/testers/directedtest/RubyDirectedTester.py.cc -> .o
 [SO Param] m5.objects.RubyDirectedTester, DirectedGenerator -> 
ALL_MSI/python/_m5/param_DirectedGenerator.cc
 [SO Param] m5.objects.RubyDirectedTester, SeriesRequestGenerator -> 
ALL_MSI/python/_m5/param_SeriesRequestGenerator.cc
 [SO Param] m5.objects.RubyDirectedTester, InvalidateGenerator -> 
ALL_MSI/python/_m5/param_InvalidateGenerator.cc
 [SO Param] m5.objects.RubyDirectedTester, RubyDirectedTester -> 
ALL_MSI/python/_m5/param_RubyDirectedTester.cc
 [SO Param] m5.objects.RubyDirectedTester, SeriesRequestGenerator -> 
ALL_MSI/params/SeriesRequestGenerator.hh
 [SO Param] m5.objects.RubyDirectedTester, DirectedGenerator -> 
ALL_MSI/params/DirectedGenerator.hh
 [SO Param] m5.objects.RubyDirectedTester, RubyDirectedTester -> 
ALL_MSI/params/RubyDirectedTester.hh
 [SO Param] m5.objects.RubyDirectedTester, InvalidateGenerator -> 
ALL_MSI/params/InvalidateGenerator.hh
 [ TRACING]  -> ALL_MSI/debug/DirectedTest.hh
 [ TRACING]  -> ALL_MSI/debug/DirectedTest.cc
 [ CXX] ALL_MSI/cpu/testers/memtest/MemTest.py.cc -> .o
 [ CXX] ALL_MSI/debug/DirectedTest.cc -> .o
 [SO Param] m5.objects.MemTest, MemTest -> ALL_MSI/python/_m5/param_MemTest.cc
 [ TRACING]

[gem5-dev] [M] Change in gem5/gem5[develop]: base,cpu,dev: Add a level of indirection for ListenSockets.

2023-03-29 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69162?usp=email )


Change subject: base,cpu,dev: Add a level of indirection for ListenSockets.
..

base,cpu,dev: Add a level of indirection for ListenSockets.

This makes room for there to be different implementations for different
types of sockets.

Change-Id: I8c959e2c3400caec8242e693e11330e072bc2c5f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69162
Reviewed-by: Yu-hsin Wang 
Tested-by: kokoro 
Maintainer: Gabe Black 
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/base/socket.cc
M src/base/socket.hh
M src/base/vnc/vncserver.cc
M src/base/vnc/vncserver.hh
M src/cpu/nativetrace.cc
M src/cpu/nativetrace.hh
M src/dev/net/ethertap.cc
M src/dev/serial/terminal.cc
M src/dev/serial/terminal.hh
11 files changed, 76 insertions(+), 38 deletions(-)

Approvals:
  kokoro: Regressions pass
  Yu-hsin Wang: Looks good to me, approved
  Gabe Black: Looks good to me, approved




diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index c8cb32f..095b2bd 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -392,10 +392,11 @@

 BaseRemoteGDB::BaseRemoteGDB(System *_system, int _port) :
 incomingConnectionEvent(nullptr), incomingDataEvent(nullptr),
-listener(_system->name() + ".remote_gdb", _port), fd(-1),  
sys(_system),

-connectEvent(*this), disconnectEvent(*this), trapEvent(this),
-singleStepEvent(*this)
-{}
+fd(-1), sys(_system), connectEvent(*this), disconnectEvent(*this),
+trapEvent(this), singleStepEvent(*this)
+{
+listener = listenSocketInetConfig(_port).build(name());
+}

 BaseRemoteGDB::~BaseRemoteGDB()
 {
@@ -417,25 +418,22 @@
 return;
 }

-listener.listen();
+listener->listen();

 incomingConnectionEvent =
-new IncomingConnectionEvent(this, listener.getfd(), POLLIN);
+new IncomingConnectionEvent(this, listener->getfd(), POLLIN);
 pollQueue.schedule(incomingConnectionEvent);
-
-ccprintf(std::cerr, "%d: %s: listening for remote gdb on %s\n",
- curTick(), name(), listener);
 }

 void
 BaseRemoteGDB::connect()
 {
-panic_if(!listener.islistening(),
+panic_if(!listener->islistening(),
  "Can't accept GDB connections without any threads!");

 pollQueue.remove(incomingConnectionEvent);

-int sfd = listener.accept();
+int sfd = listener->accept();

 if (sfd != -1) {
 if (isAttached())
@@ -448,9 +446,9 @@
 const ListenSocket &
 BaseRemoteGDB::hostSocket() const
 {
-panic_if(!listener.islistening(),
+panic_if(!listener->islistening(),
  "Remote GDB socket is unknown until listen() has been  
called.");

-return listener;
+return *listener;
 }

 void
@@ -513,7 +511,7 @@
 assert(selectThreadContext(_tc->contextId()));

 // Now that we have a thread, we can start listening.
-if (!listener.islistening())
+if (!listener->islistening())
 listen();
 }

diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index 60a0d6a..9f09582 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -231,7 +231,7 @@
 IncomingConnectionEvent *incomingConnectionEvent;
 IncomingDataEvent *incomingDataEvent;

-ListenSocket listener;
+ListenSocketPtr listener;

 // The socket commands come in through.
 int fd;
diff --git a/src/base/socket.cc b/src/base/socket.cc
index 1aff73a..5fb8492 100644
--- a/src/base/socket.cc
+++ b/src/base/socket.cc
@@ -269,4 +269,12 @@
 return sfd;
 }

+ListenSocketConfig
+listenSocketInetConfig(int port)
+{
+return ListenSocketConfig([port](const std::string ) {
+return std::make_unique(name, port);
+});
+}
+
 } // namespace gem5
diff --git a/src/base/socket.hh b/src/base/socket.hh
index 81f4d62..638ce40 100644
--- a/src/base/socket.hh
+++ b/src/base/socket.hh
@@ -33,6 +33,9 @@
 #include 
 #include 

+#include 
+#include 
+#include 
 #include 

 #include "base/named.hh"
@@ -127,6 +130,33 @@
 /** @} */ // end of api_socket
 };

+using ListenSocketPtr = std::unique_ptr;
+
+class ListenSocketConfig
+{
+  public:
+using Builder = std::function)>;

+
+ListenSocketConfig() {}
+ListenSocketConfig(Builder _builder) : builder(_builder) {}
+
+ListenSocketPtr
+build(const std::string ) const
+{
+assert(builder);
+return builder(name);
+}
+
+operator bool() const { return (bool)builder; }
+
+  private:
+Builder builder;
+};
+
+static inline ListenSocketConfig listenSocketEmptyConfig() { return {}; }
+
+ListenSocketConfig listenSocketInetConfig(int port);
+
 inline static std::ostream &
 operator << (std::ostream , const ListenSocket )
 {
diff --git a/src/base/vnc/vncserver.cc b/src/base/vnc/vncserver.cc
index 2d32cef..4e5c951 100644
--- a/src/base/vnc/vncserver.cc
+++