[gem5-dev] [XS] Change in gem5/gem5[develop]: base: error out when socker path too long
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/69482?usp=email )
Change subject: base: error out when socker path too long
..
base: error out when socker path too long
When unix socket path is too long, we should simply error out the
execution instead of keeping running with an unexpected path and
warning.
Change-Id: I736727807ac41a23c5dac563dd8c904f3eec92b1
---
M src/base/socket.cc
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/src/base/socket.cc b/src/base/socket.cc
index 2e9f815..554513b 100644
--- a/src/base/socket.cc
+++ b/src/base/socket.cc
@@ -95,13 +95,8 @@
std::string resolved_path = resolve(path);
std::string fmt_path = replace(resolved_path, '\0', '@');
-if (resolved_path.size() > max_len) {
-resolved_path = resolved_path.substr(0, max_len);
-const std::string untruncated_path = std::move(fmt_path);
-fmt_path = replace(resolved_path, '\0', '@');
-warn("SocketPath: unix socket path truncated from '%s' to '%s'",
- untruncated_path, fmt_path);
-}
+panic_if(resolved_path.size() > max_len,
+ "SocketPath: unix socket path too long.");
// We can't use strncpy here, since abstract sockets start with \0
which
// will make strncpy think that the string is empty.
--
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Gerrit-Change-Id: I736727807ac41a23c5dac563dd8c904f3eec92b1
Gerrit-Change-Number: 69482
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: sim: handle async events in main thread only
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67533?usp=email )
Change subject: sim: handle async events in main thread only
..
sim: handle async events in main thread only
In the current implementation pollqueue is not thread safe. The design
of multi threads handle async events is thus causing issue in parallel
environment. Given the low rate of async events, it should be OK to only
handle them in the main thread to avoid unexpected racing issues.
Change-Id: Iddd512235e84e9d77f60985bb1771aa4cc693004
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67533
Reviewed-by: Gabe Black
Reviewed-by: Yu-hsin Wang
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/sim/simulate.cc
1 file changed, 23 insertions(+), 24 deletions(-)
Approvals:
Yu-hsin Wang: Looks good to me, but someone else must approve
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc
index 86d516d..abd2b1d 100644
--- a/src/sim/simulate.cc
+++ b/src/sim/simulate.cc
@@ -43,7 +43,6 @@
#include "sim/simulate.hh"
#include
-#include
#include
#include "base/logging.hh"
@@ -274,28 +273,6 @@
/**
- * Test and clear the global async_event flag, such that each time the
- * flag is cleared, only one thread returns true (and thus is assigned
- * to handle the corresponding async event(s)).
- */
-static bool
-testAndClearAsyncEvent()
-{
-static std::mutex mutex;
-
-bool was_set = false;
-mutex.lock();
-
-if (async_event) {
-was_set = true;
-async_event = false;
-}
-
-mutex.unlock();
-return was_set;
-}
-
-/**
* The main per-thread simulation loop. This loop is executed by all
* simulation threads (the main thread and the subordinate threads) in
* parallel.
@@ -307,6 +284,8 @@
curEventQueue(eventq);
eventq->handleAsyncInsertions();
+bool mainQueue = eventq == getEventQueue(0);
+
while (1) {
// there should always be at least one event (the SimLoopExitEvent
// we just scheduled) in the queue
@@ -314,7 +293,8 @@
assert(curTick() <= eventq->nextTick() &&
"event scheduled in the past");
-if (async_event && testAndClearAsyncEvent()) {
+if (mainQueue && async_event) {
+async_event = false;
// Take the event queue lock in case any of the service
// routines want to schedule new events.
std::lock_guard lock(*eventq);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iddd512235e84e9d77f60985bb1771aa4cc693004
Gerrit-Change-Number: 67533
Gerrit-PatchSet: 7
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem: use default backdoor behavior for thread_bridge
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67531?usp=email )
Change subject: mem: use default backdoor behavior for thread_bridge
..
mem: use default backdoor behavior for thread_bridge
The original backdoor implementation is incorrect. We use simply
fallback to default (disable backdoor) as backdoor across threads is not
thread-safe in most of cases.
Change-Id: Ia39be0dda4f16917cc3565eb5b012270e6d7697a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67531
Maintainer: Gabe Black
Tested-by: kokoro
Reviewed-by: Yu-hsin Wang
---
M src/mem/thread_bridge.cc
M src/mem/thread_bridge.hh
2 files changed, 17 insertions(+), 18 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
Yu-hsin Wang: Looks good to me, approved
diff --git a/src/mem/thread_bridge.cc b/src/mem/thread_bridge.cc
index 0090e42..5af2a59 100644
--- a/src/mem/thread_bridge.cc
+++ b/src/mem/thread_bridge.cc
@@ -64,12 +64,6 @@
// AtomicResponseProtocol
Tick
-ThreadBridge::IncomingPort::recvAtomicBackdoor(PacketPtr pkt,
- MemBackdoorPtr )
-{
-panic("ThreadBridge only supports atomic/functional access.");
-}
-Tick
ThreadBridge::IncomingPort::recvAtomic(PacketPtr pkt)
{
EventQueue::ScopedMigration migrate(device_.eventQueue());
@@ -84,14 +78,6 @@
device_.out_port_.sendFunctional(pkt);
}
-void
-ThreadBridge::IncomingPort::recvMemBackdoorReq(const MemBackdoorReq ,
- MemBackdoorPtr )
-{
-EventQueue::ScopedMigration migrate(device_.eventQueue());
-device_.out_port_.sendMemBackdoorReq(req, backdoor);
-}
-
ThreadBridge::OutgoingPort::OutgoingPort(const std::string ,
ThreadBridge )
: RequestPort(name), device_(device)
diff --git a/src/mem/thread_bridge.hh b/src/mem/thread_bridge.hh
index 92cb078..8a253fd 100644
--- a/src/mem/thread_bridge.hh
+++ b/src/mem/thread_bridge.hh
@@ -55,14 +55,10 @@
void recvRespRetry() override;
// AtomicResponseProtocol
-Tick recvAtomicBackdoor(PacketPtr pkt,
-MemBackdoorPtr ) override;
Tick recvAtomic(PacketPtr pkt) override;
// FunctionalResponseProtocol
void recvFunctional(PacketPtr pkt) override;
-void recvMemBackdoorReq(const MemBackdoorReq ,
-MemBackdoorPtr ) override;
private:
ThreadBridge _;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia39be0dda4f16917cc3565eb5b012270e6d7697a
Gerrit-Change-Number: 67531
Gerrit-PatchSet: 5
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: dev: terminal: run pollevent in terminal eventq
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67532?usp=email )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: dev: terminal: run pollevent in terminal eventq
..
dev: terminal: run pollevent in terminal eventq
Change-Id: Idefda0ca1cd71d3e790d470458fa1cd370393c4a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67532
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/dev/serial/terminal.cc
1 file changed, 17 insertions(+), 0 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/serial/terminal.cc b/src/dev/serial/terminal.cc
index 52dbb9e..d4108a3 100644
--- a/src/dev/serial/terminal.cc
+++ b/src/dev/serial/terminal.cc
@@ -87,6 +87,10 @@
void
Terminal::ListenEvent::process(int revent)
{
+// As a consequence of being called from the PollQueue, we might
+// have been called from a different thread. Migrate to "our"
+// thread.
+EventQueue::ScopedMigration migrate(term->eventQueue());
term->accept();
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Idefda0ca1cd71d3e790d470458fa1cd370393c4a
Gerrit-Change-Number: 67532
Gerrit-PatchSet: 6
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem: implement atomic backdoor in thread_bridge
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67531?usp=email )
Change subject: mem: implement atomic backdoor in thread_bridge
..
mem: implement atomic backdoor in thread_bridge
Change-Id: Ia39be0dda4f16917cc3565eb5b012270e6d7697a
---
M src/mem/thread_bridge.cc
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/mem/thread_bridge.cc b/src/mem/thread_bridge.cc
index efaf19a..5b591f3 100644
--- a/src/mem/thread_bridge.cc
+++ b/src/mem/thread_bridge.cc
@@ -67,7 +67,8 @@
ThreadBridge::IncomingPort::recvAtomicBackdoor(PacketPtr pkt,
MemBackdoorPtr )
{
-panic("ThreadBridge only supports atomic/functional access.");
+EventQueue::ScopedMigration migrate(device_.eventQueue());
+return device_.out_port_.sendAtomic(pkt);
}
Tick
ThreadBridge::IncomingPort::recvAtomic(PacketPtr pkt)
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ia39be0dda4f16917cc3565eb5b012270e6d7697a
Gerrit-Change-Number: 67531
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: sim: handle async events in main thread only
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67533?usp=email )
Change subject: sim: handle async events in main thread only
..
sim: handle async events in main thread only
Change-Id: Iddd512235e84e9d77f60985bb1771aa4cc693004
---
M src/sim/simulate.cc
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc
index 86d516d..78ba33a 100644
--- a/src/sim/simulate.cc
+++ b/src/sim/simulate.cc
@@ -307,6 +307,8 @@
curEventQueue(eventq);
eventq->handleAsyncInsertions();
+bool mainQueue = eventq == getEventQueue(0);
+
while (1) {
// there should always be at least one event (the SimLoopExitEvent
// we just scheduled) in the queue
@@ -314,7 +316,7 @@
assert(curTick() <= eventq->nextTick() &&
"event scheduled in the past");
-if (async_event && testAndClearAsyncEvent()) {
+if (mainQueue && async_event && testAndClearAsyncEvent()) {
// Take the event queue lock in case any of the service
// routines want to schedule new events.
std::lock_guard lock(*eventq);
--
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Gerrit-Change-Id: Iddd512235e84e9d77f60985bb1771aa4cc693004
Gerrit-Change-Number: 67533
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: dev: terminal: run pollevent in terminal eventq
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67532?usp=email )
Change subject: dev: terminal: run pollevent in terminal eventq
..
dev: terminal: run pollevent in terminal eventq
Change-Id: Idefda0ca1cd71d3e790d470458fa1cd370393c4a
---
M src/dev/serial/terminal.cc
1 file changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/dev/serial/terminal.cc b/src/dev/serial/terminal.cc
index 52dbb9e..d4108a3 100644
--- a/src/dev/serial/terminal.cc
+++ b/src/dev/serial/terminal.cc
@@ -87,6 +87,10 @@
void
Terminal::ListenEvent::process(int revent)
{
+// As a consequence of being called from the PollQueue, we might
+// have been called from a different thread. Migrate to "our"
+// thread.
+EventQueue::ScopedMigration migrate(term->eventQueue());
term->accept();
}
--
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Gerrit-Change-Id: Idefda0ca1cd71d3e790d470458fa1cd370393c4a
Gerrit-Change-Number: 67532
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] [L] Change in gem5/gem5[develop]: mem: create port_wrapper classes
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67232?usp=email )
Change subject: mem: create port_wrapper classes
..
mem: create port_wrapper classes
The port_wrapper classes convert the Request/ResponsePort from
inherit-base to callback registrations. This help 'composition over
inheritance' that most design pattern follows, which help reducing
code length and increase reusability.
Change-Id: Ia13cc62507ac8425bd7cf143a2e080d041c173f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67232
Maintainer: Jason Lowe-Power
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/SConscript
A src/mem/port_wrapper.cc
A src/mem/port_wrapper.hh
3 files changed, 347 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 3bcfc0d..ca164c1 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -88,6 +88,7 @@
Source('port.cc')
Source('packet_queue.cc')
Source('port_proxy.cc')
+Source('port_wrapper.cc')
Source('physical.cc')
Source('shared_memory_server.cc')
Source('simple_mem.cc')
diff --git a/src/mem/port_wrapper.cc b/src/mem/port_wrapper.cc
new file mode 100644
index 000..fd5ebbd
--- /dev/null
+++ b/src/mem/port_wrapper.cc
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2023 Google, LLC.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/port_wrapper.hh"
+
+namespace gem5
+{
+
+RequestPortWrapper::RequestPortWrapper(const std::string& name,
+ SimObject* _owner, PortID id)
+: RequestPort(name, _owner, id)
+{
+}
+
+void
+RequestPortWrapper::recvRangeChange()
+{
+if (!recvRangeChangeCb) {
+RequestPort::recvRangeChange();
+return;
+}
+recvRangeChangeCb();
+}
+
+bool
+RequestPortWrapper::recvTimingResp(PacketPtr packet)
+{
+panic_if(!recvTimingRespCb, "RecvTimingRespCallback is empty.");
+return recvTimingRespCb(packet);
+}
+
+void
+RequestPortWrapper::recvReqRetry()
+{
+panic_if(!recvReqRetryCb, "RecvReqRetryCallback is empty.");
+recvReqRetryCb();
+}
+
+void
+RequestPortWrapper::setRangeChangeCallback(RecvReqRetryCallback cb)
+{
+recvRangeChangeCb = std::move(cb);
+}
+
+void
+RequestPortWrapper::setTimingCallbacks(RecvTimingRespCallback resp_cb,
+ RecvReqRetryCallback retry_cb)
+{
+recvTimingRespCb = std::move(resp_cb);
+recvReqRetryCb = std::move(retry_cb);
+}
+
+ResponsePortWrapper::ResponsePortWrapper(const std::string& name,
+ SimObject* _owner, PortID id)
+: ResponsePort(name, _owner, id)
+{
+}
+
+AddrRangeList
+ResponsePortWrapper::getAddrRanges() const
+{
+panic_if(!getAddrRangesCb, "GetAddrRangesCallback is empty.");
+return getAddrRangesCb();
+}
+
+bool
+ResponsePortWrapper::recvTimingReq(PacketPtr packet)
+{
+panic_if(!recvTimingReqCb, "RecvTimingReqCallback is empty.");
+return recvTimingReqCb(packet);
+}
+
+void
+ResponsePortWrapper::recvRespRetry()
+{
+panic_if(!recvRespRetryCb, "RecvRespRetryCallback is empty.");
+recvRespRetryCb();
+}
+
+Tick
+ResponsePortWrapper::recvAtomic(PacketPtr packet)
+{
+panic_if(!recvAtomicCb, "RecvAtomicCallback is empty.");
+return recvAtomicCb(packet);
+}
+
+Tick
+ResponsePortWrapper::recvAtomicBackdoor(PacketPtr packet,
+
[gem5-dev] [M] Change in gem5/gem5[develop]: systemc: fix -Wno-free-nonheap-object for building scheduler.cc
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67237?usp=email )
Change subject: systemc: fix -Wno-free-nonheap-object for building
scheduler.cc
..
systemc: fix -Wno-free-nonheap-object for building scheduler.cc
-Wno-free-nonheap-object can happen at compile or link time depending on
the versions. To better disable this false alarm, we move the memory
management part into .cc file, so the check is always done at link time.
This change also removes the global flags so other code is still checked
with the flags.
Change-Id: I8f1e20197b25c90b5f439e2ecc474bd99e4f82ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67237
Tested-by: kokoro
Reviewed-by: Yu-hsin Wang
Maintainer: Gabe Black
---
M SConstruct
M src/sim/eventq.cc
M src/sim/eventq.hh
M src/systemc/core/SConscript
4 files changed, 52 insertions(+), 22 deletions(-)
Approvals:
Yu-hsin Wang: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index bd26e45..e08c2984 100755
--- a/SConstruct
+++ b/SConstruct
@@ -447,10 +447,6 @@
error('gcc version 7 or newer required.\n'
'Installed version:', env['CXXVERSION'])
-with gem5_scons.Configure(env) as conf:
-# This warning has a false positive in the systemc in g++ 11.1.
-conf.CheckCxxFlag('-Wno-free-nonheap-object')
-
# Add the appropriate Link-Time Optimization (LTO) flags if
# `--with-lto` is set.
if GetOption('with_lto'):
diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc
index 66d0385..23ca2f6 100644
--- a/src/sim/eventq.cc
+++ b/src/sim/eventq.cc
@@ -109,6 +109,32 @@
}
void
+Event::acquire()
+{
+if (flags.isSet(Event::Managed))
+acquireImpl();
+}
+
+void
+Event::release()
+{
+if (flags.isSet(Event::Managed))
+releaseImpl();
+}
+
+void
+Event::acquireImpl()
+{
+}
+
+void
+Event::releaseImpl()
+{
+if (!scheduled())
+delete this;
+}
+
+void
EventQueue::insert(Event *event)
{
// Deal with the head case
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index cd5d285f..62495bf 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -381,26 +381,16 @@
/**
* Managed event scheduled and being held in the event queue.
*/
-void acquire()
-{
-if (flags.isSet(Event::Managed))
-acquireImpl();
-}
+void acquire();
/**
* Managed event removed from the event queue.
*/
-void release() {
-if (flags.isSet(Event::Managed))
-releaseImpl();
-}
+void release();
-virtual void acquireImpl() {}
+virtual void acquireImpl();
-virtual void releaseImpl() {
-if (!scheduled())
-delete this;
-}
+virtual void releaseImpl();
/** @} */
diff --git a/src/systemc/core/SConscript b/src/systemc/core/SConscript
index 2b88111..c7c9dbb 100644
--- a/src/systemc/core/SConscript
+++ b/src/systemc/core/SConscript
@@ -40,6 +40,7 @@
Source('port.cc')
Source('process.cc')
Source('sched_event.cc')
+Source('scheduler.cc')
Source('sensitivity.cc')
Source('time.cc')
@@ -75,7 +76,4 @@
# Disable the false positive warning for the event members of the
scheduler.
with gem5_scons.Configure(env) as conf:
flag = '-Wno-free-nonheap-object'
-append = {}
-if conf.CheckCxxFlag(flag, autoadd=False):
-append['CCFLAGS'] = [flag]
-Source('scheduler.cc', append=append)
+conf.CheckLinkFlag(flag)
--
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https://gem5-review.googlesource.com/c/public/gem5/+/67237?usp=email
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8f1e20197b25c90b5f439e2ecc474bd99e4f82ed
Gerrit-Change-Number: 67237
Gerrit-PatchSet: 3
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-CC: Gabe Black
Gerrit-CC: Nicolas Boichat
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: fix -Wno-free-nonheap-object for building scheduler.cc
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67237?usp=email )
Change subject: systemc: fix -Wno-free-nonheap-object for building
scheduler.cc
..
systemc: fix -Wno-free-nonheap-object for building scheduler.cc
-Wno-free-nonheap-object need to be added into linker flag as
the this check is actually at link time. This change also removes
the global flags so other code is still checked with the flags.
Change-Id: I8f1e20197b25c90b5f439e2ecc474bd99e4f82ed
---
M SConstruct
M src/systemc/core/SConscript
2 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/SConstruct b/SConstruct
index bd26e45..e08c2984 100755
--- a/SConstruct
+++ b/SConstruct
@@ -447,10 +447,6 @@
error('gcc version 7 or newer required.\n'
'Installed version:', env['CXXVERSION'])
-with gem5_scons.Configure(env) as conf:
-# This warning has a false positive in the systemc in g++ 11.1.
-conf.CheckCxxFlag('-Wno-free-nonheap-object')
-
# Add the appropriate Link-Time Optimization (LTO) flags if
# `--with-lto` is set.
if GetOption('with_lto'):
diff --git a/src/systemc/core/SConscript b/src/systemc/core/SConscript
index 2b88111..c7c9dbb 100644
--- a/src/systemc/core/SConscript
+++ b/src/systemc/core/SConscript
@@ -40,6 +40,7 @@
Source('port.cc')
Source('process.cc')
Source('sched_event.cc')
+Source('scheduler.cc')
Source('sensitivity.cc')
Source('time.cc')
@@ -75,7 +76,4 @@
# Disable the false positive warning for the event members of the
scheduler.
with gem5_scons.Configure(env) as conf:
flag = '-Wno-free-nonheap-object'
-append = {}
-if conf.CheckCxxFlag(flag, autoadd=False):
-append['CCFLAGS'] = [flag]
-Source('scheduler.cc', append=append)
+conf.CheckLinkFlag(flag)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8f1e20197b25c90b5f439e2ecc474bd99e4f82ed
Gerrit-Change-Number: 67237
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: systemc: fix warning of auto event deletion
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67236?usp=email )
Change subject: systemc: fix warning of auto event deletion
..
systemc: fix warning of auto event deletion
We see the following warning in systemc Scheduler:
eventq.hh: warning: operator delete called on unallocated object
scheduler [-Wfree-nonheap-object]
This is because Event has auto deletion feature and is wrapped
into EventWrapper. The additional Flag layer in EventWrapper
makes it difficult for compiler to tell if the Event can delete
itself or not. And Scheduler put Event in stack instead of heap.
This CL moves them from stack to heap to avoid the warning. The
proper longer term fix is probably by removing the auto delete
feature, and use smart pointer to explicitly transfer ownership
to the event queue.
Change-Id: Iadff0240b5d108a448799ee55f9e6c24992d7af2
---
M src/systemc/core/scheduler.cc
M src/systemc/core/scheduler.hh
2 files changed, 103 insertions(+), 52 deletions(-)
diff --git a/src/systemc/core/scheduler.cc b/src/systemc/core/scheduler.cc
index 42a2ca4..240ff6a 100644
--- a/src/systemc/core/scheduler.cc
+++ b/src/systemc/core/scheduler.cc
@@ -43,17 +43,38 @@
namespace sc_gem5
{
-Scheduler::Scheduler() :
-eq(nullptr), readyEvent(this, false, ReadyPriority),
-pauseEvent(this, false, PausePriority),
-stopEvent(this, false, StopPriority), _throwUp(nullptr),
-starvationEvent(this, false, StarvationPriority),
-_elaborationDone(false), _started(false), _stopNow(false),
-_status(StatusOther), maxTick(gem5::MaxTick),
-maxTickEvent(this, false, MaxTickPriority),
-timeAdvancesEvent(this, false, TimeAdvancesPriority), _numCycles(0),
-_changeStamp(0), _current(nullptr), initDone(false), runToTime(true),
-runOnce(false)
+Scheduler::Scheduler()
+: eq(nullptr),
+ readyEvent(std::make_unique<
+ gem5::EventWrapper>(
+ this, false, ReadyPriority)),
+ pauseEvent(std::make_unique<
+ gem5::EventWrapper>(
+ this, false, PausePriority)),
+ stopEvent(std::make_unique<
+ gem5::EventWrapper>(
+ this, false, StopPriority)),
+ _throwUp(nullptr),
+ starvationEvent(std::make_unique<
+ gem5::EventWrapper>(
+ this, false, StarvationPriority)),
+ _elaborationDone(false),
+ _started(false),
+ _stopNow(false),
+ _status(StatusOther),
+ maxTick(gem5::MaxTick),
+ maxTickEvent(std::make_unique<
+ gem5::EventWrapper>(
+ this, false, MaxTickPriority)),
+ timeAdvancesEvent(std::make_unique<
+ gem5::EventWrapper>(
+ this, false, TimeAdvancesPriority)),
+ _numCycles(0),
+ _changeStamp(0),
+ _current(nullptr),
+ initDone(false),
+ runToTime(true),
+ runOnce(false)
{}
Scheduler::~Scheduler()
@@ -79,18 +100,18 @@
timeSlots.clear();
// gem5 events.
-if (readyEvent.scheduled())
-deschedule();
-if (pauseEvent.scheduled())
-deschedule();
-if (stopEvent.scheduled())
-deschedule();
-if (starvationEvent.scheduled())
-deschedule();
-if (maxTickEvent.scheduled())
-deschedule();
-if (timeAdvancesEvent.scheduled())
-deschedule();
+if (readyEvent->scheduled())
+deschedule(readyEvent.get());
+if (pauseEvent->scheduled())
+deschedule(pauseEvent.get());
+if (stopEvent->scheduled())
+deschedule(stopEvent.get());
+if (starvationEvent->scheduled())
+deschedule(starvationEvent.get());
+if (maxTickEvent->scheduled())
+deschedule(maxTickEvent.get());
+if (timeAdvancesEvent->scheduled())
+deschedule(timeAdvancesEvent.get());
Process *p;
while ((p = initList.getNext()))
@@ -266,20 +287,20 @@
Scheduler::scheduleReadyEvent()
{
// Schedule the evaluate and update phases.
-if (!readyEvent.scheduled()) {
-schedule();
-if (starvationEvent.scheduled())
-deschedule();
+if (!readyEvent->scheduled()) {
+schedule(readyEvent.get());
+if (starvationEvent->scheduled())
+deschedule(starvationEvent.get());
}
}
void
Scheduler::scheduleStarvationEvent()
{
-if (!starvationEvent.scheduled()) {
-schedule();
-if (readyEvent.scheduled())
-deschedule();
+if (!starvationEvent->scheduled()) {
+schedule(starvationEvent.get());
+if (readyEvent->scheduled())
+deschedule(readyEvent.get());
}
}
@@ -416,20 +437,20 @@
kernel->status(::sc_core::SC_RUNNING);
}
-schedule(, maxTick);
+schedule(maxTickEvent.get(), maxTick);
scheduleTimeAdvancesEvent();
// Return to gem5 to let it run events, etc.
gem5::Fiber::primaryFiber()->run();
-if
[gem5-dev] [L] Change in gem5/gem5[develop]: mem: create simple_port classes
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67232?usp=email )
Change subject: mem: create simple_port classes
..
mem: create simple_port classes
The simple_port classes convert the Request/ResponsePort from
inherit-base to callback registrations. This help 'composition over
inheritance' that most design pattern follows, which help reducing
code length and increase reusability.
Change-Id: Ia13cc62507ac8425bd7cf143a2e080d041c173f9
---
M src/mem/SConscript
A src/mem/simple_port.cc
A src/mem/simple_port.hh
3 files changed, 302 insertions(+), 0 deletions(-)
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 3bcfc0d..c692e45 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -91,6 +91,7 @@
Source('physical.cc')
Source('shared_memory_server.cc')
Source('simple_mem.cc')
+Source('simple_port.cc')
Source('snoop_filter.cc')
Source('stack_dist_calc.cc')
Source('sys_bridge.cc')
diff --git a/src/mem/simple_port.cc b/src/mem/simple_port.cc
new file mode 100644
index 000..229b2a1
--- /dev/null
+++ b/src/mem/simple_port.cc
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2023 Google, LLC.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/simple_port.hh"
+
+namespace gem5
+{
+
+SimpleRequestPort::SimpleRequestPort(const std::string& name,
+ SimObject* _owner, PortID id)
+: RequestPort(name, _owner, id)
+{
+}
+
+void
+SimpleRequestPort::recvRangeChange()
+{
+if (!recvRangeChangeCb) {
+RequestPort::recvRangeChange();
+return;
+}
+recvRangeChangeCb();
+}
+
+bool
+SimpleRequestPort::recvTimingResp(PacketPtr packet)
+{
+panic_if(!recvTimingRespCb, "RecvTimingRespCallback is empty.");
+return recvTimingRespCb(packet);
+}
+
+void
+SimpleRequestPort::recvReqRetry()
+{
+panic_if(!recvReqRetryCb, "RecvReqRetryCallback is empty.");
+recvReqRetryCb();
+}
+
+void
+SimpleRequestPort::setRangeChangeCallback(RecvReqRetryCallback cb)
+{
+recvRangeChangeCb = std::move(cb);
+}
+
+void
+SimpleRequestPort::setTimingCallbacks(RecvTimingRespCallback resp_cb,
+ RecvReqRetryCallback retry_cb)
+{
+recvTimingRespCb = std::move(resp_cb);
+recvReqRetryCb = std::move(retry_cb);
+}
+
+SimpleResponsePort::SimpleResponsePort(const std::string& name,
+ SimObject* _owner, PortID id)
+: ResponsePort(name, _owner, id)
+{
+}
+
+AddrRangeList
+SimpleResponsePort::getAddrRanges() const
+{
+panic_if(!getAddrRangesCb, "GetAddrRangesCallback is empty.");
+return getAddrRangesCb();
+}
+
+bool
+SimpleResponsePort::recvTimingReq(PacketPtr packet)
+{
+panic_if(!recvTimingReqCb, "RecvTimingReqCallback is empty.");
+return recvTimingReqCb(packet);
+}
+
+void
+SimpleResponsePort::recvRespRetry()
+{
+panic_if(!recvRespRetryCb, "RecvRespRetryCallback is empty.");
+recvRespRetryCb();
+}
+
+Tick
+SimpleResponsePort::recvAtomic(PacketPtr packet)
+{
+panic_if(!recvAtomicCb, "RecvAtomicCallback is empty.");
+return recvAtomicCb(packet);
+}
+
+Tick
+SimpleResponsePort::recvAtomicBackdoor(PacketPtr packet,
+ MemBackdoorPtr& backdoor)
+{
+if (!recvAtomicBackdoorCb) {
+return ResponsePort::recvAtomicBackdoor(packet, backdoor);
+}
+return recvAtomicBackdoorCb(packet, backdoor);
+}
+
+void
[gem5-dev] [M] Change in gem5/gem5[develop]: sim: allow specifying remote gdb port for each workload
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/65151?usp=email )
Change subject: sim: allow specifying remote gdb port for each workload
..
sim: allow specifying remote gdb port for each workload
In a platform with multiple systems, we may want to specify the
remote gdb port for each system. This change makes it
possible to specify the port number at each Workload instance.
Change-Id: I755b3960ee920ae5289819aa05d98902614a5615
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65151
Maintainer: Earl Ou
Reviewed-by: Yu-hsin Wang
Tested-by: kokoro
---
M src/arch/arm/fs_workload.hh
M src/arch/arm/se_workload.hh
M src/arch/mips/se_workload.hh
M src/arch/power/se_workload.hh
M src/arch/riscv/bare_metal/fs_workload.hh
M src/arch/riscv/linux/fs_workload.hh
M src/arch/riscv/se_workload.hh
M src/arch/sparc/fs_workload.hh
M src/arch/sparc/se_workload.hh
M src/arch/x86/fs_workload.hh
M src/arch/x86/linux/se_workload.hh
M src/base/remote_gdb.hh
M src/python/m5/debug.py
M src/python/m5/main.py
M src/python/pybind11/debug.cc
M src/sim/Workload.py
M src/sim/debug.cc
M src/sim/debug.hh
M util/systemc/gem5_within_systemc/sc_gem5_control.cc
M util/systemc/gem5_within_systemc/sc_gem5_control.hh
20 files changed, 53 insertions(+), 53 deletions(-)
Approvals:
kokoro: Regressions pass
Yu-hsin Wang: Looks good to me, approved
Earl Ou: Looks good to me, approved
diff --git a/src/arch/arm/fs_workload.hh b/src/arch/arm/fs_workload.hh
index 547bbf1..0811f3d 100644
--- a/src/arch/arm/fs_workload.hh
+++ b/src/arch/arm/fs_workload.hh
@@ -153,7 +153,8 @@
setSystem(System *sys) override
{
KernelWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
}
Addr
diff --git a/src/arch/arm/se_workload.hh b/src/arch/arm/se_workload.hh
index deb5d3b..f0bf0eb 100644
--- a/src/arch/arm/se_workload.hh
+++ b/src/arch/arm/se_workload.hh
@@ -42,7 +42,7 @@
class SEWorkload : public gem5::SEWorkload
{
public:
-using Params = ArmSEWorkloadParams;
+PARAMS(ArmSEWorkload);
SEWorkload(const Params , Addr page_shift) :
gem5::SEWorkload(p, page_shift)
@@ -52,7 +52,8 @@
setSystem(System *sys) override
{
gem5::SEWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
}
loader::Arch getArch() const override { return loader::Arm64; }
diff --git a/src/arch/mips/se_workload.hh b/src/arch/mips/se_workload.hh
index d5184dd..dc6f1dd 100644
--- a/src/arch/mips/se_workload.hh
+++ b/src/arch/mips/se_workload.hh
@@ -44,7 +44,7 @@
class SEWorkload : public gem5::SEWorkload
{
public:
-using Params = MipsSEWorkloadParams;
+PARAMS(MipsSEWorkload);
SEWorkload(const Params , Addr page_shift) :
gem5::SEWorkload(p, page_shift)
@@ -54,7 +54,8 @@
setSystem(System *sys) override
{
gem5::SEWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
}
loader::Arch getArch() const override { return loader::Mips; }
diff --git a/src/arch/power/se_workload.hh b/src/arch/power/se_workload.hh
index f3c7b35..d041c45 100644
--- a/src/arch/power/se_workload.hh
+++ b/src/arch/power/se_workload.hh
@@ -45,7 +45,7 @@
class SEWorkload : public gem5::SEWorkload
{
public:
-using Params = PowerSEWorkloadParams;
+PARAMS(PowerSEWorkload);
SEWorkload(const Params , Addr page_shift) :
gem5::SEWorkload(p, page_shift)
{}
@@ -54,7 +54,8 @@
setSystem(System *sys) override
{
gem5::SEWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
}
loader::Arch getArch() const override { return loader::Power; }
diff --git a/src/arch/riscv/bare_metal/fs_workload.hh
b/src/arch/riscv/bare_metal/fs_workload.hh
index e10c0a0..35f4255 100644
--- a/src/arch/riscv/bare_metal/fs_workload.hh
+++ b/src/arch/riscv/bare_metal/fs_workload.hh
@@ -60,7 +60,8 @@
setSystem(System *sys) override
{
Workload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
}
loader::Arch getArch() const override { return bootloader->getArch(); }
diff --git a/src/arch/riscv/linux/fs_workload.hh
b/src/arch/riscv/linux/fs_workload.hh
index cb29bee..1dc704d 100644
--- a/src/arch/riscv/linux/fs_workload.hh
+++ b/src/arch/riscv/linux/fs_workload.hh
@@ -51,7 +51,8 @@
setSystem(System *sys) override
{
KernelWorkload::setSystem(sys);
-gdb =
[gem5-dev] [S] Change in gem5/gem5[develop]: util: update termios to replace nl with cr-nl
Earl Ou has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/65152?usp=email ) Change subject: util: update termios to replace nl with cr-nl .. util: update termios to replace nl with cr-nl This change enables OPOST to enable output post-processing. It then enables ONLCR to prepend newline characters with carriage return so that start of each line is always left aligned. Note that on some terminals this might display a redundant ^M. Change-Id: Ia0b4c61725ab7478e7341273a8279b96e53d9f26 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65152 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M util/term/term.c 1 file changed, 20 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/util/term/term.c b/util/term/term.c index ca88ad4..529712c 100644 --- a/util/term/term.c +++ b/util/term/term.c @@ -302,8 +302,8 @@ memcpy(_ios, , sizeof(struct termios)); ios.c_iflag &= ~(ISTRIP|ICRNL|IGNCR|ICRNL|IXOFF|IXON); -ios.c_oflag &= ~(OPOST); -ios.c_oflag &= (ONLCR); +ios.c_oflag |= OPOST; +ios.c_oflag |= ONLCR; ios.c_lflag &= ~(ISIG|ICANON|ECHO); ios.c_cc[VMIN] = 1; ios.c_cc[VTIME] = 0; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/65152?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia0b4c61725ab7478e7341273a8279b96e53d9f26 Gerrit-Change-Number: 65152 Gerrit-PatchSet: 2 Gerrit-Owner: Earl Ou Gerrit-Reviewer: Earl Ou Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nicolas Boichat Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: util: update termios to replace nl with cr-nl
Earl Ou has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65152?usp=email ) Change subject: util: update termios to replace nl with cr-nl .. util: update termios to replace nl with cr-nl This change enables OPOST to enable output post-processing. It then enables ONLCR to prepend newline characters with carriage return so that start of each line is always left aligned. Note that on some terminals this might display a redundant ^M. Change-Id: Ia0b4c61725ab7478e7341273a8279b96e53d9f26 --- M util/term/term.c 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/util/term/term.c b/util/term/term.c index ca88ad4..529712c 100644 --- a/util/term/term.c +++ b/util/term/term.c @@ -302,8 +302,8 @@ memcpy(_ios, , sizeof(struct termios)); ios.c_iflag &= ~(ISTRIP|ICRNL|IGNCR|ICRNL|IXOFF|IXON); -ios.c_oflag &= ~(OPOST); -ios.c_oflag &= (ONLCR); +ios.c_oflag |= OPOST; +ios.c_oflag |= ONLCR; ios.c_lflag &= ~(ISIG|ICANON|ECHO); ios.c_cc[VMIN] = 1; ios.c_cc[VTIME] = 0; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/65152?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia0b4c61725ab7478e7341273a8279b96e53d9f26 Gerrit-Change-Number: 65152 Gerrit-PatchSet: 1 Gerrit-Owner: Earl Ou Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: sim: allow specifying remote gdb port for each workload
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/65151?usp=email )
Change subject: sim: allow specifying remote gdb port for each workload
..
sim: allow specifying remote gdb port for each workload
In a platform with multiple systems, we may want to specify the
remote gdb port for each system. This change makes it
possible to specify the port number at each Workload instance.
Change-Id: I755b3960ee920ae5289819aa05d98902614a5615
---
M src/arch/arm/fs_workload.hh
M src/arch/arm/se_workload.hh
M src/arch/mips/se_workload.hh
M src/arch/power/se_workload.hh
M src/arch/riscv/bare_metal/fs_workload.hh
M src/arch/riscv/linux/fs_workload.hh
M src/arch/riscv/se_workload.hh
M src/arch/sparc/fs_workload.hh
M src/arch/sparc/se_workload.hh
M src/arch/x86/fs_workload.hh
M src/arch/x86/linux/se_workload.hh
M src/base/remote_gdb.hh
M src/python/m5/debug.py
M src/python/m5/main.py
M src/python/pybind11/debug.cc
M src/sim/Workload.py
M src/sim/debug.cc
M src/sim/debug.hh
M util/systemc/gem5_within_systemc/sc_gem5_control.cc
M util/systemc/gem5_within_systemc/sc_gem5_control.hh
20 files changed, 48 insertions(+), 53 deletions(-)
diff --git a/src/arch/arm/fs_workload.hh b/src/arch/arm/fs_workload.hh
index 547bbf1..0811f3d 100644
--- a/src/arch/arm/fs_workload.hh
+++ b/src/arch/arm/fs_workload.hh
@@ -153,7 +153,8 @@
setSystem(System *sys) override
{
KernelWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
}
Addr
diff --git a/src/arch/arm/se_workload.hh b/src/arch/arm/se_workload.hh
index deb5d3b..f0bf0eb 100644
--- a/src/arch/arm/se_workload.hh
+++ b/src/arch/arm/se_workload.hh
@@ -42,7 +42,7 @@
class SEWorkload : public gem5::SEWorkload
{
public:
-using Params = ArmSEWorkloadParams;
+PARAMS(ArmSEWorkload);
SEWorkload(const Params , Addr page_shift) :
gem5::SEWorkload(p, page_shift)
@@ -52,7 +52,8 @@
setSystem(System *sys) override
{
gem5::SEWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
}
loader::Arch getArch() const override { return loader::Arm64; }
diff --git a/src/arch/mips/se_workload.hh b/src/arch/mips/se_workload.hh
index d5184dd..dc6f1dd 100644
--- a/src/arch/mips/se_workload.hh
+++ b/src/arch/mips/se_workload.hh
@@ -44,7 +44,7 @@
class SEWorkload : public gem5::SEWorkload
{
public:
-using Params = MipsSEWorkloadParams;
+PARAMS(MipsSEWorkload);
SEWorkload(const Params , Addr page_shift) :
gem5::SEWorkload(p, page_shift)
@@ -54,7 +54,8 @@
setSystem(System *sys) override
{
gem5::SEWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
}
loader::Arch getArch() const override { return loader::Mips; }
diff --git a/src/arch/power/se_workload.hh b/src/arch/power/se_workload.hh
index f3c7b35..d041c45 100644
--- a/src/arch/power/se_workload.hh
+++ b/src/arch/power/se_workload.hh
@@ -45,7 +45,7 @@
class SEWorkload : public gem5::SEWorkload
{
public:
-using Params = PowerSEWorkloadParams;
+PARAMS(PowerSEWorkload);
SEWorkload(const Params , Addr page_shift) :
gem5::SEWorkload(p, page_shift)
{}
@@ -54,7 +54,8 @@
setSystem(System *sys) override
{
gem5::SEWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
}
loader::Arch getArch() const override { return loader::Power; }
diff --git a/src/arch/riscv/bare_metal/fs_workload.hh
b/src/arch/riscv/bare_metal/fs_workload.hh
index e10c0a0..35f4255 100644
--- a/src/arch/riscv/bare_metal/fs_workload.hh
+++ b/src/arch/riscv/bare_metal/fs_workload.hh
@@ -60,7 +60,8 @@
setSystem(System *sys) override
{
Workload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
}
loader::Arch getArch() const override { return bootloader->getArch(); }
diff --git a/src/arch/riscv/linux/fs_workload.hh
b/src/arch/riscv/linux/fs_workload.hh
index cb29bee..1dc704d 100644
--- a/src/arch/riscv/linux/fs_workload.hh
+++ b/src/arch/riscv/linux/fs_workload.hh
@@ -51,7 +51,8 @@
setSystem(System *sys) override
{
KernelWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
}
ByteOrder byteOrder() const override { return ByteOrder::little; }
diff --git a/src/arch/riscv/se_workload.hh
[gem5-dev] [L] Change in gem5/gem5[develop]: mem: implement ThreadBridge
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/65071?usp=email )
Change subject: mem: implement ThreadBridge
..
mem: implement ThreadBridge
ThreadBridge is used for communication between two SimObjects from
different threads (EventQueue).
Change-Id: I3e00df9184404599dfacef64b505cd0b64ee46aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65071
Reviewed-by: Jason Lowe-Power
Reviewed-by: Yu-hsin Wang
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/SConscript
A src/mem/ThreadBridge.py
A src/mem/thread_bridge.cc
A src/mem/thread_bridge.hh
4 files changed, 288 insertions(+), 0 deletions(-)
Approvals:
kokoro: Regressions pass
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Yu-hsin Wang: Looks good to me, approved
diff --git a/src/mem/SConscript b/src/mem/SConscript
index ad42fe8..3bcfc0d 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -67,6 +67,7 @@
SimObject('SerialLink.py', sim_objects=['SerialLink'])
SimObject('MemDelay.py', sim_objects=['MemDelay', 'SimpleMemDelay'])
SimObject('PortTerminator.py', sim_objects=['PortTerminator'])
+SimObject('ThreadBridge.py', sim_objects=['ThreadBridge'])
Source('abstract_mem.cc')
Source('addr_mapper.cc')
@@ -93,6 +94,7 @@
Source('snoop_filter.cc')
Source('stack_dist_calc.cc')
Source('sys_bridge.cc')
+Source('thread_bridge.cc')
Source('token_port.cc')
Source('tport.cc')
Source('xbar.cc')
diff --git a/src/mem/ThreadBridge.py b/src/mem/ThreadBridge.py
new file mode 100644
index 000..f0ee089
--- /dev/null
+++ b/src/mem/ThreadBridge.py
@@ -0,0 +1,60 @@
+# Copyright 2022 Google, LLC
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+
+class ThreadBridge(SimObject):
+"""Bridge for SimObjects from different threads (EventQueues)
+
+When two SimObjects running on two separate threads (EventQueues), an
+access from one side to the other side could easily cause event
scheduled
+on the wrong event queue.
+
+ThreadBridge is used to migrate the EventQueue to the one used by
+ThreadBridge itself before sending transation to the other side to
avoid
+the issue. The receiver side is expected to use the same EventQueue
that
+the ThreadBridge is using.
+
+Given that this is only used for simulation speed accelerating, only
the
+atomic and functional access are supported.
+
+Example:
+
+sys.initator = Initiator(eventq_index=0)
+sys.target = Target(eventq_index=1)
+sys.bridge = ThreadBridge(eventq_index=1)
+
+sys.initator.out_port = sys.bridge.in_port
+sys.bridge.out_port = sys.target.in_port
+"""
+
+type = "ThreadBridge"
+cxx_header = "mem/thread_bridge.hh"
+cxx_class = "gem5::ThreadBridge"
+
+in_port = ResponsePort("Incoming port")
+out_port = RequestPort("Outgoing port")
diff --git a/src/mem/thread_bridge.cc b/src/mem/thread_bridge.cc
new file mode 100644
index 000..3f76ef4
--- /dev/null
+++ b/src/mem/thread_bridge.cc
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2022 Google, LLC
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary
[gem5-dev] [M] Change in gem5/gem5[develop]: bazel
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58949 )
Change subject: bazel
..
bazel
Change-Id: I8013b4544b9922f35bcafbb383cc7f1b4d0c11e7
---
A BUILD
A WORKSPACE
A bazel-bin
A bazel-out
A bazel-testlogs
A bazel-upstream
A builddef.bzl
A ext/dnet/BUILD
A ext/iostream3/BUILD
A hello/BUILD
A hello/hello.cc
A src/base/BUILD
A src/dev/BUILD
A src/sim/BUILD
14 files changed, 185 insertions(+), 0 deletions(-)
diff --git a/BUILD b/BUILD
new file mode 100644
index 000..d2d6a7e
--- /dev/null
+++ b/BUILD
@@ -0,0 +1,18 @@
+load("//:builddef.bzl", "config")
+
+package(default_visibility = ["//visibility:public"])
+
+config("have_deprecated_namespace", 1)
+
+config("have_fenv", 1)
+
+config("have_valgrind", 0)
+
+cc_library(
+name = "config",
+hdrs = [
+"config/have_deprecated_namespace.hh",
+"config/have_fenv.hh",
+"config/have_valgrind.hh",
+],
+)
diff --git a/WORKSPACE b/WORKSPACE
new file mode 100644
index 000..e69de29
--- /dev/null
+++ b/WORKSPACE
diff --git a/bazel-bin b/bazel-bin
new file mode 12
index 000..19a8d18
--- /dev/null
+++ b/bazel-bin
@@ -0,0 +1 @@
+/usr/local/google/home/shunhsingou/.cache/bazel/_bazel_shunhsingou/49565d7c865eb89d24e99f6508df830b/execroot/__main__/bazel-out/k8-fastbuild/bin
\ No newline at end of file
diff --git a/bazel-out b/bazel-out
new file mode 12
index 000..28dd258
--- /dev/null
+++ b/bazel-out
@@ -0,0 +1 @@
+/usr/local/google/home/shunhsingou/.cache/bazel/_bazel_shunhsingou/49565d7c865eb89d24e99f6508df830b/execroot/__main__/bazel-out
\ No newline at end of file
diff --git a/bazel-testlogs b/bazel-testlogs
new file mode 12
index 000..d68ff1d
--- /dev/null
+++ b/bazel-testlogs
@@ -0,0 +1 @@
+/usr/local/google/home/shunhsingou/.cache/bazel/_bazel_shunhsingou/49565d7c865eb89d24e99f6508df830b/execroot/__main__/bazel-out/k8-fastbuild/testlogs
\ No newline at end of file
diff --git a/bazel-upstream b/bazel-upstream
new file mode 12
index 000..ea0f8b5
--- /dev/null
+++ b/bazel-upstream
@@ -0,0 +1 @@
+/usr/local/google/home/shunhsingou/.cache/bazel/_bazel_shunhsingou/49565d7c865eb89d24e99f6508df830b/execroot/__main__
\ No newline at end of file
diff --git a/builddef.bzl b/builddef.bzl
new file mode 100644
index 000..ddb021d
--- /dev/null
+++ b/builddef.bzl
@@ -0,0 +1,15 @@
+def config(name, value):
+native.genrule(
+name = name,
+srcs = [],
+outs = [
+"config/%s.hh" % name,
+],
+cmd = """
+echo "#define %s %s" >"$@"
+""" % (name.upper(), value),
+)
+
+def simobject(name, enums):
+native.genrule(
+)
diff --git a/ext/dnet/BUILD b/ext/dnet/BUILD
new file mode 100644
index 000..68543ba
--- /dev/null
+++ b/ext/dnet/BUILD
@@ -0,0 +1,10 @@
+package(default_visibility = ["//visibility:public"])
+
+cc_library(
+name = "dnet",
+hdrs = ["os.h"],
+copts = [
+"-Iext",
+],
+includes = ["."],
+)
diff --git a/ext/iostream3/BUILD b/ext/iostream3/BUILD
new file mode 100644
index 000..155fca3
--- /dev/null
+++ b/ext/iostream3/BUILD
@@ -0,0 +1,9 @@
+package(default_visibility = ["//visibility:public"])
+
+cc_library(
+name = "iostream3",
+hdrs = [
+"zfstream.h",
+],
+includes = ["."],
+)
diff --git a/hello/BUILD b/hello/BUILD
new file mode 100644
index 000..08e322d
--- /dev/null
+++ b/hello/BUILD
@@ -0,0 +1,4 @@
+cc_binary(
+name = "hello",
+srcs = ["hello.cc"],
+)
diff --git a/hello/hello.cc b/hello/hello.cc
new file mode 100644
index 000..f59acf8
--- /dev/null
+++ b/hello/hello.cc
@@ -0,0 +1,6 @@
+#include
+
+int main()
+{
+ std::cout << "Hello" << std::endl;
+}
diff --git a/src/base/BUILD b/src/base/BUILD
new file mode 100644
index 000..7f9c780
--- /dev/null
+++ b/src/base/BUILD
@@ -0,0 +1,96 @@
+cc_library(
+name = "base",
+srcs = [
+"atomicio.cc",
+"bitfield.cc",
+"bmpwriter.cc",
+"channel_addr.cc",
+"debug.cc",
+"fenv.cc",
+"fiber.cc",
+"framebuffer.cc",
+"hostinfo.cc",
+"imgwriter.cc",
+"inet.cc",
+"inifile.cc",
+"logging.cc",
+"match.cc",
+"output.cc",
+"pixel.cc",
+"pngwriter.cc",
+"pollevent.cc",
+"random.cc",
+"socket.cc",
+"statistics.cc",
+"str.cc",
+"temperature.cc",
+"time.cc",
+"trace.cc",
+"types.cc",
+"version.cc",
+],
+hdrs = glob(["*.hh"]),
+copts = [
+"-Isrc",
+"-std=c++17",
+],
+deps = [
+"//:config",
+"//ext/dnet",
+"//ext/iostream3",
+"//src/dev",
+"//src/sim",
+],
+)
+
+# SourceLib('png', tags='png')
+#
+# Source('pngwriter.cc', tags='png')
+# Source('fiber.cc')
+# Source('framebuffer.cc')
+#
[gem5-dev] Change in gem5/gem5[develop]: fastmodel: make gem5 fastmodel build hermetic
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55085 )
Change subject: fastmodel: make gem5 fastmodel build hermetic
..
fastmodel: make gem5 fastmodel build hermetic
This CL makes fastmodel RPATH relative to $ORIGIN instead of absolute
path. In this way we can move build folder (installing), without
breaking gem5 run.
Change-Id: I8b16d749252b982e45dfe779a5df931015a0e07d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55085
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/SConscript
M src/arch/arm/fastmodel/arm_fast_model.py
2 files changed, 42 insertions(+), 20 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/SConscript
b/src/arch/arm/fastmodel/SConscript
index ccfc620..69749bf 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -81,7 +81,16 @@
pvlib_lib_dir = pvlib_home.Dir('lib').Dir(pvlib_flavor)
simulation_engine_name = 'libMAXCOREInitSimulationEngine.3.so'
-simulation_engine_lib = pvlib_lib_dir.File(simulation_engine_name)
+simulation_engine_lib = env.Command(
+Dir(env['BUILDDIR']).File(simulation_engine_name),
+pvlib_lib_dir.File(simulation_engine_name),
+MakeAction("cp ${SOURCE} ${TARGET}", Transform('COPY')))
+
+arm_singleton_registry_name = 'arm_singleton_registry.so'
+arm_singleton_registry_lib = env.Command(
+Dir(env['BUILDDIR']).File(arm_singleton_registry_name),
+pvlib_lib_dir.File(arm_singleton_registry_name),
+MakeAction("cp ${SOURCE} ${TARGET}", Transform('COPY')))
def staticify(env, name):
@@ -95,9 +104,7 @@
full_name = Dir(path).File(static_name).get_abspath()
if os.path.isfile(full_name):
return File(full_name)
-
-return name
-
+raise BuildError("Failed to find FM static lib: " + name)
# Adjust the build environment to support building in Fast Models.
@@ -121,16 +128,20 @@
pvlib_home.Dir('Iris').Dir(pvlib_flavor),
)
env.Append(LIBPATH=lib_paths)
-env.Append(RPATH=lib_paths)
-fm_libs = (
+# Per ARM's 11.16 release note, a platform build with simgen automatically
+# copies libraries into the build target directory along with the other
+# dependencies. Therefore, we only need to add each simgen result into
rpath and
+# no other shared librarires are required here.
+fm_static_libs = (
'components',
'pvbus',
'armctmodel',
'fmruntime',
'IrisSupport',
)
-env.Append(LIBS=list(staticify(env, lib) for lib in fm_libs))
+env.Append(LIBS=list(staticify(env, lib) for lib in fm_static_libs))
+
system_libs = (
'atomic',
'dl',
@@ -337,7 +348,8 @@
self.headerpaths = [gen_dir]
self.libs = static_lib_nodes + shared_libs
self.libpaths = [simgen_dir]
-self.rpaths = [simgen_dir]
+# Simgen also puts required share library under the project folder.
+self.rpaths = [simgen_dir, project_file_dir]
self.log = gen_dir.File('build_%s.log' % tlc)
self.simgen_cmd = env.subst('${SIMGEN} -p %s --configuration %s
-b ' +
'--verbose off --num-build-cpus 100 --build-dir %s >%s') % \
@@ -364,6 +376,11 @@
# but the difference is probably not significant.
env.SideEffect(next(license_cycle), lib_nodes[0])
+# We need a copy of the simulation engine lib and
arm_singleton_registry
+# (introduced in 11.16) alongside the executable.
+Depends(lib_nodes[0], simulation_engine_lib)
+Depends(lib_nodes[0], arm_singleton_registry_lib)
+
def prepare_env(self, env):
env.Append(LIBPATH=self.libpaths)
env.AddLocalRPATH(*self.rpaths)
diff --git a/src/arch/arm/fastmodel/arm_fast_model.py
b/src/arch/arm/fastmodel/arm_fast_model.py
index c9d1113..f11443d 100644
--- a/src/arch/arm/fastmodel/arm_fast_model.py
+++ b/src/arch/arm/fastmodel/arm_fast_model.py
@@ -42,21 +42,9 @@
# 7.6 of the Fast Models User Guide.
def scx_initialize(id):
-# Change our working directory to where the simulation engine library
-# is so that the fast model code can find it. It looks in the binary
-# directory and in the current working directory, and we can change
-# the later. This avoids having to make copies of that library all
-# over the place.
-cwd = os.getcwd()
-os.chdir(os.path.join(buildEnv['PVLIB_HOME'], 'lib',
- buildEnv['PVLIB_FLAVOR']))
-
# Actually run scx_initialize.
_m5.arm_fast_model.scx_initialize(id)
-# Restore the previous working directory.
-os.chdir(cwd)
-
def scx_load_application(instance, application):
_m5.arm_fast_model.scx_load_application(instance, application)
--
To view, visit
[gem5-dev] Change in gem5/gem5[develop]: fastmodel: make gem5 fastmodel build harmonic
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55085 )
Change subject: fastmodel: make gem5 fastmodel build harmonic
..
fastmodel: make gem5 fastmodel build harmonic
This CL makes fastmodel RPATH relative to $ORIGIN instead of absolute
path. In this way we can move build folder (installing), without
breaking gem5 run.
Change-Id: I8b16d749252b982e45dfe779a5df931015a0e07d
---
M src/arch/arm/fastmodel/SConscript
M src/arch/arm/fastmodel/arm_fast_model.py
2 files changed, 35 insertions(+), 18 deletions(-)
diff --git a/src/arch/arm/fastmodel/SConscript
b/src/arch/arm/fastmodel/SConscript
index 63b1b16..12bc5d3 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -95,9 +95,7 @@
full_name = Dir(path).File(static_name).get_abspath()
if os.path.isfile(full_name):
return File(full_name)
-
-return name
-
+raise BuildError("Failed to find FM staic lib: " + name)
# Adjust the build environment to support building in Fast Models.
@@ -121,16 +119,27 @@
pvlib_home.Dir('Iris').Dir(pvlib_flavor),
)
env.Append(LIBPATH=lib_paths)
-env.Append(RPATH=lib_paths)
-fm_libs = (
+fm_static_libs = (
'components',
'pvbus',
'armctmodel',
'fmruntime',
'IrisSupport',
)
-env.Append(LIBS=list(staticify(env, lib) for lib in fm_libs))
+env.Append(LIBS=list(staticify(env, lib) for lib in fm_static_libs))
+
+fm_shared_libs = (
+'armctmodel',
+)
+for fm_shared_lib in fm_shared_libs:
+name = '${SHLIBPREFIX}%s${SHLIBSUFFIX}' % fm_shared_lib
+env.Execute(Copy(Dir('pvlib').File('lib%s.so' % fm_shared_lib),
+ pvlib_lib_dir.File('lib%s.so' % fm_shared_lib)))
+env.Append(LIBPATH=Dir('pvlib'))
+env.Append(LIBS=fm_shared_libs)
+env.AddLocalRPATH(Dir('pvlib'))
+
system_libs = (
'atomic',
'dl',
@@ -331,6 +340,13 @@
# but the difference is probably not significant.
env.SideEffect(next(license_cycle), lib_nodes[0])
+# We need a copy of the simulation engine lib alongside the
executable
+# so that the license check works properly.
+local_engine = Dir(env['BUILDDIR']).File(simulation_engine_name)
+Depends(lib_nodes[0], local_engine)
+env.Command(local_engine, simulation_engine_lib,
+MakeAction("cp ${SOURCE} ${TARGET}", Transform('COPY')))
+
def prepare_env(self, env):
env.Append(LIBPATH=self.libpaths)
env.AddLocalRPATH(*self.rpaths)
diff --git a/src/arch/arm/fastmodel/arm_fast_model.py
b/src/arch/arm/fastmodel/arm_fast_model.py
index c9d1113..f11443d 100644
--- a/src/arch/arm/fastmodel/arm_fast_model.py
+++ b/src/arch/arm/fastmodel/arm_fast_model.py
@@ -42,21 +42,9 @@
# 7.6 of the Fast Models User Guide.
def scx_initialize(id):
-# Change our working directory to where the simulation engine library
-# is so that the fast model code can find it. It looks in the binary
-# directory and in the current working directory, and we can change
-# the later. This avoids having to make copies of that library all
-# over the place.
-cwd = os.getcwd()
-os.chdir(os.path.join(buildEnv['PVLIB_HOME'], 'lib',
- buildEnv['PVLIB_FLAVOR']))
-
# Actually run scx_initialize.
_m5.arm_fast_model.scx_initialize(id)
-# Restore the previous working directory.
-os.chdir(cwd)
-
def scx_load_application(instance, application):
_m5.arm_fast_model.scx_load_application(instance, application)
--
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[gem5-dev] Change in gem5/gem5[develop]: Fix for 11.16 fastmodel
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52543 )
Change subject: Fix for 11.16 fastmodel
..
Fix for 11.16 fastmodel
Change-Id: Id6bfa1c374e9c9e65f2c234654f87567d2b29c09
---
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
1 file changed, 60 insertions(+), 51 deletions(-)
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
index 735e06d..ff82bbe 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -310,67 +310,67 @@
{ ArmISA::MISCREG_CSSELR, "CSSELR_EL1" }, //XXX verify
// ArmISA::MISCREG_CSSELR_NS?
// ArmISA::MISCREG_CSSELR_S?
-{ ArmISA::MISCREG_VPIDR, "VPIDR" },
-{ ArmISA::MISCREG_VMPIDR, "VMPIDR" },
+// ArmISA::MISCREG_VPIDR?
+// ArmISA::MISCREG_VMPIDR?,
// ArmISA::MISCREG_SCTLR?
// ArmISA::MISCREG_SCTLR_NS?
// ArmISA::MISCREG_SCTLR_S?
// ArmISA::MISCREG_ACTLR?
// ArmISA::MISCREG_ACTLR_NS?
// ArmISA::MISCREG_ACTLR_S?
-{ ArmISA::MISCREG_CPACR, "CPACR" },
+// ArmISA::MISCREG_CPACR?
{ ArmISA::MISCREG_SCR, "SCR" },
{ ArmISA::MISCREG_SDER, "SDER" },
-{ ArmISA::MISCREG_NSACR, "NSACR" },
-{ ArmISA::MISCREG_HSCTLR, "HSCTLR" },
-{ ArmISA::MISCREG_HACTLR, "HACTLR" },
-{ ArmISA::MISCREG_HCR, "HCR" },
-{ ArmISA::MISCREG_HDCR, "HDCR" },
-{ ArmISA::MISCREG_HCPTR, "HCPTR" },
+// ArmISA::MISCREG_NSACR?
+// ArmISA::MISCREG_HSCTLR?
+// ArmISA::MISCREG_HACTLR?
+// ArmISA::MISCREG_HCR?
+// ArmISA::MISCREG_HDCR?
+// ArmISA::MISCREG_HCPTR?
{ ArmISA::MISCREG_HSTR, "HSTR_EL2" }, //XXX verify
-{ ArmISA::MISCREG_HACR, "HACR" },
+// ArmISA::MISCREG_HACR?
// ArmISA::MISCREG_TTBR0?
-{ ArmISA::MISCREG_TTBR0_NS, "NS_TTBR0" }, //XXX verify
+// ArmISA::MISCREG_TTBR0_NS?
// ArmISA::MISCREG_TTBR0_S?
// ArmISA::MISCREG_TTBR1?
-{ ArmISA::MISCREG_TTBR1_NS, "NS_TTBR1" }, //XXX verify
+// ArmISA::MISCREG_TTBR1_NS?
// ArmISA::MISCREG_TTBR1_S?
// ArmISA::MISCREG_TTBCR?
-{ ArmISA::MISCREG_TTBCR_NS, "NS_TTBCR" }, //XXX verify
+// ArmISA::MISCREG_TTBCR_NS?
// ArmISA::MISCREG_TTBCR_S?
// ArmISA::MISCREG_HTCR?
// ArmISA::MISCREG_VTCR?
// ArmISA::MISCREG_DACR?
-{ ArmISA::MISCREG_DACR_NS, "NS_DACR" }, //XXX verify
+// ArmISA::MISCREG_DACR_NS?
// ArmISA::MISCREG_DACR_S?
// ArmISA::MISCREG_DFSR?
-{ ArmISA::MISCREG_DFSR_NS, "NS_DFSR" }, //XXX verify
+// ArmISA::MISCREG_DFSR_NS?
// ArmISA::MISCREG_DFSR_S?
// ArmISA::MISCREG_IFSR?
-{ ArmISA::MISCREG_IFSR_NS, "NS_IFSR" },
+// ArmISA::MISCREG_IFSR_NS?
// ArmISA::MISCREG_IFSR_S?
-{ ArmISA::MISCREG_ADFSR, "ADFSR" },
+// { ArmISA::MISCREG_ADFSR, "ADFSR" },
// ArmISA::MISCREG_ADFSR_NS?
// ArmISA::MISCREG_ADFSR_S?
-{ ArmISA::MISCREG_AIFSR, "AIFSR" },
+// ArmISA::MISCREG_AIFSR?
// ArmISA::MISCREG_AIFSR_NS?
// ArmISA::MISCREG_AIFSR_S?
// ArmISA::MISCREG_HADFSR?
// ArmISA::MISCREG_HAIFSR?
-{ ArmISA::MISCREG_HSR, "HSR" },
+// ArmISA::MISCREG_HSR?
// ArmISA::MISCREG_DFAR?
-{ ArmISA::MISCREG_DFAR_NS, "NS_DFAR" }, //XXX verify
+// ArmISA::MISCREG_DFAR_NS?
// ArmISA::MISCREG_DFAR_S?
// ArmISA::MISCREG_IFAR?
-{ ArmISA::MISCREG_IFAR_NS, "NS_IFAR" }, //XXX verify
+// ArmISA::MISCREG_IFAR_NS?
// ArmISA::MISCREG_IFAR_S?
-{ ArmISA::MISCREG_HDFAR, "HDFAR" },
-{ ArmISA::MISCREG_HIFAR, "HIFAR" },
-{ ArmISA::MISCREG_HPFAR, "HPFAR" },
+// ArmISA::MISCREG_HDFAR?
+// ArmISA::MISCREG_HIFAR?
+// ArmISA::MISCREG_HPFAR?
{ ArmISA::MISCREG_ICIALLUIS, "ICIALLUIS" },
// ArmISA::MISCREG_BPIALLIS?
// ArmISA::MISCREG_PAR?
-{ ArmISA::MISCREG_PAR_NS, "NS_PAR" }, //XXX verify
+// ArmISA::MISCREG_PAR_NS?
// ArmISA::MISCREG_PAR_S?
{ ArmISA::MISCREG_ICIALLU, "ICIALLU" },
{ ArmISA::MISCREG_ICIMVAU, "ICIMVAU" },
@@ -445,50 +445,50 @@
// ArmISA::MISCREG_L2CTLR?
// ArmISA::MISCREG_L2ECTLR?
// ArmISA::MISCREG_PRRR?
-{ ArmISA::MISCREG_PRRR_NS, "NS_PRRR" }, //XXX verify
+// ArmISA::MISCREG_PRRR_NS?
// ArmISA::MISCREG_PRRR_S?
// ArmISA::MISCREG_MAIR0?
// ArmISA::MISCREG_MAIR0_NS?
// ArmISA::MISCREG_MAIR0_S?
// ArmISA::MISCREG_NMRR?
-{ ArmISA::MISCREG_NMRR_NS, "NS_NMRR" }, //XXX verify
+// ArmISA::MISCREG_NMRR_NS?
[gem5-dev] Change in gem5/gem5[develop]: fastmodel: print stdout when build command fail
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40475 )
Change subject: fastmodel: print stdout when build command fail
..
fastmodel: print stdout when build command fail
Originally we only print command stdout in verbose build. This leads
to misleading debug message when there is error happen in a non-verbose
build. This CL prints stdout when the step fails.
Change-Id: I8c34ac5576269177ae70fc5e01650193fd252b0b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40475
Tested-by: kokoro
Reviewed-by: Gabe Black
Maintainer: Earl Ou
---
M src/arch/arm/fastmodel/SConscript
1 file changed, 20 insertions(+), 7 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Earl Ou: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/SConscript
b/src/arch/arm/fastmodel/SConscript
index 21b3d3c..c659434 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -36,6 +36,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from itertools import cycle
+import shlex
Import('*')
@@ -306,16 +307,18 @@
self.libs = static_lib_nodes + shared_libs
self.libpaths = [simgen_dir]
self.rpaths = [simgen_dir]
+self.log = gen_dir.File('build_%s.log' % tlc)
+self.simgen_cmd = env.subst('${SIMGEN} -p %s --configuration %s
-b ' +
+'--verbose off --num-build-cpus 100 --build-dir %s >%s') % \
+(shlex.quote(project_file.srcnode().abspath),
+ shlex.quote(config_name),
+ shlex.quote(simgen_dir.abspath),
+ shlex.quote(self.log.abspath))
-simgen_cmd = env.subst('${SIMGEN} -p %s --configuration %s -b ' +
-'--verbose off --num-build-cpus 100 --build-dir %s') % \
-(project_file.srcnode().abspath, config_name,
simgen_dir.abspath)
-if not GetOption('verbose'):
-simgen_cmd += ' > /dev/null'
-simgen_action = MakeAction(simgen_cmd, Transform('SIMGEN'))
sources = [project_file]
sources.extend(extra_deps)
-env.Command(lib_nodes + self.headers, sources, simgen_action)
+env.Command(lib_nodes + self.headers + [self.log], sources,
+Action(self.simgen_builder, Transform('SIMGEN')))
# Distribute simgen actions among ARM license slots. All actions
which
# have a given license as a "side effect" will be serialized
relative
# to each other, meaning the number of licenses being used
concurrently
@@ -331,6 +334,16 @@
env.Append(CPPPATH=self.headerpaths)
env.Prepend(LIBS=self.libs)
+def simgen_builder(self, target, source, env):
+cmd = self.simgen_cmd
+if not GetOption('verbose'):
+cmd = "@" + cmd
+res = env.Execute(cmd)
+# Print output when execution return non-zero or in verbose mode.
+if res or GetOption('verbose'):
+env.Execute('@cat %s' % self.log.abspath)
+return res
+
class ArmFastModelBin(Executable):
def __init__(self, target, *components_and_sources):
--
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Gerrit-Change-Number: 40475
Gerrit-PatchSet: 5
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: fix cntfrq in A76
Earl Ou has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40355 ) Change subject: fastmodel: fix cntfrq in A76 .. fastmodel: fix cntfrq in A76 Change-Id: I7d1167e8b61d6768039c34fe1ee54560f7845dfa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40355 Reviewed-by: Ahbong Chang Maintainer: Gabe Black Tested-by: kokoro --- M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Ahbong Chang: Looks good to me, approved Gabe Black: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc index 11e8c98..5da724b 100644 --- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc +++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc @@ -42,7 +42,7 @@ for (auto *tc : threadContexts) tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, params().cntfrq); -evs_base_cpu->setSysCounterFrq(cluster->params().cntfrq); +evs_base_cpu->setSysCounterFrq(params().cntfrq); } void -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40355 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7d1167e8b61d6768039c34fe1ee54560f7845dfa Gerrit-Change-Number: 40355 Gerrit-PatchSet: 2 Gerrit-Owner: Earl Ou Gerrit-Reviewer: Ahbong Chang Gerrit-Reviewer: Earl Ou Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: scons,fastmodel: workaround SideEffect in scons
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40476 )
Change subject: scons,fastmodel: workaround SideEffect in scons
..
scons,fastmodel: workaround SideEffect in scons
Previously we use SideEffect to control the usage of license files.
However, a scons issue https://github.com/SCons/scons/issues/2777
generate strange error message when one of the build step fail, and
hide the actual information. This CL creates a workaround implementation.
Change-Id: I9739790a3b405204ee04acb3f548bc91dc7f219d
---
M src/arch/arm/fastmodel/SConscript
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/fastmodel/SConscript
b/src/arch/arm/fastmodel/SConscript
index 5cde27f..1c7ab4f 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -247,6 +247,14 @@
arm_licenses = list((Value(object()) for i in range(license_count)))
license_cycle = cycle(arm_licenses)
+# https://github.com/SCons/scons/issues/2777 causes
+# strange error message when using SideEffect. Here we create a workaround
+# until the original issue fixed.
+workaround_scons_issue_2777 = True
+
+if workaround_scons_issue_2777:
+pool_deps = {}
+
class ArmFastModelComponent(object):
def __init__(self, project_file, *extra_deps):
project_file = File(project_file)
@@ -331,7 +339,13 @@
#
# This allocation is fixed and may not be as optimal as a dynamic
one,
# but the difference is probably not significant.
-env.SideEffect(next(license_cycle), lib_nodes[0])
+if not workaround_scons_issue_2777:
+env.SideEffect(next(license_cycle), lib_nodes[0])
+else:
+pool_idx = next(license_cycle)
+if pool_deps.get(pool_idx):
+Depends(lib_nodes[0], pool_deps[pool_idx])
+pool_deps[pool_idx] = lib_nodes[0]
def prepare_env(self, env):
env.Append(LIBPATH=self.libpaths)
--
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Gerrit-Change-Number: 40476
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons,fastmodel: print stdout when build command fail
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40475 )
Change subject: scons,fastmodel: print stdout when build command fail
..
scons,fastmodel: print stdout when build command fail
Originally we only print command stdout in verbose build. This leads
to misleading debug message when there is error happen in a non-verbose
build. This CL prints stdout when the step fails.
Change-Id: I8c34ac5576269177ae70fc5e01650193fd252b0b
---
M src/arch/arm/fastmodel/SConscript
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/fastmodel/SConscript
b/src/arch/arm/fastmodel/SConscript
index 21b3d3c..5cde27f 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -36,6 +36,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from itertools import cycle
+import tempfile
Import('*')
@@ -311,7 +312,14 @@
'--verbose off --num-build-cpus 100 --build-dir %s') % \
(project_file.srcnode().abspath, config_name,
simgen_dir.abspath)
if not GetOption('verbose'):
-simgen_cmd += ' > /dev/null'
+with tempfile.NamedTemporaryFile() as f:
+# Run the build cmd, and only print stdout when there is
build
+# failure. We need to manually remove the tempfile because
+# the actual command is run after this 'with' block exit.
+simgen_cmd = (
+'({cmd} >{log}) || (cat {log}; rm -f {log}; exit
1)'.format(
+cmd=simgen_cmd,
+log=f.name))
simgen_action = MakeAction(simgen_cmd, Transform('SIMGEN'))
sources = [project_file]
sources.extend(extra_deps)
--
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[gem5-dev] Change in gem5/gem5[develop]: systemc: remove boost header dependency
Earl Ou has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40315 ) Change subject: systemc: remove boost header dependency .. systemc: remove boost header dependency The current tests included don't require boost header to work. Remove the dependency. This also gets rid of the warning message generated by the latest boost headers. Tested by running systemC tests: src/systemc/tests/verify.py --update-json \ --filter-file=src/systemc/tests/working.filt -j 56 build/ARM/ Change-Id: I9d3bfe145597335abdf24f2de85ed3c0708aea27 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40315 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- M src/systemc/ext/systemc 1 file changed, 0 insertions(+), 6 deletions(-) Approvals: Gabe Black: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/systemc/ext/systemc b/src/systemc/ext/systemc index 60ec1e6..6968b4c 100644 --- a/src/systemc/ext/systemc +++ b/src/systemc/ext/systemc @@ -28,12 +28,6 @@ #ifndef __SYSTEMC_EXT_SYSTEMC__ #define __SYSTEMC_EXT_SYSTEMC__ -// This include isn't supposed to be necessary, but some regression tests -// assume that the sc_bind macro will work without explicitly including the -// boost headers. This is in contradiction to the spec which says boost isn't -// a required dependency. -#include - #include "channel/_channel.hh" #include "core/_core.hh" #include "dt/_dt.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40315 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9d3bfe145597335abdf24f2de85ed3c0708aea27 Gerrit-Change-Number: 40315 Gerrit-PatchSet: 3 Gerrit-Owner: Earl Ou Gerrit-Reviewer: Earl Ou Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: kokoro Gerrit-CC: Yu-hsin Wang Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: fastmodel: fix cntfrq in A76
Earl Ou has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/40355 ) Change subject: fastmodel: fix cntfrq in A76 .. fastmodel: fix cntfrq in A76 Change-Id: I7d1167e8b61d6768039c34fe1ee54560f7845dfa --- M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc index 11e8c98..5da724b 100644 --- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc +++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc @@ -42,7 +42,7 @@ for (auto *tc : threadContexts) tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, params().cntfrq); -evs_base_cpu->setSysCounterFrq(cluster->params().cntfrq); +evs_base_cpu->setSysCounterFrq(params().cntfrq); } void -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40355 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7d1167e8b61d6768039c34fe1ee54560f7845dfa Gerrit-Change-Number: 40355 Gerrit-PatchSet: 1 Gerrit-Owner: Earl Ou Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: systemc: remove boost header dependency
Earl Ou has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/40315 ) Change subject: systemc: remove boost header dependency .. systemc: remove boost header dependency The current tests included doesn't require boost header to work. Remove the dependency. This also gets rid of the warning message generated by the latest boost headers. Change-Id: I9d3bfe145597335abdf24f2de85ed3c0708aea27 --- M src/systemc/ext/systemc 1 file changed, 0 insertions(+), 6 deletions(-) diff --git a/src/systemc/ext/systemc b/src/systemc/ext/systemc index 60ec1e6..6968b4c 100644 --- a/src/systemc/ext/systemc +++ b/src/systemc/ext/systemc @@ -28,12 +28,6 @@ #ifndef __SYSTEMC_EXT_SYSTEMC__ #define __SYSTEMC_EXT_SYSTEMC__ -// This include isn't supposed to be necessary, but some regression tests -// assume that the sc_bind macro will work without explicitly including the -// boost headers. This is in contradiction to the spec which says boost isn't -// a required dependency. -#include - #include "channel/_channel.hh" #include "core/_core.hh" #include "dt/_dt.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40315 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9d3bfe145597335abdf24f2de85ed3c0708aea27 Gerrit-Change-Number: 40315 Gerrit-PatchSet: 1 Gerrit-Owner: Earl Ou Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: fastmodel: add interface to update system counter freq
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40278 )
Change subject: fastmodel: add interface to update system counter freq
..
fastmodel: add interface to update system counter freq
This CL set the cntfrq and system counter frequency at once from python
script. This aligns the fastmodel implementation to other part of gem5
CPU.
Change-Id: I78c9a7be801112844c03d2669a94d57015136d16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40278
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
M src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
M src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
M src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/iris/cpu.hh
10 files changed, 55 insertions(+), 4 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index 1decdf9..11e8c98 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -41,6 +41,8 @@
{
for (auto *tc : threadContexts)
tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0,
params().cntfrq);
+
+evs_base_cpu->setSysCounterFrq(cluster->params().cntfrq);
}
void
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc
b/src/arch/arm/fastmodel/CortexA76/evs.cc
index 29d8877..02ccaab 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -46,6 +46,13 @@
template
void
+ScxEvsCortexA76::setSysCounterFrq(uint64_t sys_counter_frq)
+{
+periphClockRateControl->set_mul_div(sys_counter_frq, 1);
+}
+
+template
+void
ScxEvsCortexA76::setCluster(SimObject *cluster)
{
gem5CpuCluster = dynamic_cast(cluster);
@@ -86,6 +93,7 @@
}
clockRateControl.bind(this->clock_rate_s);
+periphClockRateControl.bind(this->periph_clock_rate_s);
}
template
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh
b/src/arch/arm/fastmodel/CortexA76/evs.hh
index fa12ff8..4aa43b6 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -63,6 +63,7 @@
SC_HAS_PROCESS(ScxEvsCortexA76);
ClockRateControlInitiatorSocket clockRateControl;
+ClockRateControlInitiatorSocket periphClockRateControl;
typedef sc_gem5::TlmTargetBaseWrapper<
64, svp_gicv3_comms::gicv3_comms_fw_if,
@@ -105,6 +106,8 @@
void setClkPeriod(Tick clk_period) override;
+void setSysCounterFrq(uint64_t sys_counter_frq) override;
+
void setCluster(SimObject *cluster) override;
};
diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
index 1968931..04dae41 100644
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
@@ -35,7 +35,7 @@
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
-clockDivPeriph : ClockDivider(mul=0x0180);
+clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@
clockDiv.rate.set64(mul, div);
}
}
+slave port periph_clock_rate_s
+{
+behavior set_mul_div(uint64_t mul, uint64_t div)
+{
+clockDivPeriph.rate.set64(mul, div);
+}
+}
slave port redistributor[1];
// External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
index e0f7a93..0279140 100644
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
@@ -35,7 +35,7 @@
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
-clockDivPeriph : ClockDivider(mul=0x0180);
+clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@
clockDiv.rate.set64(mul, div);
}
}
+slave port periph_clock_rate_s
+{
+behavior set_mul_div(uint64_t mul, uint64_t div)
+{
+clockDivPeriph.rate.set64(mul, div);
+}
+}
slave port redistributor[2];
// External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
index 9ce9027..b18b102 100644
--- a/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
@@ -35,7 +35,7 @@
// Clocks.
clock1Hz : MasterClock();
clockDiv :
[gem5-dev] Change in gem5/gem5[develop]: fastmodel: create base class for EVS CPU
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40277 )
Change subject: fastmodel: create base class for EVS CPU
..
fastmodel: create base class for EVS CPU
Previously we use attribute and event for communication between gem5
SimObject to systemC fastmodel sc_module. Creating a base class allows us
to perform casting once and get all the interface required. Also,
instead of warning on attribute not found, we should make simulator
panic if the sc_module does not provide the interface we need.
Change-Id: I91e1036cb792d556dfc4010e7a0f138b1519b079
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40277
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/iris/cpu.cc
M src/arch/arm/fastmodel/iris/cpu.hh
8 files changed, 70 insertions(+), 133 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index d2b9676..1decdf9 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -104,16 +104,9 @@
for (int i = 0; i < p.cores.size(); i++)
p.cores[i]->setCluster(this, i);
-sc_core::sc_attr_base *base;
-
-base = evs->get_attribute(Iris::Gem5CpuClusterAttributeName);
-auto *gem5_cluster_attr =
-dynamic_cast *>(base);
-panic_if(base && !gem5_cluster_attr,
- "The EVS gem5 CPU cluster attribute was not of type "
- "sc_attribute.");
-if (gem5_cluster_attr)
-gem5_cluster_attr->value = this;
+Iris::BaseCpuEvs *e = dynamic_cast(evs);
+panic_if(!e, "EVS should be of type Iris::BaseCpuEvs");
+e->setCluster(this);
set_evs_param("core.BROADCASTATOMIC", p.BROADCASTATOMIC);
set_evs_param("core.BROADCASTCACHEMAINT", p.BROADCASTCACHEMAINT);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc
b/src/arch/arm/fastmodel/CortexA76/evs.cc
index 360a5dd..29d8877 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -39,19 +39,23 @@
template
void
-ScxEvsCortexA76::clockChangeHandler()
+ScxEvsCortexA76::setClkPeriod(Tick clk_period)
{
-clockRateControl->set_mul_div(SimClock::Int::s, clockPeriod.value);
+clockRateControl->set_mul_div(SimClock::Int::s, clk_period);
+}
+
+template
+void
+ScxEvsCortexA76::setCluster(SimObject *cluster)
+{
+gem5CpuCluster = dynamic_cast(cluster);
+panic_if(!gem5CpuCluster, "Cluster should be of type
CortexA76Cluster");
}
template
ScxEvsCortexA76::ScxEvsCortexA76(
const sc_core::sc_module_name _name, const Params ) :
Base(mod_name), amba(Base::amba, p.name + ".amba", -1),
-clockChanged(Iris::ClockEventName.c_str()),
-clockPeriod(Iris::PeriodAttributeName.c_str()),
-gem5CpuCluster(Iris::Gem5CpuClusterAttributeName.c_str()),
-sendFunctional(Iris::SendFunctionalAttributeName.c_str()),
params(p)
{
for (int i = 0; i < CoreCount; i++) {
@@ -82,15 +86,6 @@
}
clockRateControl.bind(this->clock_rate_s);
-
-this->add_attribute(gem5CpuCluster);
-this->add_attribute(clockPeriod);
-SC_METHOD(clockChangeHandler);
-this->dont_initialize();
-this->sensitive << clockChanged;
-
-sendFunctional.value = [this](PacketPtr pkt) { sendFunc(pkt); };
-this->add_attribute(sendFunctional);
}
template
@@ -109,12 +104,10 @@
{
Base::before_end_of_elaboration();
-auto *cluster = gem5CpuCluster.value;
-
-auto set_on_change = [cluster](
+auto set_on_change = [this](
SignalReceiver , ArmInterruptPinGen *gen, int num)
{
-auto *pin = gen->get(cluster->getCore(num)->getContext(0));
+auto *pin = gen->get(gem5CpuCluster->getCore(num)->getContext(0));
auto handler = [pin](bool status)
{
status ? pin->raise() : pin->clear();
@@ -123,15 +116,15 @@
};
for (int i = 0; i < CoreCount; i++) {
-set_on_change(*cnthpirq[i], cluster->params().cnthpirq, i);
-set_on_change(*cnthvirq[i], cluster->params().cnthvirq, i);
-set_on_change(*cntpsirq[i], cluster->params().cntpsirq, i);
-set_on_change(*cntvirq[i], cluster->params().cntvirq, i);
-set_on_change(*commirq[i], cluster->params().commirq, i);
-set_on_change(*ctidbgirq[i], cluster->params().ctidbgirq, i);
-set_on_change(*pmuirq[i], cluster->params().pmuirq, i);
-set_on_change(*vcpumntirq[i], cluster->params().vcpumntirq, i);
-
[gem5-dev] Change in gem5/gem5[develop]: fastmodel: remove incorrect cntfrq update
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40276 )
Change subject: fastmodel: remove incorrect cntfrq update
..
fastmodel: remove incorrect cntfrq update
The register cntfrq should be set to system counter frequency.
However, the current fastmodel implementation accidentally set it to
core frequency. This CL removes the wrong implementation, and real
cntfrq setting is performed in the initState.
Change-Id: I6c62822a4fbbcc0c499f79f6003dabb0c133f997
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40276
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
1 file changed, 0 insertions(+), 13 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
index 68ff1a8..724b04d 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
@@ -66,19 +66,6 @@
Base(p, scx::scx_get_iris_connection_interface()), _params(p)
{}
-void
-clockPeriodUpdated() override
-{
-Base::clockPeriodUpdated();
-
-// FIXME(b/139447397): this is a workaround since CNTFRQ_EL0
should not
-// be modified after clock is changed in real hardwares. Remove or
-// modify this after a more reasonable solution is found.
-for (auto *tc : threadContexts) {
-tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0,
frequency());
-}
-}
-
void initState() override;
template
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40276
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6c62822a4fbbcc0c499f79f6003dabb0c133f997
Gerrit-Change-Number: 40276
Gerrit-PatchSet: 3
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-CC: Yu-hsin Wang
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util: Fix packet parser for Python3
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40075 )
Change subject: util: Fix packet parser for Python3
..
util: Fix packet parser for Python3
Change-Id: Id5124135b0dd4049ce6531d7bdbc562d33f4d299
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40075
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M util/decode_packet_trace.py
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/decode_packet_trace.py b/util/decode_packet_trace.py
index e3486e6..21d7f9a 100755
--- a/util/decode_packet_trace.py
+++ b/util/decode_packet_trace.py
@@ -63,7 +63,7 @@
exit(-1)
# Read the magic number in 4-byte Little Endian
-magic_number = proto_in.read(4)
+magic_number = proto_in.read(4).decode()
if magic_number != "gem5":
print("Unrecognized file", sys.argv[1])
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40075
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id5124135b0dd4049ce6531d7bdbc562d33f4d299
Gerrit-Change-Number: 40075
Gerrit-PatchSet: 4
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: create base class for EVS CPU
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40277 )
Change subject: fastmodel: create base class for EVS CPU
..
fastmodel: create base class for EVS CPU
Previously we use attribute and event for communication between gem5
SimObject to systemC fastmodel sc_module. Creating a base class allows us
to perform casting once and get all the interface required. Also,
instead of warning on attribute not found, we should make simulator
panic if the sc_module does not provide the interface we need.
Change-Id: I91e1036cb792d556dfc4010e7a0f138b1519b079
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/iris/cpu.cc
M src/arch/arm/fastmodel/iris/cpu.hh
8 files changed, 71 insertions(+), 132 deletions(-)
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index d2b9676..897be24 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -104,16 +104,9 @@
for (int i = 0; i < p.cores.size(); i++)
p.cores[i]->setCluster(this, i);
-sc_core::sc_attr_base *base;
-
-base = evs->get_attribute(Iris::Gem5CpuClusterAttributeName);
-auto *gem5_cluster_attr =
-dynamic_cast *>(base);
-panic_if(base && !gem5_cluster_attr,
- "The EVS gem5 CPU cluster attribute was not of type "
- "sc_attribute.");
-if (gem5_cluster_attr)
-gem5_cluster_attr->value = this;
+Iris::BaseCpuEvs* e = dynamic_cast(evs);
+panic_if(!e, "EVS should be of type Iris::BaseCpuEvs");
+e->setCluster(this);
set_evs_param("core.BROADCASTATOMIC", p.BROADCASTATOMIC);
set_evs_param("core.BROADCASTCACHEMAINT", p.BROADCASTCACHEMAINT);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc
b/src/arch/arm/fastmodel/CortexA76/evs.cc
index 360a5dd..b4153cc 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -39,19 +39,23 @@
template
void
-ScxEvsCortexA76::clockChangeHandler()
+ScxEvsCortexA76::setClkFrq(uint64_t clk_frq)
{
-clockRateControl->set_mul_div(SimClock::Int::s, clockPeriod.value);
+clockRateControl->set_mul_div(clk_frq, 1);
+}
+
+template
+void
+ScxEvsCortexA76::setCluster(SimObject* cluster)
+{
+gem5CpuCluster = dynamic_cast(cluster);
+panic_if(!gem5CpuCluster, "Cluster should be of type
CortexA76Cluster");
}
template
ScxEvsCortexA76::ScxEvsCortexA76(
const sc_core::sc_module_name _name, const Params ) :
Base(mod_name), amba(Base::amba, p.name + ".amba", -1),
-clockChanged(Iris::ClockEventName.c_str()),
-clockPeriod(Iris::PeriodAttributeName.c_str()),
-gem5CpuCluster(Iris::Gem5CpuClusterAttributeName.c_str()),
-sendFunctional(Iris::SendFunctionalAttributeName.c_str()),
params(p)
{
for (int i = 0; i < CoreCount; i++) {
@@ -82,15 +86,6 @@
}
clockRateControl.bind(this->clock_rate_s);
-
-this->add_attribute(gem5CpuCluster);
-this->add_attribute(clockPeriod);
-SC_METHOD(clockChangeHandler);
-this->dont_initialize();
-this->sensitive << clockChanged;
-
-sendFunctional.value = [this](PacketPtr pkt) { sendFunc(pkt); };
-this->add_attribute(sendFunctional);
}
template
@@ -109,12 +104,10 @@
{
Base::before_end_of_elaboration();
-auto *cluster = gem5CpuCluster.value;
-
-auto set_on_change = [cluster](
+auto set_on_change = [this](
SignalReceiver , ArmInterruptPinGen *gen, int num)
{
-auto *pin = gen->get(cluster->getCore(num)->getContext(0));
+auto *pin = gen->get(gem5CpuCluster->getCore(num)->getContext(0));
auto handler = [pin](bool status)
{
status ? pin->raise() : pin->clear();
@@ -123,15 +116,15 @@
};
for (int i = 0; i < CoreCount; i++) {
-set_on_change(*cnthpirq[i], cluster->params().cnthpirq, i);
-set_on_change(*cnthvirq[i], cluster->params().cnthvirq, i);
-set_on_change(*cntpsirq[i], cluster->params().cntpsirq, i);
-set_on_change(*cntvirq[i], cluster->params().cntvirq, i);
-set_on_change(*commirq[i], cluster->params().commirq, i);
-set_on_change(*ctidbgirq[i], cluster->params().ctidbgirq, i);
-set_on_change(*pmuirq[i], cluster->params().pmuirq, i);
-set_on_change(*vcpumntirq[i], cluster->params().vcpumntirq, i);
-set_on_change(*cntpnsirq[i], cluster->params().cntpnsirq, i);
+set_on_change(*cnthpirq[i], gem5CpuCluster->params().cnthpirq, i);
+set_on_change(*cnthvirq[i], gem5CpuCluster->params().cnthvirq, i);
+set_on_change(*cntpsirq[i],
[gem5-dev] Change in gem5/gem5[develop]: fastmodel: remove incorrect cntfrq update
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40276 )
Change subject: fastmodel: remove incorrect cntfrq update
..
fastmodel: remove incorrect cntfrq update
The register cntfrq should be set to system counter frequency.
However, the current fastmodel implementation accidentally set it to
core frequency. This CL removes the wrong implementation, and real
cntfrq setting is performed in the base class's initStat.
Change-Id: I6c62822a4fbbcc0c499f79f6003dabb0c133f997
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
1 file changed, 0 insertions(+), 13 deletions(-)
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
index 68ff1a8..724b04d 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
@@ -66,19 +66,6 @@
Base(p, scx::scx_get_iris_connection_interface()), _params(p)
{}
-void
-clockPeriodUpdated() override
-{
-Base::clockPeriodUpdated();
-
-// FIXME(b/139447397): this is a workaround since CNTFRQ_EL0
should not
-// be modified after clock is changed in real hardwares. Remove or
-// modify this after a more reasonable solution is found.
-for (auto *tc : threadContexts) {
-tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0,
frequency());
-}
-}
-
void initState() override;
template
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6c62822a4fbbcc0c499f79f6003dabb0c133f997
Gerrit-Change-Number: 40276
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: add interface to update system counter freq
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40278 )
Change subject: fastmodel: add interface to update system counter freq
..
fastmodel: add interface to update system counter freq
This CL set the cntfrq and system counter frequency at once from python
script. This aligns the fastmodel implementation to other part of gem5
CPU.
Change-Id: I78c9a7be801112844c03d2669a94d57015136d16
---
M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
M src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
M src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
M src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
M src/arch/arm/fastmodel/iris/cpu.hh
9 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
index 0b0fa8d..bbfe18a 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -340,6 +340,7 @@
"signal).")
ptw_latency = Param.UInt64(0, "Page table walker latency for TA "\
"(Timing Annotation), expressed in simulation ticks")
+sys_counter_frq = Param.UInt64(0x180, "The system counter
frequency")
tlb_latency = Param.UInt64(0, "TLB latency for TA (Timing
Annotation), "\
"expressed in simulation ticks")
treat_dcache_cmos_to_pou_as_nop = Param.Bool(False, "Whether dcache "\
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index 897be24..7fdc6c2 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -39,8 +39,12 @@
void
CortexA76::initState()
{
+warn_if(params().cntfrq != cluster->params().sys_counter_frq,
+"CNTFRQ configured freq does not match the system counter
freq\n");
for (auto *tc : threadContexts)
tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0,
params().cntfrq);
+
+evs_base_cpu->setSysCounterFrq(cluster->params().sys_counter_frq);
}
void
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc
b/src/arch/arm/fastmodel/CortexA76/evs.cc
index b4153cc..c1fe23a 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -46,6 +46,13 @@
template
void
+ScxEvsCortexA76::setSysCounterFrq(uint64_t sys_counter_frq)
+{
+periphClockRateControl->set_mul_div(sys_counter_frq, 1);
+}
+
+template
+void
ScxEvsCortexA76::setCluster(SimObject* cluster)
{
gem5CpuCluster = dynamic_cast(cluster);
@@ -86,6 +93,7 @@
}
clockRateControl.bind(this->clock_rate_s);
+periphClockRateControl.bind(this->periph_clock_rate_s);
}
template
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh
b/src/arch/arm/fastmodel/CortexA76/evs.hh
index 64d605a..c8e20fd 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -63,6 +63,7 @@
SC_HAS_PROCESS(ScxEvsCortexA76);
ClockRateControlInitiatorSocket clockRateControl;
+ClockRateControlInitiatorSocket periphClockRateControl;
typedef sc_gem5::TlmTargetBaseWrapper<
64, svp_gicv3_comms::gicv3_comms_fw_if,
@@ -105,6 +106,8 @@
void setClkFrq(uint64_t clk_frq) override;
+void setSysCounterFrq(uint64_t sys_counter_frq) override;
+
void setCluster(SimObject* cluster) override;
};
diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
index 1968931..04dae41 100644
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
@@ -35,7 +35,7 @@
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
-clockDivPeriph : ClockDivider(mul=0x0180);
+clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@
clockDiv.rate.set64(mul, div);
}
}
+slave port periph_clock_rate_s
+{
+behavior set_mul_div(uint64_t mul, uint64_t div)
+{
+clockDivPeriph.rate.set64(mul, div);
+}
+}
slave port redistributor[1];
// External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
index e0f7a93..0279140 100644
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
@@ -35,7 +35,7 @@
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
-clockDivPeriph : ClockDivider(mul=0x0180);
+clockDivPeriph : ClockDivider();
}
connection
@@ -77,6
[gem5-dev] Change in gem5/gem5[develop]: Fix package parser
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40075 )
Change subject: Fix package parser
..
Fix package parser
Change-Id: Id5124135b0dd4049ce6531d7bdbc562d33f4d299
---
M util/decode_packet_trace.py
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/decode_packet_trace.py b/util/decode_packet_trace.py
index e3486e6..21d7f9a 100755
--- a/util/decode_packet_trace.py
+++ b/util/decode_packet_trace.py
@@ -63,7 +63,7 @@
exit(-1)
# Read the magic number in 4-byte Little Endian
-magic_number = proto_in.read(4)
+magic_number = proto_in.read(4).decode()
if magic_number != "gem5":
print("Unrecognized file", sys.argv[1])
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Id5124135b0dd4049ce6531d7bdbc562d33f4d299
Gerrit-Change-Number: 40075
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: systemc: remove pipe through flag in TLM extension
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37375 )
Change subject: systemc: remove pipe through flag in TLM extension
..
systemc: remove pipe through flag in TLM extension
Pipe through flag should be equal to whether we have the extension
in TLM payload or not. However, in the current implementation the
two are different and cause issues when we have gem5 - SystemC
connection.
Change-Id: I2c318777d91dca446c1a700d9f7cff356d29ae6d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37375
Reviewed-by: Earl Ou
Maintainer: Earl Ou
Tested-by: kokoro
---
M src/systemc/tlm_bridge/gem5_to_tlm.cc
M src/systemc/tlm_bridge/sc_ext.cc
M src/systemc/tlm_bridge/sc_ext.hh
M src/systemc/tlm_bridge/tlm_to_gem5.cc
M util/tlm/src/sc_ext.cc
M util/tlm/src/sc_ext.hh
M util/tlm/src/sc_master_port.cc
M util/tlm/src/sc_slave_port.cc
8 files changed, 15 insertions(+), 44 deletions(-)
Approvals:
Earl Ou: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc
b/src/systemc/tlm_bridge/gem5_to_tlm.cc
index f03548c..9d10876 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.cc
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -167,18 +167,14 @@
bool need_retry = false;
-/*
- * If the packet was piped through and needs a response, we don't
need
- * to touch the packet and can forward it directly as a response.
- * Otherwise, we need to make a response and send the transformed
- * packet.
- */
-if (extension.isPipeThrough()) {
-if (packet->isResponse()) {
-need_retry = !bridgeResponsePort.sendTimingResp(packet);
-}
-} else if (packet->needsResponse()) {
+// If there is another gem5 model under the receiver side, and
already
+// make a response packet back, we can simply send it back.
Otherwise,
+// we make a response packet before sending it back to the
initiator
+// side gem5 module.
+if (packet->needsResponse()) {
packet->makeResponse();
+}
+if (packet->isResponse()) {
need_retry = !bridgeResponsePort.sendTimingResp(packet);
}
diff --git a/src/systemc/tlm_bridge/sc_ext.cc
b/src/systemc/tlm_bridge/sc_ext.cc
index ea188c4..194ecbc 100644
--- a/src/systemc/tlm_bridge/sc_ext.cc
+++ b/src/systemc/tlm_bridge/sc_ext.cc
@@ -41,7 +41,6 @@
Gem5Extension::Gem5Extension(PacketPtr _packet)
{
packet = _packet;
-pipeThrough = false;
}
Gem5Extension &
diff --git a/src/systemc/tlm_bridge/sc_ext.hh
b/src/systemc/tlm_bridge/sc_ext.hh
index 0d9fc91..56a19a77 100644
--- a/src/systemc/tlm_bridge/sc_ext.hh
+++ b/src/systemc/tlm_bridge/sc_ext.hh
@@ -54,12 +54,8 @@
const tlm::tlm_generic_payload );
PacketPtr getPacket();
-bool isPipeThrough() const { return pipeThrough; }
-void setPipeThrough() { pipeThrough = true; }
-
private:
PacketPtr packet;
-bool pipeThrough;
};
} // namespace Gem5SystemC
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc
b/src/systemc/tlm_bridge/tlm_to_gem5.cc
index a1a8382..143eeac 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -181,7 +181,6 @@
// world and we can pipe through the original packet. Otherwise, we
// generate a new packet based on the transaction.
if (extension != nullptr) {
-extension->setPipeThrough();
pkt = extension->getPacket();
} else {
pkt = payload2packet(_id, trans);
@@ -306,7 +305,6 @@
// If there is an extension, this transaction was initiated by the gem5
// world and we can pipe through the original packet.
if (extension != nullptr) {
-extension->setPipeThrough();
pkt = extension->getPacket();
} else {
pkt = payload2packet(_id, trans);
@@ -343,7 +341,6 @@
// If there is an extension, this transaction was initiated by the gem5
// world and we can pipe through the original packet.
if (extension != nullptr) {
-extension->setPipeThrough();
bmp.sendFunctional(extension->getPacket());
} else {
auto pkt = payload2packet(_id, trans);
@@ -369,7 +366,6 @@
// If there is an extension, this transaction was initiated by the gem5
// world and we can pipe through the original packet.
if (extension != nullptr) {
-extension->setPipeThrough();
pkt = extension->getPacket();
} else {
pkt = payload2packet(_id, trans);
@@ -447,8 +443,6 @@
// delete it. The packet travels back with the transaction.
if (extension == nullptr)
destroyPacket(pkt);
-else
-sc_assert(extension->isPipeThrough());
sendBeginResp(trans, delay);
trans.release();
diff --git a/util/tlm/src/sc_ext.cc
[gem5-dev] Change in gem5/gem5[develop]: scons: only wrap message with positive value
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/35596 )
Change subject: scons: only wrap message with positive value
..
scons: only wrap message with positive value
In case we have small TTY, scons failed with wrong testwrap value. Fix
the issue.
Change-Id: I8ec1d55c6856c1e592a57a68067091b796ac84ae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35596
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M site_scons/gem5_scons/__init__.py
1 file changed, 15 insertions(+), 12 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/site_scons/gem5_scons/__init__.py
b/site_scons/gem5_scons/__init__.py
index 3323112..4208cf1 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -160,20 +160,23 @@
text_width = 80
def print_message(prefix, color, message, **kwargs):
-# Precompute some useful values.
prefix_len = len(prefix)
-wrap_width = text_width - prefix_len
-padding = ' ' * prefix_len
+if text_width > prefix_len:
+wrap_width = text_width - prefix_len
+padding = ' ' * prefix_len
-# First split on newlines.
-lines = message.split('\n')
-# Then wrap each line to the required width.
-wrapped_lines = []
-for line in lines:
-wrapped_lines.extend(textwrap.wrap(line, wrap_width))
-# Finally add the prefix and padding on extra lines, and glue it all
back
-# together.
-message = prefix + ('\n' + padding).join(wrapped_lines)
+# First split on newlines.
+lines = message.split('\n')
+# Then wrap each line to the required width.
+wrapped_lines = []
+for line in lines:
+wrapped_lines.extend(textwrap.wrap(line, wrap_width))
+# Finally add the prefix and padding on extra lines, and glue it
all
+# back together.
+message = prefix + ('\n' + padding).join(wrapped_lines)
+else:
+# We have very small terminal, indent formatting doesn't help.
+message = prefix + message
# Add in terminal escape sequences.
message = color + termcap.Bold + message + termcap.Normal
# Actually print the message.
--
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Gerrit-Change-Id: I8ec1d55c6856c1e592a57a68067091b796ac84ae
Gerrit-Change-Number: 35596
Gerrit-PatchSet: 4
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jui-min Lee
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: only wrap message with positive value
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35596 )
Change subject: scons: only wrap message with positive value
..
scons: only wrap message with positive value
In case we have small TTY, scons failed with wrong testwrap value. Fix
the issue.
Change-Id: I8ec1d55c6856c1e592a57a68067091b796ac84ae
---
M site_scons/gem5_scons/__init__.py
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/site_scons/gem5_scons/__init__.py
b/site_scons/gem5_scons/__init__.py
index 7fa8d3d..be5676d 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -161,18 +161,21 @@
def print_message(prefix, color, message, **kwargs):
# Precompute some useful values.
prefix_len = len(prefix)
-wrap_width = text_width - prefix_len
-padding = ' ' * prefix_len
+if text_width > prefix_len:
+ wrap_width = text_width - prefix_len
+ padding = ' ' * prefix_len
-# First split on newlines.
-lines = message.split('\n')
-# Then wrap each line to the required width.
-wrapped_lines = []
-for line in lines:
-wrapped_lines.extend(textwrap.wrap(line, wrap_width))
-# Finally add the prefix and padding on extra lines, and glue it all
back
-# together.
-message = prefix + ('\n' + padding).join(wrapped_lines)
+ # First split on newlines.
+ lines = message.split('\n')
+ # Then wrap each line to the required width.
+ wrapped_lines = []
+ for line in lines:
+ wrapped_lines.extend(textwrap.wrap(line, wrap_width))
+ # Finally add the prefix and padding on extra lines, and glue it all
back
+ # together.
+ message = prefix + ('\n' + padding).join(wrapped_lines)
+else:
+ message = prefix + message
# Add in terminal escape sequences.
message = color + termcap.Bold + message + termcap.Normal
# Actually print the message.
--
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[gem5-dev] Change in gem5/gem5[develop]: SCons: avoid interactive access in non-tty
Earl Ou has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/35595 ) Change subject: SCons: avoid interactive access in non-tty .. SCons: avoid interactive access in non-tty We saw some strange behavior when building scons without an interactive TTY. This seems be caused by the control signal set from curses.initscr() and endwin(). To avoid issues, we should avoid those operation when running in non interactive situation. Change-Id: I9cf8e48a786d47d567ba193f0b069f638e8db647 --- M site_scons/gem5_scons/__init__.py 1 file changed, 4 insertions(+), 0 deletions(-) diff --git a/site_scons/gem5_scons/__init__.py b/site_scons/gem5_scons/__init__.py index 169e0fe..7fa8d3d 100644 --- a/site_scons/gem5_scons/__init__.py +++ b/site_scons/gem5_scons/__init__.py @@ -41,6 +41,7 @@ from __future__ import print_function import os +import sys import textwrap from gem5_scons.util import get_termcap @@ -131,6 +132,9 @@ # The width warning and error messages should be wrapped at. text_width = None +if not sys.stdout.isatty(): +text_width = 80 + # This should work in python 3.3 and above. if text_width is None: try: -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35595 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9cf8e48a786d47d567ba193f0b069f638e8db647 Gerrit-Change-Number: 35595 Gerrit-PatchSet: 1 Gerrit-Owner: Earl Ou Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: base,sim: implement a faster mutex for single thread case
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34915 )
Change subject: base,sim: implement a faster mutex for single thread case
..
base,sim: implement a faster mutex for single thread case
This change applies an atomic variable to check if we really need to
obtain a mutex, and uses a condition variable to notify.
See about 5% improvement in the simulation speed.
Change-Id: I7e165987dcb587b27fae90978b9b3fde6f5563ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34915
Reviewed-by: Andreas Sandberg
Reviewed-by: Richard Cooper
Reviewed-by: Daniel Carvalho
Reviewed-by: Giacomo Travaglini
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/base/SConscript
A src/base/uncontended_mutex.hh
A src/base/uncontended_mutex.test.cc
M src/sim/eventq.cc
M src/sim/eventq.hh
5 files changed, 211 insertions(+), 3 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, but someone else must approve
Giacomo Travaglini: Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve
Richard Cooper: Looks good to me, but someone else must approve
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/SConscript b/src/base/SConscript
index 6514de0..e04d84a 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -73,6 +73,7 @@
GTest('trie.test', 'trie.test.cc')
Source('types.cc')
GTest('types.test', 'types.test.cc', 'types.cc')
+GTest('uncontended_mutex.test', 'uncontended_mutex.test.cc')
Source('stats/group.cc')
Source('stats/text.cc')
diff --git a/src/base/uncontended_mutex.hh b/src/base/uncontended_mutex.hh
new file mode 100644
index 000..721712f
--- /dev/null
+++ b/src/base/uncontended_mutex.hh
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2020 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __BASE_UNCONTENDED_MUTEX_HH__
+#define __BASE_UNCONTENDED_MUTEX_HH__
+
+#include
+#include
+#include
+
+/*
+ * The std::mutex implementation is slower than expected because of many
mode
+ * checking and legacy support.
+ *
+ * The UncontendedMutex uses an atomic flag to check if we really need to
+ * obtain a mutex lock. For most cases without multi-threads event queues,
+ * e.g. non-KVM simulation, this avoid the usage of mutex and speed up the
+ * simulation.
+ */
+class UncontendedMutex
+{
+ private:
+/*
+ * A flag to record the current status:
+ * 0: no one has the lock
+ * 1: exactly one thread has the lock
+ * >1: one or more threads are waiting for the lock
+ */
+std::atomic flag;
+std::mutex m;
+std::condition_variable cv;
+
+bool
+testAndSet(int expected, int desired)
+{
+return flag.compare_exchange_strong(expected, desired);
+}
+
+ public:
+UncontendedMutex() : flag(0) {}
+
+void
+lock()
+{
+/*
+ * Here we use 'flag' to check if we are the first thread to get
the
+ * lock. If not, we try to obtain the real mutex, and use the
condition
+ * variable to wait for the thread who has the lock to release it.
+ *
+ * The flag will be updated to more than 1, so the thread with lock
+ * knows that there is another thread waiting for the lock.
+ */
+while (!testAndSet(0, 1)) {
+std::unique_lock ul(m);
+/*
+ * It is possible that just before we obtain the mutex
[gem5-dev] Change in gem5/gem5[develop]: systemc: avoid mutex lock in non async cases
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34695 )
Change subject: systemc: avoid mutex lock in non async cases
..
systemc: avoid mutex lock in non async cases
Avoid acquiring a mutex lock in case there is no async update in the
scheduler. This helps increasing simulation speed by about 4%.
Change-Id: I971c7bf1a1eeb462086e5da6385c907092b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34695
Reviewed-by: Earl Ou
Maintainer: Earl Ou
Tested-by: kokoro
---
M src/systemc/core/scheduler.cc
M src/systemc/core/scheduler.hh
2 files changed, 5 insertions(+), 1 deletion(-)
Approvals:
Earl Ou: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/systemc/core/scheduler.cc b/src/systemc/core/scheduler.cc
index 50a1e6b..cc0be7c 100644
--- a/src/systemc/core/scheduler.cc
+++ b/src/systemc/core/scheduler.cc
@@ -259,6 +259,7 @@
{
std::lock_guard lock(asyncListMutex);
asyncUpdateList.pushLast(c);
+hasAsyncUpdate = true;
}
void
@@ -325,11 +326,12 @@
Scheduler::runUpdate()
{
status(StatusUpdate);
-{
+if (hasAsyncUpdate) {
std::lock_guard lock(asyncListMutex);
Channel *channel;
while ((channel = asyncUpdateList.getNext()) != nullptr)
updateList.pushLast(channel);
+hasAsyncUpdate = false;
}
try {
diff --git a/src/systemc/core/scheduler.hh b/src/systemc/core/scheduler.hh
index 742f916..13f35ed 100644
--- a/src/systemc/core/scheduler.hh
+++ b/src/systemc/core/scheduler.hh
@@ -28,6 +28,7 @@
#ifndef __SYSTEMC_CORE_SCHEDULER_HH__
#define __SYSTEMC_CORE_SCHEDULER_HH__
+#include
#include
#include
#include
@@ -529,6 +530,7 @@
ChannelList asyncUpdateList;
std::mutex asyncListMutex;
+std::atomic hasAsyncUpdate;
std::map<::Event *, Tick> eventsToSchedule;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34695
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I971c7bf1a1eeb462086e5da6385c907092b3
Gerrit-Change-Number: 34695
Gerrit-PatchSet: 4
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base,sim: implement a faster mutex for single thread case
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34915 )
Change subject: base,sim: implement a faster mutex for single thread case
..
base,sim: implement a faster mutex for single thread case
This change applies an atomic variable to check if we really need to
obtain a mutex, and uses a condition variable to notify.
See about 5% improvement in the simulation speed.
Change-Id: I7e165987dcb587b27fae90978b9b3fde6f5563ef
---
A src/base/fast_mutex.hh
M src/sim/eventq.cc
M src/sim/eventq.hh
3 files changed, 86 insertions(+), 3 deletions(-)
diff --git a/src/base/fast_mutex.hh b/src/base/fast_mutex.hh
new file mode 100644
index 000..b003072
--- /dev/null
+++ b/src/base/fast_mutex.hh
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2020 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __BASE_FAST_MUTEXT_HH__
+#define __BASE_FAST_MUTEXT_HH__
+
+#include
+#include
+#include
+
+/*
+ * The FastMutex uses an atomic flag to check if we really need to obtain a
+ * mutex lock. For most cases without multi-threads event queues, e.g.
non-KVM
+ * simulation, this avoid the system call and speed up the simulation.
+ */
+class FastMutex {
+ private:
+// A flag to record the current status:
+// 0: no one has the lock
+// 1: exactly one thread has the lock
+// >1: more than one threads are waiting for the lock.
+std::atomic flag;
+std::mutex m;
+std::condition_variable cv;
+
+bool test_and_set(int expected, int desired) {
+return flag.compare_exchange_strong(expected, desired);
+}
+
+ public:
+FastMutex() : flag(0) {}
+
+void
+lock()
+{
+while (!test_and_set(0, 1)) {
+std::unique_lock ul(m);
+if (flag++ == 0) // in case flag is set to 0 before we get m.
+break;
+cv.wait(ul);
+}
+}
+
+void
+unlock()
+{
+if (test_and_set(1, 0))
+return;
+
+{
+std::lock_guard g(m);
+flag = 0;
+}
+cv.notify_all();
+}
+};
+
+#endif // __BASE_FAST_MUTEXT_HH__
diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc
index bc4864c..adce51e 100644
--- a/src/sim/eventq.cc
+++ b/src/sim/eventq.cc
@@ -32,6 +32,7 @@
#include
#include
+#include
#include
#include
#include
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index aa54722..ecd9b78 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -41,10 +41,10 @@
#include
#include
#include
-#include
#include
#include "base/debug.hh"
+#include "base/fast_mutex.hh"
#include "base/flags.hh"
#include "base/types.hh"
#include "debug/Event.hh"
@@ -622,7 +622,7 @@
Tick _curTick;
//! Mutex to protect async queue.
-std::mutex async_queue_mutex;
+FastMutex async_queue_mutex;
//! List of events added by other threads to this event queue.
std::list async_queue;
@@ -647,7 +647,7 @@
* @see EventQueue::lock()
* @see EventQueue::unlock()
*/
-std::mutex service_mutex;
+FastMutex service_mutex;
//! Insert / remove event from the queue. Should only be called
//! by thread operating this queue.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34915
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Gerrit-Change-Id:
[gem5-dev] Change in gem5/gem5[develop]: base: avoid std::mutex by implementing a spinlock
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34696 )
Change subject: base: avoid std::mutex by implementing a spinlock
..
base: avoid std::mutex by implementing a spinlock
Eventq and systemC scheduler use std::mutex to protect critical section
across threads. However, their use cases are usually low contention
(e.g., async IO). Acquiring std::mutex is considered expensive in such
cases.
In this change we implement a spinlock. A test in systemC shows about
12% speed improvement.
Change-Id: I3da946bb74ecd1f00a3009c8c4b8d5245667291e
---
A src/base/lock.hh
M src/sim/eventq.hh
M src/systemc/core/scheduler.cc
M src/systemc/core/scheduler.hh
4 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/src/base/lock.hh b/src/base/lock.hh
new file mode 100644
index 000..7167ee7
--- /dev/null
+++ b/src/base/lock.hh
@@ -0,0 +1,9 @@
+#include
+class SpinLock
+{
+ private:
+std::atomic_flag flag = ATOMIC_FLAG_INIT;
+ public:
+void lock() { while (flag.test_and_set(std::memory_order_acquire)); }
+void unlock() { flag.clear(std::memory_order_release); }
+};
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index aa54722..107648f 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -46,6 +46,7 @@
#include "base/debug.hh"
#include "base/flags.hh"
+#include "base/lock.hh"
#include "base/types.hh"
#include "debug/Event.hh"
#include "sim/serialize.hh"
@@ -622,7 +623,7 @@
Tick _curTick;
//! Mutex to protect async queue.
-std::mutex async_queue_mutex;
+SpinLock async_queue_mutex;
//! List of events added by other threads to this event queue.
std::list async_queue;
@@ -647,7 +648,7 @@
* @see EventQueue::lock()
* @see EventQueue::unlock()
*/
-std::mutex service_mutex;
+SpinLock service_mutex;
//! Insert / remove event from the queue. Should only be called
//! by thread operating this queue.
diff --git a/src/systemc/core/scheduler.cc b/src/systemc/core/scheduler.cc
index 50a1e6b..b1a5e9f 100644
--- a/src/systemc/core/scheduler.cc
+++ b/src/systemc/core/scheduler.cc
@@ -27,6 +27,8 @@
#include "systemc/core/scheduler.hh"
+#include
+
#include "base/fiber.hh"
#include "base/logging.hh"
#include "sim/eventq.hh"
@@ -257,7 +259,7 @@
void
Scheduler::asyncRequestUpdate(Channel *c)
{
-std::lock_guard lock(asyncListMutex);
+std::lock_guard lock(asyncListMutex);
asyncUpdateList.pushLast(c);
}
@@ -326,7 +328,7 @@
{
status(StatusUpdate);
{
-std::lock_guard lock(asyncListMutex);
+std::lock_guard lock(asyncListMutex);
Channel *channel;
while ((channel = asyncUpdateList.getNext()) != nullptr)
updateList.pushLast(channel);
diff --git a/src/systemc/core/scheduler.hh b/src/systemc/core/scheduler.hh
index 273faf7..38ddc33 100644
--- a/src/systemc/core/scheduler.hh
+++ b/src/systemc/core/scheduler.hh
@@ -28,10 +28,10 @@
#ifndef __SYSTEMC_CORE_SCHEDULER_HH__
#define __SYSTEMC_CORE_SCHEDULER_HH__
+#include
#include
#include
#include
-#include
#include
#include
@@ -528,7 +528,7 @@
ChannelList updateList;
ChannelList asyncUpdateList;
-std::mutex asyncListMutex;
+SpinLock asyncListMutex;
std::map<::Event *, Tick> eventsToSchedule;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34696
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Gerrit-Branch: develop
Gerrit-Change-Id: I3da946bb74ecd1f00a3009c8c4b8d5245667291e
Gerrit-Change-Number: 34696
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: systemc: avoid mutex lock in non async cases
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34695 )
Change subject: systemc: avoid mutex lock in non async cases
..
systemc: avoid mutex lock in non async cases
Avoid acquiring a mutex lock in case there is no async update in the
scheduler. This helps increasing simulation speed by about 4%.
Change-Id: I971c7bf1a1eeb462086e5da6385c907092b3
---
M src/systemc/core/scheduler.cc
M src/systemc/core/scheduler.hh
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/systemc/core/scheduler.cc b/src/systemc/core/scheduler.cc
index 50a1e6b..cc0be7c 100644
--- a/src/systemc/core/scheduler.cc
+++ b/src/systemc/core/scheduler.cc
@@ -259,6 +259,7 @@
{
std::lock_guard lock(asyncListMutex);
asyncUpdateList.pushLast(c);
+hasAsyncUpdate = true;
}
void
@@ -325,11 +326,12 @@
Scheduler::runUpdate()
{
status(StatusUpdate);
-{
+if (hasAsyncUpdate) {
std::lock_guard lock(asyncListMutex);
Channel *channel;
while ((channel = asyncUpdateList.getNext()) != nullptr)
updateList.pushLast(channel);
+hasAsyncUpdate = false;
}
try {
diff --git a/src/systemc/core/scheduler.hh b/src/systemc/core/scheduler.hh
index 273faf7..b2ab94d 100644
--- a/src/systemc/core/scheduler.hh
+++ b/src/systemc/core/scheduler.hh
@@ -28,6 +28,7 @@
#ifndef __SYSTEMC_CORE_SCHEDULER_HH__
#define __SYSTEMC_CORE_SCHEDULER_HH__
+#include
#include
#include
#include
@@ -529,6 +530,7 @@
ChannelList asyncUpdateList;
std::mutex asyncListMutex;
+std::atomic hasAsyncUpdate;
std::map<::Event *, Tick> eventsToSchedule;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34695
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Gerrit-Branch: develop
Gerrit-Change-Id: I971c7bf1a1eeb462086e5da6385c907092b3
Gerrit-Change-Number: 34695
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: systemc: self-manage TimeSlot in Scheduler
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34615 )
Change subject: systemc: self-manage TimeSlot in Scheduler
..
systemc: self-manage TimeSlot in Scheduler
TimeSlot is new and deleted frequently. Having a recycling memory
manager can help saving the time spent new and delete. Tested and see
about 4% improvement in simulation speed.
Change-Id: I0ab173168336a883b85f768d7fdf07a936a14d69
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34615
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/systemc/core/scheduler.hh
1 file changed, 35 insertions(+), 3 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/systemc/core/scheduler.hh b/src/systemc/core/scheduler.hh
index 693cb3a..273faf7 100644
--- a/src/systemc/core/scheduler.hh
+++ b/src/systemc/core/scheduler.hh
@@ -152,14 +152,24 @@
class TimeSlot : public ::Event
{
public:
-TimeSlot(const Tick& targeted_when) : ::Event(Default_Pri,
AutoDelete),
- targeted_when(targeted_when)
{}
+TimeSlot(Scheduler* scheduler) : ::Event(Default_Pri, AutoDelete),
+ parent_scheduler(scheduler) {}
// Event::when() is only set after it's scheduled to an event
queue.
// However, TimeSlot won't be scheduled before init is done. We
need
// to keep the real 'targeted_when' information before scheduled.
Tick targeted_when;
+Scheduler* parent_scheduler;
ScEvents events;
void process();
+
+ protected:
+void
+releaseImpl() override
+{
+if (!scheduled())
+parent_scheduler->releaseTimeSlot(this);
+}
+
};
typedef std::list TimeSlots;
@@ -259,7 +269,7 @@
while (it != timeSlots.end() && (*it)->targeted_when < tick)
it++;
if (it == timeSlots.end() || (*it)->targeted_when != tick) {
-it = timeSlots.emplace(it, new TimeSlot(tick));
+it = timeSlots.emplace(it, acquireTimeSlot(tick));
schedule(*it, tick);
}
event->schedule((*it)->events, tick);
@@ -386,6 +396,27 @@
void registerTraceFile(TraceFile *tf) { traceFiles.insert(tf); }
void unregisterTraceFile(TraceFile *tf) { traceFiles.erase(tf); }
+TimeSlot*
+acquireTimeSlot(Tick tick)
+{
+TimeSlot *ts = nullptr;
+if (!freeTimeSlots.empty()) {
+ts = freeTimeSlots.top();
+freeTimeSlots.pop();
+} else {
+ts = new TimeSlot(this);
+}
+ts->targeted_when = tick;
+ts->events.clear();
+return ts;
+}
+
+void
+releaseTimeSlot(TimeSlot *ts)
+{
+freeTimeSlots.push(ts);
+}
+
private:
typedef const EventBase::Priority Priority;
static Priority DefaultPriority = EventBase::Default_Pri;
@@ -422,6 +453,7 @@
ScEvents deltas;
TimeSlots timeSlots;
+std::stack freeTimeSlots;
Process *
getNextReady()
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34615
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0ab173168336a883b85f768d7fdf07a936a14d69
Gerrit-Change-Number: 34615
Gerrit-PatchSet: 4
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-CC: Jui-min Lee
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: systemc: use list instead of map in scheduler
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34515 )
Change subject: systemc: use list instead of map in scheduler
..
systemc: use list instead of map in scheduler
The queue in systemC scheduler is implemented as a std::map. This provides
the best big-O solution. However, most of simulation usecases has very
small number of pending events. This is expected as we usually only trigger
a
few new events after some events are processed. In such scenario, we
should optimize for insert/erase instead of search. This change use
std::list instead of std::map.
As a proof, we can find that gem5's original event_queue is also
implemented as a list instead of tree.
We see 5% speed improvement with the example provided by Matthias Jung:
https://gist.github.com/myzinsky/557200aa04556de44a317e0a10f51840
Change-Id: I75c30df9134e94df42fd778115cf923488ff5886
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34515
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/systemc/core/scheduler.cc
M src/systemc/core/scheduler.hh
2 files changed, 28 insertions(+), 16 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/systemc/core/scheduler.cc b/src/systemc/core/scheduler.cc
index 179bd55..50a1e6b 100644
--- a/src/systemc/core/scheduler.cc
+++ b/src/systemc/core/scheduler.cc
@@ -71,8 +71,7 @@
deltas.front()->deschedule();
// Timed notifications.
-for (auto : timeSlots) {
-TimeSlot * = tsp.second;
+for (auto : timeSlots) {
while (!ts->events.empty())
ts->events.front()->deschedule();
deschedule(ts);
diff --git a/src/systemc/core/scheduler.hh b/src/systemc/core/scheduler.hh
index c9ca161..693cb3a 100644
--- a/src/systemc/core/scheduler.hh
+++ b/src/systemc/core/scheduler.hh
@@ -29,6 +29,7 @@
#define __SYSTEMC_CORE_SCHEDULER_HH__
#include
+#include
#include
#include
#include
@@ -151,13 +152,17 @@
class TimeSlot : public ::Event
{
public:
-TimeSlot() : ::Event(Default_Pri, AutoDelete) {}
-
+TimeSlot(const Tick& targeted_when) : ::Event(Default_Pri,
AutoDelete),
+ targeted_when(targeted_when)
{}
+// Event::when() is only set after it's scheduled to an event
queue.
+// However, TimeSlot won't be scheduled before init is done. We
need
+// to keep the real 'targeted_when' information before scheduled.
+Tick targeted_when;
ScEvents events;
void process();
};
-typedef std::map TimeSlots;
+typedef std::list TimeSlots;
Scheduler();
~Scheduler();
@@ -250,12 +255,14 @@
}
// Timed notification/timeout.
-TimeSlot * = timeSlots[tick];
-if (!ts) {
-ts = new TimeSlot;
-schedule(ts, tick);
+auto it = timeSlots.begin();
+while (it != timeSlots.end() && (*it)->targeted_when < tick)
+it++;
+if (it == timeSlots.end() || (*it)->targeted_when != tick) {
+it = timeSlots.emplace(it, new TimeSlot(tick));
+schedule(*it, tick);
}
-event->schedule(ts->events, tick);
+event->schedule((*it)->events, tick);
}
// For descheduling delayed/timed notifications/timeouts.
@@ -270,10 +277,15 @@
}
// Timed notification/timeout.
-auto tsit = timeSlots.find(event->when());
-panic_if(tsit == timeSlots.end(),
+auto tsit = timeSlots.begin();
+while (tsit != timeSlots.end() &&
+ (*tsit)->targeted_when < event->when())
+tsit++;
+
+panic_if(tsit == timeSlots.end() ||
+ (*tsit)->targeted_when != event->when(),
"Descheduling event at time with no events.");
-TimeSlot *ts = tsit->second;
+TimeSlot *ts = *tsit;
ScEvents = ts->events;
assert(on == );
event->deschedule();
@@ -288,7 +300,7 @@
void
completeTimeSlot(TimeSlot *ts)
{
-assert(ts == timeSlots.begin()->second);
+assert(ts == timeSlots.front());
timeSlots.erase(timeSlots.begin());
if (!runToTime && starved())
scheduleStarvationEvent();
@@ -324,7 +336,7 @@
if (pendingCurr())
return 0;
if (pendingFuture())
-return timeSlots.begin()->first - getCurTick();
+return timeSlots.front()->targeted_when - getCurTick();
return MaxTick - getCurTick();
}
@@ -434,7 +446,8 @@
{
return (readyListMethods.empty() && readyListThreads.empty() &&
updateList.empty() && deltas.empty() &&
-(timeSlots.empty() || timeSlots.begin()->first > maxTick)
&&
+(timeSlots.empty()
[gem5-dev] Change in gem5/gem5[develop]: base: use setjmp to speed up fiber
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34356 )
Change subject: base: use setjmp to speed up fiber
..
base: use setjmp to speed up fiber
ucontext is an order of magnitude slower compared to most of the fiber
implementation, mainly due to the additional signal mask operation.
This change applies the trick provided in
http://www.1024cores.net/home/lock-free-algorithms/tricks/fibers,
which uses _setjmp/_longjmp to switch between contexts created by
ucontext.
Combine with NodeList improvement, we see 81% speed improvement with the
example provided by Matthias Jung:
https://gist.github.com/myzinsky/557200aa04556de44a317e0a10f51840
Compared with Accellera's SystemC, gem5 SystemC was originally 10x
slower, and with this change it's about 1.8x.
Change-Id: I0ffb6978e83dc8be049b750dc1baebb3d251601c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34356
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/base/fiber.cc
M src/base/fiber.hh
2 files changed, 18 insertions(+), 5 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/fiber.cc b/src/base/fiber.cc
index 3d2e2e9..fe1bad0 100644
--- a/src/base/fiber.cc
+++ b/src/base/fiber.cc
@@ -145,10 +145,12 @@
setStarted();
-// Swap back to the parent context which is still considered "current",
-// now that we're ready to go.
-int ret M5_VAR_USED = swapcontext(, &_currentFiber->ctx);
-panic_if(ret == -1, strerror(errno));
+if (_setjmp(jmp) == 0) {
+// Swap back to the parent context which is still
considered "current",
+// now that we're ready to go.
+int ret = swapcontext(, &_currentFiber->ctx);
+panic_if(ret == -1, strerror(errno));
+}
// Call main() when we're been reactivated for the first time.
main();
@@ -175,7 +177,8 @@
Fiber *prev = _currentFiber;
Fiber *next = this;
_currentFiber = next;
-swapcontext(>ctx, >ctx);
+if (_setjmp(prev->jmp) == 0)
+_longjmp(next->jmp, 1);
}
Fiber *Fiber::currentFiber() { return _currentFiber; }
diff --git a/src/base/fiber.hh b/src/base/fiber.hh
index dc7ef01..be8937f 100644
--- a/src/base/fiber.hh
+++ b/src/base/fiber.hh
@@ -39,6 +39,12 @@
#include
#endif
+// Avoid fortify source for longjmp to work between ucontext stacks.
+#pragma push_macro("__USE_FORTIFY_LEVEL")
+#undef __USE_FORTIFY_LEVEL
+#include
+#pragma pop_macro("__USE_FORTIFY_LEVEL")
+
#include
#include
@@ -137,6 +143,10 @@
void start();
ucontext_t ctx;
+// ucontext is slow in swapcontext. Here we use _setjmp/_longjmp to
avoid
+// the additional signals for speed up.
+jmp_buf jmp;
+
Fiber *link;
// The stack for this context, or a nullptr if allocated elsewhere.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0ffb6978e83dc8be049b750dc1baebb3d251601c
Gerrit-Change-Number: 34356
Gerrit-PatchSet: 11
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: systemc: self-manage TimeSlot in Scheduler
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34615 )
Change subject: systemc: self-manage TimeSlot in Scheduler
..
systemc: self-manage TimeSlot in Scheduler
TimeSlot is new and deleted frequently. Having a recycling memory
manager can help saving the time spent new and delete. Tested and see
about 4% improvement in simulation speed.
Change-Id: I0ab173168336a883b85f768d7fdf07a936a14d69
---
M src/systemc/core/scheduler.hh
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/src/systemc/core/scheduler.hh b/src/systemc/core/scheduler.hh
index 693cb3a..a45c6d9 100644
--- a/src/systemc/core/scheduler.hh
+++ b/src/systemc/core/scheduler.hh
@@ -152,14 +152,22 @@
class TimeSlot : public ::Event
{
public:
-TimeSlot(const Tick& targeted_when) : ::Event(Default_Pri,
AutoDelete),
- targeted_when(targeted_when)
{}
+TimeSlot(Scheduler* scheduler) : ::Event(Default_Pri, AutoDelete),
+ parent_scheduler(scheduler) {}
// Event::when() is only set after it's scheduled to an event
queue.
// However, TimeSlot won't be scheduled before init is done. We
need
// to keep the real 'targeted_when' information before scheduled.
Tick targeted_when;
+Scheduler* parent_scheduler;
ScEvents events;
void process();
+
+ protected:
+void releaseImpl() override {
+ if (!scheduled())
+ parent_scheduler->releaseTimeSlot(this);
+}
+
};
typedef std::list TimeSlots;
@@ -259,7 +267,7 @@
while (it != timeSlots.end() && (*it)->targeted_when < tick)
it++;
if (it == timeSlots.end() || (*it)->targeted_when != tick) {
-it = timeSlots.emplace(it, new TimeSlot(tick));
+it = timeSlots.emplace(it, acquireTimeSlot(tick));
schedule(*it, tick);
}
event->schedule((*it)->events, tick);
@@ -386,6 +394,23 @@
void registerTraceFile(TraceFile *tf) { traceFiles.insert(tf); }
void unregisterTraceFile(TraceFile *tf) { traceFiles.erase(tf); }
+TimeSlot* acquireTimeSlot(const Tick& tick) {
+ TimeSlot* ts = nullptr;
+ if (!freeTimeSlots.empty()) {
+ts = freeTimeSlots.top();
+freeTimeSlots.pop();
+ } else {
+ts = new TimeSlot(this);
+ }
+ ts->targeted_when = tick;
+ ts->events.clear();
+ return ts;
+}
+
+void releaseTimeSlot(TimeSlot* ts) {
+ freeTimeSlots.push(ts);
+}
+
private:
typedef const EventBase::Priority Priority;
static Priority DefaultPriority = EventBase::Default_Pri;
@@ -422,6 +447,7 @@
ScEvents deltas;
TimeSlots timeSlots;
+std::stack freeTimeSlots;
Process *
getNextReady()
--
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Gerrit-Change-Id: I0ab173168336a883b85f768d7fdf07a936a14d69
Gerrit-Change-Number: 34615
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: systemc: avoid dynamic_cast in the critical path
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34355 )
Change subject: systemc: avoid dynamic_cast in the critical path
..
systemc: avoid dynamic_cast in the critical path
NodeList is in the critical path of the systemc scheduler in gem5. A
unnecessary dynamic_cast in the NodeList slow down the event process by
about 15%. Fix the issue by avoiding dynamic_cast.
We see about 15% speed improvement on the example provided by Matthias Jung:
https://gist.github.com/myzinsky/557200aa04556de44a317e0a10f51840
Compare with Accellera implementation, gem5 version is originally 10x
slower and now it's about 8.5x slower.
Change-Id: I3b4ddca31e58e1d4e96144a4021b0a5bb956fda4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34355
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/systemc/core/list.hh
1 file changed, 7 insertions(+), 2 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/systemc/core/list.hh b/src/systemc/core/list.hh
index b1c5f55..6ba2825 100644
--- a/src/systemc/core/list.hh
+++ b/src/systemc/core/list.hh
@@ -102,8 +102,13 @@
prevListNode = t;
}
-T *getNext() { return dynamic_cast(nextListNode); }
-bool empty() { return getNext() == nullptr; }
+T *
+getNext()
+{
+return empty() ? nullptr : static_cast(nextListNode);
+}
+
+bool empty() { return nextListNode == this; }
};
} // namespace sc_gem5
--
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Gerrit-Change-Id: I3b4ddca31e58e1d4e96144a4021b0a5bb956fda4
Gerrit-Change-Number: 34355
Gerrit-PatchSet: 6
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: systemc: use list instead of map in scheduler
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34515 )
Change subject: systemc: use list instead of map in scheduler
..
systemc: use list instead of map in scheduler
The queue in systemC scheduler is implemented as a std::map. This provides
the best big-O solution. However, most of simulation usecases has very
small number of pending events. This is expected as we usually only trigger
a
few new events after some events are processed. In such scenario, we
should optimize for insert/erase instead of search. This change use
std::list instead of std::map.
As a proof, we can find that gem5's original event_queue is also
implemented as a list instead of tree.
We see 5% speed improvement with the example provided by Matthias Jung:
https://gist.github.com/myzinsky/557200aa04556de44a317e0a10f51840
Change-Id: I75c30df9134e94df42fd778115cf923488ff5886
---
M src/systemc/core/scheduler.hh
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/src/systemc/core/scheduler.hh b/src/systemc/core/scheduler.hh
index c9ca161..c129a35 100644
--- a/src/systemc/core/scheduler.hh
+++ b/src/systemc/core/scheduler.hh
@@ -29,6 +29,7 @@
#define __SYSTEMC_CORE_SCHEDULER_HH__
#include
+#include
#include
#include
#include
@@ -157,7 +158,7 @@
void process();
};
-typedef std::map TimeSlots;
+typedef std::list> TimeSlots;
Scheduler();
~Scheduler();
@@ -250,12 +251,14 @@
}
// Timed notification/timeout.
-TimeSlot * = timeSlots[tick];
-if (!ts) {
-ts = new TimeSlot;
-schedule(ts, tick);
+auto it = timeSlots.begin();
+while (it != timeSlots.end() && it->first < tick)
+it++;
+if (it == timeSlots.end() || it->first != tick) {
+it = timeSlots.emplace(it, tick, new TimeSlot);
+schedule(it->second, tick);
}
-event->schedule(ts->events, tick);
+event->schedule(it->second->events, tick);
}
// For descheduling delayed/timed notifications/timeouts.
@@ -270,8 +273,11 @@
}
// Timed notification/timeout.
-auto tsit = timeSlots.find(event->when());
-panic_if(tsit == timeSlots.end(),
+auto tsit = timeSlots.begin();
+while (tsit != timeSlots.end() && tsit->first < event->when())
+tsit++;
+
+panic_if(tsit == timeSlots.end() || tsit->first != event->when(),
"Descheduling event at time with no events.");
TimeSlot *ts = tsit->second;
ScEvents = ts->events;
--
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Gerrit-Change-Id: I75c30df9134e94df42fd778115cf923488ff5886
Gerrit-Change-Number: 34515
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: systemc: avoid dynamic_cast in the critical path
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34355 )
Change subject: systemc: avoid dynamic_cast in the critical path
..
systemc: avoid dynamic_cast in the critical path
NostList is in the critical path of the event queue in gem5. A
unnecessary dynamic_cast in the NodeList slow down the event process by
about 15%. Fix the issue by avoiding dynamic_cast.
We see about 15% speed improvement on the example provided by Jung Matthias:
https://gist.github.com/myzinsky/557200aa04556de44a317e0a10f51840
Compare with Accellera implementation, gem5 version is originally 10x
slower and now it's about 8.5x slower.
Change-Id: I3b4ddca31e58e1d4e96144a4021b0a5bb956fda4
---
M src/systemc/core/list.hh
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/systemc/core/list.hh b/src/systemc/core/list.hh
index b1c5f55..c22bfc9 100644
--- a/src/systemc/core/list.hh
+++ b/src/systemc/core/list.hh
@@ -102,8 +102,12 @@
prevListNode = t;
}
-T *getNext() { return dynamic_cast(nextListNode); }
-bool empty() { return getNext() == nullptr; }
+T *getNext()
+{
+return nextListNode == this ? nullptr
+: static_cast(nextListNode);
+}
+bool empty() { return nextListNode == this; }
};
} // namespace sc_gem5
--
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Gerrit-Change-Id: I3b4ddca31e58e1d4e96144a4021b0a5bb956fda4
Gerrit-Change-Number: 34355
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: systemc: use setjmp to speed up fiber
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34356 )
Change subject: systemc: use setjmp to speed up fiber
..
systemc: use setjmp to speed up fiber
ucontext is an order of magnitude slower compared to most of the fiber
implementation, mainly due to the additional signal mask operation.
This change applies the trick provided in
http://www.1024cores.net/home/lock-free-algorithms/tricks/fibers,
which uses _setjmp/_longjmp to switch between contexts created by
ucontext.
Combine with NodeList improvement, we see 81% speed improvement with the
example provided by Jung Matthias:
https://gist.github.com/myzinsky/557200aa04556de44a317e0a10f51840
Compared with Accellera's SystemC, gem5 SystemC was originally 10x
slower, and with this change it's about 1.8x.
Change-Id: I0ffb6978e83dc8be049b750dc1baebb3d251601c
---
M src/base/fiber.cc
M src/base/fiber.hh
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/src/base/fiber.cc b/src/base/fiber.cc
index 3d2e2e9..023c091 100644
--- a/src/base/fiber.cc
+++ b/src/base/fiber.cc
@@ -39,6 +39,7 @@
#define _DARWIN_C_SOURCE
#endif
+#include
#include
#include
@@ -145,10 +146,13 @@
setStarted();
-// Swap back to the parent context which is still considered "current",
-// now that we're ready to go.
-int ret M5_VAR_USED = swapcontext(, &_currentFiber->ctx);
-panic_if(ret == -1, strerror(errno));
+if (_setjmp(jmp) == 0)
+{
+// Swap back to the parent context which is still
considered "current",
+// now that we're ready to go.
+int ret M5_VAR_USED = swapcontext(, &_currentFiber->ctx);
+panic_if(ret == -1, strerror(errno));
+}
// Call main() when we're been reactivated for the first time.
main();
@@ -175,7 +179,8 @@
Fiber *prev = _currentFiber;
Fiber *next = this;
_currentFiber = next;
-swapcontext(>ctx, >ctx);
+if (_setjmp(prev->jmp) == 0)
+_longjmp(next->jmp, 1);
}
Fiber *Fiber::currentFiber() { return _currentFiber; }
diff --git a/src/base/fiber.hh b/src/base/fiber.hh
index dc7ef01..b3c9964 100644
--- a/src/base/fiber.hh
+++ b/src/base/fiber.hh
@@ -39,6 +39,8 @@
#include
#endif
+#include
+
#include
#include
@@ -137,6 +139,10 @@
void start();
ucontext_t ctx;
+// ucontext is slow in swapcontext. Here we use _setjmp/_longjmp to
avoid
+// the additional signals for speed up.
+jmp_buf jmp;
+
Fiber *link;
// The stack for this context, or a nullptr if allocated elsewhere.
--
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