[gem5-dev] Change in gem5/gem5[develop]: cpu-kvm,arch-arm: Improve KvmCPU tick event scheduling
Hsuan Hsu has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30919 )
Change subject: cpu-kvm,arch-arm: Improve KvmCPU tick event scheduling
..
cpu-kvm,arch-arm: Improve KvmCPU tick event scheduling
The memory-mapped timer emulated by gem5 is driven by the underlying
gem5 tick, which means that we must align the tick with the host time
to make the timer interrupt fire at a nearly native rate.
In each KVM execution round, the number of ticks incremented is
directly calculated from the number of instructions executed. However,
when a guest CPU switches to idle state, KVM seems to stay in kernel-
space until the POSIX timer set up in user-space raises an expiration
signal, instead of trapping to user-space immediately; and somehow the
instruction count is just too low to match the elapsed host time. This
makes the gem5 tick increment very slowly when the guest is idle and
drastically slow down workloads being sensitive to the guest time which
is driven by timer interrupt.
Before switching to KVM to execute the guest code, gem5 programs the
POSIX timer to expire according to the remaining ticks before the next
event in the event queue. Based on this, we can come up with the
following solution: If KVM returns to user-space due to POSIX timer
expiration, it must be time to process the next gem5 event, so we just
fast-forward the tick (by scheduling the next CPU tick event) to that
event directly without calculating from the instruction count.
There is one more related issue needed to be solved. The KVM exit
reason, KVM_EXIT_INTR, was treated as the case where the KVM execution
was disturbed by POSIX timer expiration. However, there exists a case
where the exit reason is KVM_EXIT_INTR but the POSIX timer has not
expired. Its cause is still unknown, but it can be observed via the
"old_value" argument returned by timer_settime() when disarming the
POSIX timer. In addition, it seems to happen often when a guest CPU is
not in idle state. When this happens, the above tick event scheduling
incorrectly treats KVM_EXIT_INTR as POSIX timer expiration and fast-
forwards the tick to process the next event too early. This makes the
guest feel external events come too fast, and will sometimes cause
trouble. One example is the VSYNC interrupt from HDLCD. The guest seems
to get stuck in VSYNC handling if the KVM CPU is not given enough time
between each VSYNC interrupt to complete a service. (Honestly I did not
dig in to see how the guest handled the VSYNC interrupt and how the
above situation became trouble. I just observed from the debug trace of
GIC & HDLCD & timer, and made this conclusion.) This change also uses
a workaround to detect POSIX timer expiration correctly to make the
guest work with HDLCD.
JIRA: https://gem5.atlassian.net/browse/GEM5-663
Change-Id: I6159238a36fc18c0c881d177a742d8a7745a23ca
Signed-off-by: Hsuan Hsu
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30919
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/cpu/kvm/base.cc
M src/cpu/kvm/timer.cc
M src/cpu/kvm/timer.hh
3 files changed, 24 insertions(+), 5 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index 18aead8..0afab1e 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -691,8 +691,13 @@
}
// Schedule a new tick if we are still running
-if (_status != Idle && _status != RunningMMIOPending)
-schedule(tickEvent, clockEdge(ticksToCycles(delay)));
+if (_status != Idle && _status != RunningMMIOPending) {
+if (_kvmRun->exit_reason == KVM_EXIT_INTR && runTimer->expired())
+schedule(tickEvent, clockEdge(ticksToCycles(
+ curEventQueue()->nextTick() - curTick() + 1)));
+else
+schedule(tickEvent, clockEdge(ticksToCycles(delay)));
+}
}
Tick
diff --git a/src/cpu/kvm/timer.cc b/src/cpu/kvm/timer.cc
index e7b185f..538fd56 100644
--- a/src/cpu/kvm/timer.cc
+++ b/src/cpu/kvm/timer.cc
@@ -122,10 +122,19 @@
struct itimerspec ts;
memset(, 0, sizeof(ts));
-DPRINTF(KvmTimer, "Disarming POSIX timer\n");
-
-if (timer_settime(timer, 0, , NULL) == -1)
+if (timer_settime(timer, 0, , ) == -1)
panic("PosixKvmTimer: Failed to disarm timer\n");
+
+DPRINTF(KvmTimer, "Disarmed POSIX timer: %is%ins left\n",
+prevTimerSpec.it_value.tv_sec,
+prevTimerSpec.it_value.tv_nsec);
+}
+
+bool
+PosixKvmTimer::expired()
+{
+return (prevTimerSpec.it_value.tv_nsec == 0 &&
+prevTimerSpec.it_value.tv_sec == 0);
}
Tick
diff --git a/src/cpu/kvm/timer.hh b/src/cpu/kvm/timer.hh
index 3e5..376ba7c 100644
--- a/src/cpu/kvm/timer.hh
+++ b/src/cpu/kvm/timer.hh
@@ -93,6 +93,9 @@
* signals upon timeout.
*/
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add basic support for KVM_CAP_ARM_USER_IRQ
Hsuan Hsu has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30921 )
Change subject: arch-arm: Add basic support for KVM_CAP_ARM_USER_IRQ
..
arch-arm: Add basic support for KVM_CAP_ARM_USER_IRQ
KVM_CAP_ARM_USER_IRQ is a KVM extension introduced in newer versions of
Linux (>= 4.12). It supports delivering interrupt from the kernel-space
timer to the user-space GIC, which means that it will be unnecessary to
use the memory-mapped timer and emulate it in gem5 anymore.
Using the option provided by this change, Linux is able to boot with 1
CPU successfully, and the speed is slightly faster then the memory-
mapped timer option. However, multicore seems to hang during boot and
still needs more investigation to be enabled.
JIRA: https://gem5.atlassian.net/browse/GEM5-663
Change-Id: I146bbcce3cf66f8f5ebee04ea5f1b9f54868721a
Signed-off-by: Hsuan Hsu
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30921
Tested-by: kokoro
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/arch/arm/kvm/base_cpu.cc
M src/arch/arm/kvm/base_cpu.hh
2 files changed, 49 insertions(+), 2 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index c028106..04c5d0f 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -41,7 +41,9 @@
#include "arch/arm/interrupts.hh"
#include "debug/KvmInt.hh"
+#include "dev/arm/generic_timer.hh"
#include "params/BaseArmKvmCPU.hh"
+#include "params/GenericTimer.hh"
#define INTERRUPT_ID(type, vcpu, irq) (\
((type) << KVM_ARM_IRQ_TYPE_SHIFT) | \
@@ -57,7 +59,8 @@
BaseArmKvmCPU::BaseArmKvmCPU(BaseArmKvmCPUParams *params)
: BaseKvmCPU(params),
- irqAsserted(false), fiqAsserted(false)
+ irqAsserted(false), fiqAsserted(false),
+ virtTimerPin(nullptr), prevDeviceIRQLevel(0)
{
}
@@ -82,6 +85,10 @@
target_config.features[0] |= (1 << KVM_ARM_VCPU_EL1_32BIT);
}
kvmArmVCpuInit(target_config);
+
+if (!vm.hasKernelIRQChip())
+virtTimerPin = static_cast(system)\
+->getGenericTimer()->params()->int_virt->get(tc);
}
Tick
@@ -113,7 +120,29 @@
irqAsserted = simIRQ;
fiqAsserted = simFIQ;
-return BaseKvmCPU::kvmRun(ticks);
+Tick kvmRunTicks = BaseKvmCPU::kvmRun(ticks);
+
+if (!vm.hasKernelIRQChip()) {
+uint64_t device_irq_level =
+getKvmRunState()->s.regs.device_irq_level;
+
+if (!(prevDeviceIRQLevel & KVM_ARM_DEV_EL1_VTIMER) &&
+(device_irq_level & KVM_ARM_DEV_EL1_VTIMER)) {
+
+DPRINTF(KvmInt, "In-kernel vtimer IRQ asserted\n");
+prevDeviceIRQLevel |= KVM_ARM_DEV_EL1_VTIMER;
+virtTimerPin->raise();
+
+} else if ((prevDeviceIRQLevel & KVM_ARM_DEV_EL1_VTIMER) &&
+ !(device_irq_level & KVM_ARM_DEV_EL1_VTIMER)) {
+
+DPRINTF(KvmInt, "In-kernel vtimer IRQ disasserted\n");
+prevDeviceIRQLevel &= ~KVM_ARM_DEV_EL1_VTIMER;
+virtTimerPin->clear();
+}
+}
+
+return kvmRunTicks;
}
const BaseArmKvmCPU::RegIndexVector &
diff --git a/src/arch/arm/kvm/base_cpu.hh b/src/arch/arm/kvm/base_cpu.hh
index 4ee35ca..028cd39 100644
--- a/src/arch/arm/kvm/base_cpu.hh
+++ b/src/arch/arm/kvm/base_cpu.hh
@@ -41,6 +41,7 @@
#include
#include "cpu/kvm/base.hh"
+#include "dev/arm/base_gic.hh"
struct BaseArmKvmCPUParams;
@@ -61,6 +62,23 @@
/** Cached state of the FIQ line */
bool fiqAsserted;
+/**
+ * If the user-space GIC and the kernel-space timer are used
+ * simultaneously, set up this interrupt pin to forward interrupt from
+ * the timer to the GIC when timer IRQ level change is intercepted.
+ */
+ArmInterruptPin *virtTimerPin;
+
+/**
+ * KVM records whether each in-kernel device IRQ is asserted or
+ * disasserted in the kvmRunState->s.regs.device_irq_level bit map,
+ * and guarantees at least one KVM exit when the level changes. We
+ * use only the KVM_ARM_DEV_EL1_VTIMER bit field currently to track
+ * the level of the in-kernel timer, and preserve the last level in
+ * this class member.
+ */
+uint64_t prevDeviceIRQLevel;
+
protected:
typedef std::vector RegIndexVector;
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I146bbcce3cf66f8f5ebee04ea5f1b9f54868721a
Gerrit-Change-Number: 30921
Gerrit-PatchSet: 17
Gerrit-Owner: Hsuan Hsu
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Hsuan Hsu
Gerrit-Reviewer: kokoro
[gem5-dev] Change in gem5/gem5[develop]: cpu-kvm: Initialize _hasKernelIRQChip in the constructor
Hsuan Hsu has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30917 )
Change subject: cpu-kvm: Initialize _hasKernelIRQChip in the constructor
..
cpu-kvm: Initialize _hasKernelIRQChip in the constructor
This class member was only correctly set to true when using an in-kernel
interrupt controller, but was un-initialized when trying to use a user-
space one and would cause trouble.
JIRA: https://gem5.atlassian.net/browse/GEM5-663
Change-Id: I71b052c6da7e8790b05a15c07e7933bc4f912785
Signed-off-by: Hsuan Hsu
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30917
Reviewed-by: Giacomo Travaglini
Reviewed-by: Andreas Sandberg
Maintainer: Giacomo Travaglini
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/cpu/kvm/vm.cc
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/kvm/vm.cc b/src/cpu/kvm/vm.cc
index 720548c..4640ca1 100644
--- a/src/cpu/kvm/vm.cc
+++ b/src/cpu/kvm/vm.cc
@@ -294,6 +294,7 @@
kvm(new Kvm()), system(nullptr),
vmFD(kvm->createVM()),
started(false),
+ _hasKernelIRQChip(false),
nextVCPUID(0)
{
maxMemorySlot = kvm->capNumMemSlots();
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I71b052c6da7e8790b05a15c07e7933bc4f912785
Gerrit-Change-Number: 30917
Gerrit-PatchSet: 8
Gerrit-Owner: Hsuan Hsu
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Hsuan Hsu
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Fix handling of writing timer control registers
Hsuan Hsu has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30918 )
Change subject: dev-arm: Fix handling of writing timer control registers
..
dev-arm: Fix handling of writing timer control registers
We should also deal with change of the imask bit, or we will lose timer
interrupt if the timer expires before the guest kernel unmasks the bit.
More precisely, consider the following common pattern in timer interrupt
handling:
1. Set the interrupt mask bit (CNTV_CTL.IMASK)
2. Reprogram the downcounter (CNTV_TVAL) for the next interrupt
3. Clear the interrupt mask bit (CNTV_CTL.IMASK)
The timer can expires between step 2 & 3 if the value programmed in step
2 is small enough, and this seems very likely to happen in KVM mode. If
we don't check for timer expiration right after unmasking, we will miss
the only chance to inject the interrupt.
JIRA: https://gem5.atlassian.net/browse/GEM5-663
Change-Id: I75e8253bb78d15ae72cb985ed132f896d8e92ca6
Signed-off-by: Hsuan Hsu
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30918
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/generic_timer.cc
1 file changed, 6 insertions(+), 4 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 42b03ad..bf6cd4e 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -313,11 +313,13 @@
_control.enable = new_ctl.enable;
_control.imask = new_ctl.imask;
_control.istatus = old_ctl.istatus;
-// Timer enabled
-if (!old_ctl.enable && new_ctl.enable)
+// Timer unmasked or enabled
+if ((old_ctl.imask && !new_ctl.imask) ||
+(!old_ctl.enable && new_ctl.enable))
updateCounter();
-// Timer disabled
-else if (old_ctl.enable && !new_ctl.enable) {
+// Timer masked or disabled
+else if ((!old_ctl.imask && new_ctl.imask) ||
+ (old_ctl.enable && !new_ctl.enable)) {
if (_control.istatus) {
DPRINTF(Timer, "Clearing interrupt\n");
_interrupt->clear();
--
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Gerrit-Change-Id: I75e8253bb78d15ae72cb985ed132f896d8e92ca6
Gerrit-Change-Number: 30918
Gerrit-PatchSet: 7
Gerrit-Owner: Hsuan Hsu
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Hsuan Hsu
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Make generic timer work with level-sensitive support
Hsuan Hsu has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30916 )
Change subject: dev-arm: Make generic timer work with level-sensitive
support
..
dev-arm: Make generic timer work with level-sensitive support
Support for level-sensitive PPIs and SPIs has been added to GICv2 now.
It is therefore the timer's responsibility to notify GICv2 to clear its
interrupt pending state. Without doing this, the guest will get stuck
in just a single round of the interrupt handler because GICv2 does not
clear the pending state, and eventually make the guest treat this
interrupt as problematic and then just disable it.
JIRA: https://gem5.atlassian.net/browse/GEM5-663
Change-Id: Ia8fd96bf00b28e91aa440274e6f8bb000446fbe3
Signed-off-by: Hsuan Hsu
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30916
Reviewed-by: Giacomo Travaglini
Reviewed-by: Andreas Sandberg
Maintainer: Giacomo Travaglini
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/generic_timer.cc
1 file changed, 12 insertions(+), 3 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 1b75728..42b03ad 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -281,7 +281,11 @@
if (value() >= _counterLimit) {
counterLimitReached();
} else {
-_control.istatus = 0;
+if (_control.istatus) {
+DPRINTF(Timer, "Clearing interrupt\n");
+_interrupt->clear();
+_control.istatus = 0;
+}
if (scheduleEvents()) {
_parent.schedule(_counterLimitReachedEvent,
whenValue(_counterLimit));
@@ -313,8 +317,13 @@
if (!old_ctl.enable && new_ctl.enable)
updateCounter();
// Timer disabled
-else if (old_ctl.enable && !new_ctl.enable)
-_control.istatus = 0;
+else if (old_ctl.enable && !new_ctl.enable) {
+if (_control.istatus) {
+DPRINTF(Timer, "Clearing interrupt\n");
+_interrupt->clear();
+_control.istatus = 0;
+}
+}
}
void
--
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Gerrit-Change-Id: Ia8fd96bf00b28e91aa440274e6f8bb000446fbe3
Gerrit-Change-Number: 30916
Gerrit-PatchSet: 7
Gerrit-Owner: Hsuan Hsu
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Hsuan Hsu
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove m5ops_base declaration from ArmSystem
Hsuan Hsu has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/30914 ) Change subject: arch-arm: Remove m5ops_base declaration from ArmSystem .. arch-arm: Remove m5ops_base declaration from ArmSystem This declaration should have been removed but was accidentally re-added. It keeps m5ops_base from being passed correctly from Python to C++ when using ARM ISA, and hence triggers gem5 crash when the guest tries to call m5ops. This change removes it again to fix the crash. JIRA: https://gem5.atlassian.net/browse/GEM5-658 Change-Id: I8df4ff19ecc0d64255f24dc991f71b065d2a894e Signed-off-by: Hsuan Hsu Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30914 Reviewed-by: Gabe Black Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- M src/arch/arm/ArmSystem.py 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: Andreas Sandberg: Looks good to me, approved; Looks good to me, approved Gabe Black: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 6555ea9..c4cc51f 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -79,10 +79,6 @@ semihosting = Param.ArmSemihosting(NULL, "Enable support for the Arm semihosting by settings this parameter") -m5ops_base = Param.Addr(0, -"Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 " -"to disable.") - # Set to true if simulation provides a PSCI implementation # This flag will be checked when auto-generating # a PSCI node. A client (e.g Linux) would then be able to -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30914 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8df4ff19ecc0d64255f24dc991f71b065d2a894e Gerrit-Change-Number: 30914 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan Hsu Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Hsuan Hsu Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove m5ops_base declaration from ArmSystem
Hsuan Hsu has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/30914 ) Change subject: arch-arm: Remove m5ops_base declaration from ArmSystem .. arch-arm: Remove m5ops_base declaration from ArmSystem This declaration should have been removed but was accidentally re-added. It keeps m5ops_base from being passed correctly from Python to C++ when using ARM ISA, and hence triggers gem5 crash when the guest tries to call m5ops. This change removes it again to fix the crash. JIRA: https://gem5.atlassian.net/browse/GEM5-658 Change-Id: I8df4ff19ecc0d64255f24dc991f71b065d2a894e Signed-off-by: Hsuan Hsu --- M src/arch/arm/ArmSystem.py 1 file changed, 0 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 6555ea9..c4cc51f 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -79,10 +79,6 @@ semihosting = Param.ArmSemihosting(NULL, "Enable support for the Arm semihosting by settings this parameter") -m5ops_base = Param.Addr(0, -"Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 " -"to disable.") - # Set to true if simulation provides a PSCI implementation # This flag will be checked when auto-generating # a PSCI node. A client (e.g Linux) would then be able to -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30914 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8df4ff19ecc0d64255f24dc991f71b065d2a894e Gerrit-Change-Number: 30914 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan Hsu Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: cpu: Don't assert on branch target addresses
Hsuan Hsu has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28347 )
Change subject: cpu: Don't assert on branch target addresses
..
cpu: Don't assert on branch target addresses
We should assume a branch target can be any address.
JIRA: https://gem5.atlassian.net/browse/GEM5-483
Change-Id: I6f6da1f9260d6e8978536967dc7fcf1808965db2
Signed-off-by: Hsuan Hsu
Signed-off-by: Howard Wang
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28347
Reviewed-by: Trivikram Reddy
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/pred/ltage.cc
M src/cpu/pred/multiperspective_perceptron.cc
M src/cpu/pred/multiperspective_perceptron_tage.cc
M src/cpu/pred/tage.cc
M src/cpu/pred/tage_sc_l.cc
5 files changed, 0 insertions(+), 9 deletions(-)
Approvals:
Trivikram Reddy: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/pred/ltage.cc b/src/cpu/pred/ltage.cc
index a2cc56a..68a6db7 100644
--- a/src/cpu/pred/ltage.cc
+++ b/src/cpu/pred/ltage.cc
@@ -95,8 +95,6 @@
LTageBranchInfo* bi = static_cast(bp_history);
-assert(corrTarget != MaxAddr);
-
if (squashed) {
if (tage->isSpeculativeUpdateEnabled()) {
// This restores the global history, then update it
diff --git a/src/cpu/pred/multiperspective_perceptron.cc
b/src/cpu/pred/multiperspective_perceptron.cc
index d081b49..6582197 100644
--- a/src/cpu/pred/multiperspective_perceptron.cc
+++ b/src/cpu/pred/multiperspective_perceptron.cc
@@ -613,7 +613,6 @@
{
assert(bp_history);
MPPBranchInfo *bi = static_cast(bp_history);
-assert(corrTarget != MaxAddr);
if (squashed) {
//delete bi;
return;
diff --git a/src/cpu/pred/multiperspective_perceptron_tage.cc
b/src/cpu/pred/multiperspective_perceptron_tage.cc
index 3ef5f4f..a54f37c 100644
--- a/src/cpu/pred/multiperspective_perceptron_tage.cc
+++ b/src/cpu/pred/multiperspective_perceptron_tage.cc
@@ -605,8 +605,6 @@
assert(bp_history);
MPPTAGEBranchInfo *bi = static_cast(bp_history);
-assert(corrTarget != MaxAddr);
-
if (squashed) {
if (tage->isSpeculativeUpdateEnabled()) {
// This restores the global history, then update it
diff --git a/src/cpu/pred/tage.cc b/src/cpu/pred/tage.cc
index 7906532..d7c50f0 100644
--- a/src/cpu/pred/tage.cc
+++ b/src/cpu/pred/tage.cc
@@ -58,8 +58,6 @@
TageBranchInfo *bi = static_cast(bp_history);
TAGEBase::BranchInfo *tage_bi = bi->tageBranchInfo;
-assert(corrTarget != MaxAddr);
-
if (squashed) {
// This restores the global history, then update it
// and recomputes the folded histories.
diff --git a/src/cpu/pred/tage_sc_l.cc b/src/cpu/pred/tage_sc_l.cc
index de7c2f2..cbd9a45 100644
--- a/src/cpu/pred/tage_sc_l.cc
+++ b/src/cpu/pred/tage_sc_l.cc
@@ -419,8 +419,6 @@
TAGE_SC_L_TAGE::BranchInfo* tage_bi =
static_cast(bi->tageBranchInfo);
-assert(corrTarget != MaxAddr);
-
if (squashed) {
if (tage->isSpeculativeUpdateEnabled()) {
// This restores the global history, then update it
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6f6da1f9260d6e8978536967dc7fcf1808965db2
Gerrit-Change-Number: 28347
Gerrit-PatchSet: 5
Gerrit-Owner: Hsuan Hsu
Gerrit-Reviewer: Hsuan Hsu
Gerrit-Reviewer: Jairo Balart
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Pau Cabre
Gerrit-Reviewer: Trivikram Reddy
Gerrit-Reviewer: kokoro
Gerrit-CC: Ciro Santilli
Gerrit-CC: Giacomo Travaglini
Gerrit-CC: Nikos Nikoleris
Gerrit-MessageType: merged
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