[gem5-dev] Change in gem5/gem5[develop]: cpu: Remove "lane" accessors from the ExecContext classes.

2021-03-04 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41897 )


Change subject: cpu: Remove "lane" accessors from the ExecContext classes.
..

cpu: Remove "lane" accessors from the ExecContext classes.

These are not used by instructions. If something other than instructions
needs that style of access, it would use the ThreadContext, not the
ExecContext.

Change-Id: Ic74dcfd34f8bb0786bd2688b44d0d90714503637
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41897
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/simple/exec_context.hh
5 files changed, 0 insertions(+), 316 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 42a38fc..0900125 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -218,79 +218,6 @@
 return thread->getWritableVecReg(reg);
 }

-/** Vector Register Lane Interfaces. */
-/** @{ */
-/** Reads source vector 8bit operand. */
-virtual ConstVecLane8
-readVec8BitLaneOperand(const StaticInst *si, int idx) const override
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->readVec8BitLaneReg(reg);
-}
-
-/** Reads source vector 16bit operand. */
-virtual ConstVecLane16
-readVec16BitLaneOperand(const StaticInst *si, int idx) const override
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->readVec16BitLaneReg(reg);
-}
-
-/** Reads source vector 32bit operand. */
-virtual ConstVecLane32
-readVec32BitLaneOperand(const StaticInst *si, int idx) const override
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->readVec32BitLaneReg(reg);
-}
-
-/** Reads source vector 64bit operand. */
-virtual ConstVecLane64
-readVec64BitLaneOperand(const StaticInst *si, int idx) const override
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->readVec64BitLaneReg(reg);
-}
-
-/** Write a lane of the destination vector operand. */
-template 
-void
-setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->setVecLane(reg, val);
-}
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{
-setVecLaneOperandT(si, idx, val);
-}
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{
-setVecLaneOperandT(si, idx, val);
-}
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{
-setVecLaneOperandT(si, idx, val);
-}
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{
-setVecLaneOperandT(si, idx, val);
-}
-/** @} */
-
 TheISA::VecElem
 readVecElemOperand(const StaticInst *si, int idx) const override
 {
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 42dafbc..3c40f31 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -117,36 +117,6 @@
 const TheISA::VecRegContainer& val) = 0;
 /** @} */

-/** Vector Register Lane Interfaces. */
-/** @{ */
-/** Reads source vector 8bit operand. */
-virtual ConstVecLane8 readVec8BitLaneOperand(
-const StaticInst *si, int idx) const = 0;
-
-/** Reads source vector 16bit operand. */
-virtual ConstVecLane16 readVec16BitLaneOperand(
-const StaticInst *si, int idx) const = 0;
-
-/** Reads source vector 32bit operand. */
-virtual ConstVecLane32 readVec32BitLaneOperand(
-const StaticInst *si, int idx) const = 0;
-
-/** Reads source vector 64bit operand. */
-virtual ConstVecLane64 readVec64BitLaneOperand(
-const StaticInst *si, int idx) const = 0;
-
-/** Write a lane of the destination vector operand. */
-/** @{ */
-virtual void setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) = 0;
-virtual void setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) = 0;
-virtual void setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) 

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Switch the AAPCS ABIs to .as<>() instead of .laneView<>().

2021-03-04 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41898 )


Change subject: arch-arm: Switch the AAPCS ABIs to .as<>() instead  
of .laneView<>().

..

arch-arm: Switch the AAPCS ABIs to .as<>() instead of .laneView<>().

Change-Id: I9e9c7163db4c061af00111b8dc959c364c6b7ae6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41898
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/aapcs32.hh
M src/arch/arm/aapcs64.hh
2 files changed, 6 insertions(+), 6 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index a1345bd..c450237 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -463,7 +463,7 @@

 RegId id(VecRegClass, 0);
 auto reg = tc->readVecReg(id);
-reg.laneView() = f;
+reg.as()[0] = f;
 tc->setVecReg(id, reg);
 };
 };
@@ -487,7 +487,7 @@

 RegId id(VecRegClass, reg);
 auto val = tc->readVecReg(id);
-return val.laneView(lane);
+return val.as()[lane];
 }

 return loadFromStack(tc, state);
@@ -558,7 +558,7 @@

 RegId id(VecRegClass, reg);
 auto val = tc->readVecReg(id);
-ha[i] = val.laneView(lane);
+ha[i] = val.as()[lane];
 }
 return ha;
 }
@@ -605,7 +605,7 @@

 RegId id(VecRegClass, reg);
 auto val = tc->readVecReg(id);
-val.laneView(lane) = ha[i];
+val.as()[lane] = ha[i];
 tc->setVecReg(id, val);
 }
 }
diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index fb7b8f8..ddd5606 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -186,7 +186,7 @@
 {
 if (state.nsrn <= state.MAX_SRN) {
 RegId id(VecRegClass, state.nsrn++);
-return tc->readVecReg(id).laneView();
+return tc->readVecReg(id).as()[0];
 }

 return loadFromStack(tc, state);
@@ -203,7 +203,7 @@
 {
 RegId id(VecRegClass, 0);
 auto reg = tc->readVecReg(id);
-reg.laneView() = f;
+reg.as()[0] = f;
 tc->setVecReg(id, reg);
 }
 };

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9e9c7163db4c061af00111b8dc959c364c6b7ae6
Gerrit-Change-Number: 41898
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Simplify some code in the guest ABI mechanism.

2021-03-04 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41600 )


Change subject: sim: Simplify some code in the guest ABI mechanism.
..

sim: Simplify some code in the guest ABI mechanism.

Instead of using recursively applied templates to accumulate a series of
wrapper lambdas which dispatch to a call, use pure parameter pack
expansion. This has two benefits. One, it makes the code simpler(ish) and
easier to understand. The parameter pack machinery is still intrinsically
fairly tricky, but there's less of it and it's a fairly straightforward
application of that mechanism.

Also, a nice side benefit is that the template for simcall dispatch will
expand to a small fixed number of functions which do all their work
locally, instead of having a new function for each layer of the onion,
one per parameter, and no calls through lambdas. That should hopefully
make debugging easier, and produce less bookkeeping overhead as far as
really long names, lots of functions, etc.

This code, specifically the code in dispatch.hh, can be simplified even
further in the future once we start using c++17 which is if constexpr,
and std::apply which explodes a tuple and uses its components as
arguments to a function, something I'm doing manually here.

Change-Id: If7c9234cc1014101211474c2ec20362702cf78c2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41600
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/sim/guest_abi.hh
M src/sim/guest_abi/dispatch.hh
M src/sim/guest_abi/layout.hh
3 files changed, 48 insertions(+), 112 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/guest_abi.hh b/src/sim/guest_abi.hh
index ea3325f..75c4e00 100644
--- a/src/sim/guest_abi.hh
+++ b/src/sim/guest_abi.hh
@@ -51,7 +51,7 @@
 // types will be zero initialized.
 auto state = GuestABI::initializeState(tc);
 GuestABI::prepareForFunction(tc, state);
-return GuestABI::callFrom(tc, state,  
target);
+return GuestABI::callFrom(tc, state,  
target);

 }

 template 
@@ -86,7 +86,7 @@
 // types will be zero initialized.
 auto state = GuestABI::initializeState(tc);
 GuestABI::prepareForArguments(tc, state);
-GuestABI::callFrom(tc, state, target);
+GuestABI::callFrom(tc, state, target);
 }

 template 
@@ -113,7 +113,7 @@

 GuestABI::prepareForFunction(tc, state);
 ss << name;
-GuestABI::dumpArgsFrom(0, ss, tc, state);
+GuestABI::dumpArgsFrom(ss, tc, state);
 return ss.str();
 }

diff --git a/src/sim/guest_abi/dispatch.hh b/src/sim/guest_abi/dispatch.hh
index bc365b9..8f3a4ac 100644
--- a/src/sim/guest_abi/dispatch.hh
+++ b/src/sim/guest_abi/dispatch.hh
@@ -30,8 +30,11 @@

 #include 
 #include 
+#include 
 #include 
+#include 

+#include "base/compiler.hh"
 #include "sim/guest_abi/definition.hh"
 #include "sim/guest_abi/layout.hh"

@@ -50,114 +53,60 @@
  * still possible to support by redefining these functions..
  */

-// With no arguments to gather, call the target function and store the
-// result.
-template 
-static typename std::enable_if_t::value && store_ret,  
Ret>

-callFrom(ThreadContext *tc, typename ABI::State ,
-std::function target)
+template 
+static inline typename std::enable_if_t
+callFromHelper(Target , ThreadContext *tc, State , Args  
&,

+std::index_sequence)
 {
-Ret ret = target(tc);
+return target(tc, std::get(args)...);
+}
+
+template 
+static inline typename std::enable_if_t
+callFromHelper(Target , ThreadContext *tc, State , Args  
&,

+std::index_sequence)
+{
+Ret ret = target(tc, std::get(args)...);
 storeResult(tc, ret, state);
 return ret;
 }

-template 
-static typename std::enable_if_t::value && !store_ret,  
Ret>

+template 
+static inline Ret
 callFrom(ThreadContext *tc, typename ABI::State ,
-std::function target)
+std::function target)
 {
-return target(tc);
+// Extract all the arguments from the thread context. Braced  
initializers

+// are evaluated from left to right.
+auto args = std::tuple{getArgument(tc, state)...};
+
+// Call the wrapper which will call target.
+return callFromHelper(
+target, tc, state, std::move(args),
+std::make_index_sequence{});
 }

-// With no arguments to gather and nothing to return, call the target  
function.

-template 
-static void
-callFrom(ThreadContext *tc, typename ABI::State ,
-std::function target)
-{
-target(tc);
-}
-
-// Recursively gather arguments for target from tc until we get to the base
-// case above.
-template 
-static typename std::enable_if_t::value, Ret>
-callFrom(ThreadContext *tc, typename ABI::State ,
-std::function target)
-{
-// Extract the next argume

[gem5-dev] Change in gem5/gem5[develop]: base: Add a macro to expand parameter pack expressions in order.

2021-03-04 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42033 )


Change subject: base: Add a macro to expand parameter pack expressions in  
order.

..

base: Add a macro to expand parameter pack expressions in order.

This wraps up the strange compiler goop necessary to evaluate
expressions based on parameter pack expansions in order.

Change-Id: I16fbd53d22492a8c20524e3ef8bb8ff5e5d59b14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42033
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/base/compiler.hh
1 file changed, 10 insertions(+), 0 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/compiler.hh b/src/base/compiler.hh
index 643352c..c003bfa 100644
--- a/src/base/compiler.hh
+++ b/src/base/compiler.hh
@@ -112,6 +112,16 @@
 // we can't do that with direct substitution.
 #  define M5_LIKELY(cond) __builtin_expect(!!(cond), 1)
 #  define M5_UNLIKELY(cond) __builtin_expect(!!(cond), 0)
+
+// Evaluate an expanded parameter pack in order. Multiple arguments can be
+// passed in which be evaluated in order relative to each other as a group.
+// The argument(s) must include a parameter pack to expand. This works  
because
+// the elements of a brace inclosed initializer list are evaluated in  
order,

+// as are the arguments to the comma operator, which evaluates to the last
+// value. This is compiler specific because it uses variadic macros.
+#define M5_FOR_EACH_IN_PACK(...) \
+do { M5_VAR_USED int i[] = { 0, ((void)(__VA_ARGS__), 0)... }; } while  
(false)

+
 #else
 #  error "Don't know what to do for your compiler."
 #endif

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I16fbd53d22492a8c20524e3ef8bb8ff5e5d59b14
Gerrit-Change-Number: 42033
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Style fixes in the base and O3 dynamic inst classes.

2021-03-04 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42093 )


Change subject: cpu: Style fixes in the base and O3 dynamic inst classes.
..

cpu: Style fixes in the base and O3 dynamic inst classes.

Change-Id: Idfd8e71856931fa101e00c58a2aa4018d076
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42093
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/cpu/base_dyn_inst.hh
M src/cpu/o3/dyn_inst.hh
2 files changed, 27 insertions(+), 20 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 68a6bb3..a5a842a 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -729,8 +729,11 @@
 OpClass opClass() const { return staticInst->opClass(); }

 /** Returns the branch target address. */
-TheISA::PCState branchTarget() const
-{ return staticInst->branchTarget(pc); }
+TheISA::PCState
+branchTarget() const
+{
+return staticInst->branchTarget(pc);
+}

 /** Returns the number of source registers. */
 size_t numSrcRegs() const { return regs.numSrcs(); }
@@ -1016,11 +1019,15 @@

 /** Return whether dest registers' pinning status updated after squash  
*/

 bool
-isPinnedRegsSquashDone() const { return status[PinnedRegsSquashDone]; }
+isPinnedRegsSquashDone() const
+{
+return status[PinnedRegsSquashDone];
+}

 /** Sets dest registers' status updated after squash */
 void
-setPinnedRegsSquashDone() {
+setPinnedRegsSquashDone()
+{
 assert(!status[PinnedRegsSquashDone]);
 status.set(PinnedRegsSquashDone);
 }
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index f084368..7a54c7f 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -184,37 +184,37 @@
 this->thread->noSquashFromTC = no_squash_from_TC;
 }

-void forwardOldRegs()
+void
+forwardOldRegs()
 {

 for (int idx = 0; idx < this->numDestRegs(); idx++) {
 PhysRegIdPtr prev_phys_reg = this->regs.prevDestIdx(idx);
-const RegId& original_dest_reg =
-this->staticInst->destRegIdx(idx);
+const RegId& original_dest_reg =  
this->staticInst->destRegIdx(idx);

 switch (original_dest_reg.classValue()) {
   case IntRegClass:
 this->setIntRegOperand(this->staticInst.get(), idx,
-   this->cpu->readIntReg(prev_phys_reg));
+this->cpu->readIntReg(prev_phys_reg));
 break;
   case FloatRegClass:
 this->setFloatRegOperandBits(this->staticInst.get(), idx,
-   this->cpu->readFloatReg(prev_phys_reg));
+this->cpu->readFloatReg(prev_phys_reg));
 break;
   case VecRegClass:
 this->setVecRegOperand(this->staticInst.get(), idx,
-   this->cpu->readVecReg(prev_phys_reg));
+this->cpu->readVecReg(prev_phys_reg));
 break;
   case VecElemClass:
 this->setVecElemOperand(this->staticInst.get(), idx,
-   this->cpu->readVecElem(prev_phys_reg));
+this->cpu->readVecElem(prev_phys_reg));
 break;
   case VecPredRegClass:
 this->setVecPredRegOperand(this->staticInst.get(), idx,
-   this->cpu->readVecPredReg(prev_phys_reg));
+this->cpu->readVecPredReg(prev_phys_reg));
 break;
   case CCRegClass:
 this->setCCRegOperand(this->staticInst.get(), idx,
-   this->cpu->readCCReg(prev_phys_reg));
+this->cpu->readCCReg(prev_phys_reg));
 break;
   case MiscRegClass:
 // no need to forward misc reg values
@@ -309,25 +309,25 @@
 {
 return cpu->template setVecLane(this->regs.renamedDestIdx(idx),  
val);

 }
-virtual void
+void
 setVecLaneOperand(const StaticInst *si, int idx,
 const LaneData& val) override
 {
 return setVecLaneOperandT(si, idx, val);
 }
-virtual void
+void
 setVecLaneOperand(const StaticInst *si, int idx,
 const LaneData& val) override
 {
 return setVecLaneOperandT(si, idx, val);
 }
-virtual void
+void
 setVecLaneOperand(const StaticInst *si, int idx,
 const La

[gem5-dev] Change in gem5/gem5[develop]: cpu: Delete the cpu/o3/isa_specific.hh header.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42221 )



Change subject: cpu: Delete the cpu/o3/isa_specific.hh header.
..

cpu: Delete the cpu/o3/isa_specific.hh header.

This header has no contents and serves no purpose.

Change-Id: I574a4bb248f09ab94c38eebe18a9285dae6604db
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/fetch.cc
D src/cpu/o3/isa_specific.hh
M src/cpu/o3/thread_context.hh
5 files changed, 2 insertions(+), 34 deletions(-)



diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index f027dea..5f9d32c 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -47,7 +47,6 @@
 #include "cpu/activity.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/checker/thread_context.hh"
-#include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/thread_context.hh"
 #include "cpu/simple_thread.hh"
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index de1fe2f..3a397db 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -58,7 +58,6 @@
 #include "cpu/inst_seq.hh"
 #include "cpu/o3/cpu.hh"
 #include "cpu/o3/dyn_inst_ptr.hh"
-#include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/lsq_unit.hh"
 #include "cpu/op_class.hh"
 #include "cpu/reg_class.hh"
diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc
index a8dbecc..33f52c6 100644
--- a/src/cpu/o3/fetch.cc
+++ b/src/cpu/o3/fetch.cc
@@ -55,7 +55,7 @@
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/o3/cpu.hh"
-#include "cpu/o3/isa_specific.hh"
+#include "cpu/o3/dyn_inst.hh"
 #include "cpu/o3/limits.hh"
 #include "debug/Activity.hh"
 #include "debug/Drain.hh"
diff --git a/src/cpu/o3/isa_specific.hh b/src/cpu/o3/isa_specific.hh
deleted file mode 100644
index a5b5710..000
--- a/src/cpu/o3/isa_specific.hh
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "cpu/base.hh"
-#include "cpu/o3/dyn_inst.hh"
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index e1a56ee..b64185f 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -43,7 +43,7 @@
 #define __CPU_O3_THREAD_CONTEXT_HH__

 #include "config/the_isa.hh"
-#include "cpu/o3/isa_specific.hh"
+#include "cpu/o3/cpu.hh"
 #include "cpu/thread_context.hh"

 namespace O3

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I574a4bb248f09ab94c38eebe18a9285dae6604db
Gerrit-Change-Number: 42221
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base,tests: Add a stringstream which tracks all log output.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42181 )



Change subject: base,tests: Add a stringstream which tracks all log output.
..

base,tests: Add a stringstream which tracks all log output.

Since gtest's SUCCEED() just throws away output sent to it, there needs
to be an alternative way to capture non-fatal warn, hack, or inform
messages. This change adds a stringstream called gtestLogOutput which
will accumulate all log messages so they can be inspected later. If you
want to see what output occurs as a result of a specific action, you can
flush out the stringstream with .str(""), perform that action, and then
check the stream's contents.

The stream also records the output of exiting logs like fatal and panic.
It's not 100% clear that these messages would be retrievable or useful,
but this at least maintains consistency between the two classes of
messages.

Change-Id: I9d6650feb77b676a5b2b1fc2542cdebf3c60ed34
---
M src/base/gtest/logging.cc
A src/base/gtest/logging.hh
2 files changed, 41 insertions(+), 1 deletion(-)



diff --git a/src/base/gtest/logging.cc b/src/base/gtest/logging.cc
index d9cb9eb..7a7dfc2 100644
--- a/src/base/gtest/logging.cc
+++ b/src/base/gtest/logging.cc
@@ -25,6 +25,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

+#include "base/gtest/logging.hh"
+
 #include 

 #include 
@@ -33,6 +35,8 @@
 #include "base/cprintf.hh"
 #include "base/logging.hh"

+std::ostringstream gtestLogOutput;
+
 namespace {

 // This custom exception type will help prevent fatal exceptions from being
@@ -49,7 +53,12 @@
 using Logger::Logger;

   protected:
-void log(const Loc , std::string s) override { SUCCEED() << s; }
+void
+log(const Loc , std::string s) override
+{
+gtestLogOutput << s;
+SUCCEED() << s;
+}
 };

 class GTestExitLogger : public Logger
@@ -61,6 +70,7 @@
 void
 log(const Loc , std::string s) override
 {
+gtestLogOutput << s;
 std::cerr << loc.file << ":" << loc.line << ": " << s;
 }
 // Throw an exception to escape down to the gtest framework.
diff --git a/src/base/gtest/logging.hh b/src/base/gtest/logging.hh
new file mode 100644
index 000..e760884
--- /dev/null
+++ b/src/base/gtest/logging.hh
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2020 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+extern std::ostringstream gtestLogOutput;

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9d6650feb77b676a5b2b1fc2542cdebf3c60ed34
Gerrit-Change-Number: 42181
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Re: vector register indexing modes and renaming?

2021-03-03 Thread Gabe Black via gem5-dev
On Mon, Mar 1, 2021 at 6:48 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

>
> > -Original Message-
> > From: Gabe Black 
> > Sent: 27 February 2021 05:47
> > To: Giacomo Travaglini 
> > Cc: gem5 Developer List 
> > Subject: Re: [gem5-dev] vector register indexing modes and renaming?
> >
> > Another question/clarification:
> >
> > Does any data actually get shared between the two rename modes? I think
> you
> > said there is not, but now I can't find that.
>
> Data *do* get shared, even if in gem5 we have separate physical registers.
> In fact, when rename mode changes [1], (meta)data is copied from one
> register file to the other.
> For example, say we have an AArch64 kernel running at EL1 and my AArch32
> (basically armv7) floating point application running at EL0.
>
> My application will be using vector elements; however, every time there is
> an exception to AArch64, cpu will switch
> Rename mode and data will be copied / mapping will be adjusted. Any FP &
> SIMD operation at this point will use vector registers.
> When the kernel finishes its stuff, and goes back to AArch32, vector
> elements will be repopulated.
>


Ok, I thought that was what you said, and I couldn't think of another
reason to go through all the trouble of copying things around.



>
> > Would it work just as well to have
> > two register files which operate entirely independently?
>
> As I mentioned before, they operate independently, but they sync up when
> we pass from one mode
> To the other. Another way to look at it is that they are mutually
> exclusive.
>


Would it make sense to trigger the syncing between them explicitly from ARM
code, rather than forcing the O3 to notice and do the copying? Then the
copying, etc, wouldn't have to be generic, since it would be triggered by
an ARM architectural mechanism.



>
> > From what I can tell
> > the "V" registers of Neon in aarch64 overlap with the SVE registers, and
> the "Q"
> > registers of armv7 Neon overlap with the "S", "D", "Q" registers of the
> same,
> > but I think "V" and "Q" are independent? Maybe reused but not guaranteed
> to
> > alias?
> >
>
> I would say the rule of thumb for understanding AArch64-AArch32 mapping
> (and it's the underlying cause of using different renaming modes) is to
> bear in mind that AArch64, differently from AArch32, uses an unpacked
> approach for FP & SIMD registers.
> Prior to Armv8, smaller FP registers were packed into bigger registers
> [2]. Having for example 32 double precision registers (D0-D31) meant having
> a maximum of 16 quad word registers (Q0-Q15).
> This setup has been abandoned in Armv8 [3]. As an example, S1, or D1 are
> not packed anymore in Q0. Those are in fact the 32/64 LSBits of Q1.
> This means the newly added (V16-V31) are not accessible in AArch32.
>
> So to answer your question regarding V and Q. Until Q/V15, they alias
> perfectly; V16-V31 are simply not
> Defined/accessible in AArch32 so they are not aliased.
>
> All AArch32 SIMD data is accessible from AArch64. It just won't stick to
> the same naming. AArch32 D1 and AArch64 D1 hold different data.
> If I really wanted to access AArch32 D1 from AArch64 I would have to read
> the 64 MSB of V0. This is a software and not an hardware problem (I just
> posted this example to stress the difference between aliasing and
> reachability)
>


Gotcha, makes sense.


> Richard kindly pointed me to the following SVE tutorial:
>
> https://gitlab.com/arm-hpc/training/arm-sve-tools
>
> But I believe it is worth noting we are actually interested on testing
> armv7 (AArch32) SIMD as well, so that won't probably be enough.
> I will dig more, and I will keep you posted
>

Ok great, I'll take a look. Having *something* to test with will be a big
leg up, even if it isn't complete. It would also be nice, although more
complex, to be able to test the rename mode switching mechanism somehow.

Gabe
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[gem5-dev] Re: RFC: run python Black on gem5 python code

2021-03-03 Thread Gabe Black via gem5-dev
I'm a little worried about the no exceptions part of that, since we might
have some weird restrictions that we have to do weird things to work
around, but I can't really think of an example of that off hand. I'd want
to look at it to see how much wiggle room there is in the style, since I
think ironclad rules which make no accommodation for occasional common
sense are maybe more trouble than they're worth. I'm not opposed to having
at least some stated standard for python though, and the "official" one
seems like a pretty reasonable choice. I guess it's fine with me, up until
it causes me some sort of problem :-)

Maybe the right thing to do would be to give it a shot but not make it
compulsory until we have a feeling for how much trouble it is.

Gabe

On Wed, Mar 3, 2021 at 11:24 AM Bobby Bruce via gem5-dev 
wrote:

> Sounds like a good idea to me.
> ---
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Wed, Mar 3, 2021 at 10:11 AM Daniel Carvalho via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
>> +1
>>
>> Em quarta-feira, 3 de março de 2021 14:35:57 BRT, Jason Lowe-Power via
>> gem5-dev  escreveu:
>>
>>
>> Hi all,
>>
>> Right now, we don't have an official style guide for python. Our style
>> guide (
>> http://www.gem5.org/documentation/general_docs/development/coding_style/)
>> is very C++ focused.
>>
>> I would like to propose adopting a relatively strict PEP 8 style guide:
>> https://www.python.org/dev/peps/pep-0008. This is the "official" style
>> guide for python (as much as there is anything official). I say "relatively
>> strict" to mean that we will limit our exceptions *as much as possible*.
>>
>> To implement this, Andreas S. recently pointed me to the "Black" package (
>> https://pypi.org/project/black/) which automatically fixes code style. I
>> just tried it out with gem5art (patch coming soon) and found that it works
>> really well. The only downside is that it's not configurable at all. Adding
>> special cases would be almost impossible.
>>
>> Concrete and specific proposal:
>> - Adopt PEP 8 as our official style guide
>> - Use black to reformat all python code in src/
>> - Use black to reformat code in configs/
>> - Use black to reformat other python code
>> - Use black as part of our commit hook to make sure all future python is
>> formatted to PEP 8
>>
>> Let me know what you think!
>>
>> Cheers,
>> Jason
>> ___
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Consolidate defintions of vectorReg operands.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41896 )


Change subject: arch-arm: Consolidate defintions of vectorReg operands.
..

arch-arm: Consolidate defintions of vectorReg operands.

Each vectorReg operand defined a set of seven elements which all
followed a very predictable pattern. Since we already have a small
utility function to help generate those definitions, we can just
generate the elements at the same time and save a lot of boilerplate.

Change-Id: I065c6c319612b79c53570b313bf5ad8770796252
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41896
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/isa/operands.isa
1 file changed, 36 insertions(+), 278 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index da78561..f50144e 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -128,11 +128,17 @@
 def vectorElem(idx, elem):
 return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)

-def vectorReg(idx, elems = None):
-return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
-
-def vectorRegElem(elem, ext = 'sf'):
-return (elem, ext)
+def vectorReg(idx, base, suffix = ''):
+elems = {
+base + 'P0' + suffix : ('0', 'sf'),
+base + 'P1' + suffix : ('1', 'sf'),
+base + 'P2' + suffix : ('2', 'sf'),
+base + 'P3' + suffix : ('3', 'sf'),
+base + 'S' + suffix : ('0', 'sf'),
+base + 'D' + suffix : ('0', 'df'),
+base + 'Q' + suffix : ('0', 'tud')
+}
+return ('VecReg', 'vc', (idx, elems), 'IsVector', srtNormal)

 def vecPredReg(idx):
 return ('VecPredReg', 'pc', idx, None, srtNormal)
@@ -348,281 +354,33 @@
 # All the constituents are hierarchically defined as part of the Vector
 # Register they belong to

-'AA64FpOp1':   vectorReg('op1',
-{
-'AA64FpOp1P0': vectorRegElem('0'),
-'AA64FpOp1P1': vectorRegElem('1'),
-'AA64FpOp1P2': vectorRegElem('2'),
-'AA64FpOp1P3': vectorRegElem('3'),
-'AA64FpOp1S':  vectorRegElem('0', 'sf'),
-'AA64FpOp1D':  vectorRegElem('0', 'df'),
-'AA64FpOp1Q':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp2':   vectorReg('op2',
-{
-'AA64FpOp2P0': vectorRegElem('0'),
-'AA64FpOp2P1': vectorRegElem('1'),
-'AA64FpOp2P2': vectorRegElem('2'),
-'AA64FpOp2P3': vectorRegElem('3'),
-'AA64FpOp2S':  vectorRegElem('0', 'sf'),
-'AA64FpOp2D':  vectorRegElem('0', 'df'),
-'AA64FpOp2Q':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp3':   vectorReg('op3',
-{
-'AA64FpOp3P0': vectorRegElem('0'),
-'AA64FpOp3P1': vectorRegElem('1'),
-'AA64FpOp3P2': vectorRegElem('2'),
-'AA64FpOp3P3': vectorRegElem('3'),
-'AA64FpOp3S':  vectorRegElem('0', 'sf'),
-'AA64FpOp3D':  vectorRegElem('0', 'df'),
-'AA64FpOp3Q':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpDest':   vectorReg('dest',
-{
-'AA64FpDestP0': vectorRegElem('0'),
-'AA64FpDestP1': vectorRegElem('1'),
-'AA64FpDestP2': vectorRegElem('2'),
-'AA64FpDestP3': vectorRegElem('3'),
-'AA64FpDestS':  vectorRegElem('0', 'sf'),
-'AA64FpDestD':  vectorRegElem('0', 'df'),
-'AA64FpDestQ':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpDest2':   vectorReg('dest2',
-{
-'AA64FpDest2P0': vectorRegElem('0'),
-'AA64FpDest2P1': vectorRegElem('1'),
-'AA64FpDest2P2': vectorRegElem('2'),
-'AA64FpDest2P3': vectorRegElem('3'),
-'AA64FpDest2S':  vectorRegElem('0', 'sf'),
-'AA64FpDest2D':  vectorRegElem('0', 'df'),
-'AA64FpDest2Q':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp1V0':   vectorReg('op1',
-{
-'AA64FpOp1P0V0': vectorRegElem('0'),
-'AA64FpOp1P1V0': vectorRegElem('1'),
-'AA64FpOp1P2V0': vectorRegElem('2'),
-'AA64FpOp1P3V0': vectorRegElem('3'),
-'AA64FpOp1SV0':  vectorRegElem('0', 'sf'),
-'AA64FpOp1DV0':  vectorRegElem('0', 'df'),
-'AA64FpOp1QV0':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp1V1':   vectorReg('op1+1',
-{
-'AA64FpOp1P0V1': vectorRegElem('0'),
-'AA64FpOp1P1V1': vectorRegElem('1'),
-'AA64FpOp1P2V1': vectorRegElem('2'),
-'AA64FpOp1P3V1': vectorRegElem('3'),
-'AA64FpOp1SV1':  vectorRegElem('0', 'sf'),
-'AA64FpOp1DV1':  vectorRegElem('0', 'df'),
-'AA64FpOp1QV1':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp1V2':   vectorReg('op1+2

[gem5-dev] Re: de-templating the O3 CPU

2021-03-03 Thread Gabe Black via gem5-dev
Series of 28 CLs, ends here:

https://gem5-review.googlesource.com/c/public/gem5/+/42120

On Mon, Mar 1, 2021 at 8:50 AM Jason Lowe-Power  wrote:

> Hey Gabe,
>
> I love this idea! It would be nice if you could document the code as you
> go, too. It could serve as a good learning tool in the future.
>
> Cheers,
> Jason
>
> On Mon, Mar 1, 2021 at 7:56 AM Giacomo Travaglini via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
>> +2, +1, Merged
>>
>> 
>>
>> Giacomo
>>
>> > -Original Message-
>> > From: Gabe Black via gem5-dev 
>> > Sent: 27 February 2021 10:13
>> > To: gem5 Developer List 
>> > Cc: Gabe Black 
>> > Subject: [gem5-dev] de-templating the O3 CPU
>> >
>> > Hi folks. The O3 CPU uses templates pretty heavily, I think nominally
>> to make it
>> > possible to switch in different parts of the CPU to change how, for
>> example, a
>> > pipeline stage is implemented.
>> >
>> > Realistically, the different parts of the CPU are probably too
>> interdependent
>> > for that to actually work, and all the templates and indirection make
>> the code a
>> > lot more complicated than it really needs to be.
>> >
>> > Also, there is a pseudo-generic dynamic instruction base class in
>> > cpu/base_dyn_inst.hh which could, again theoretically, be used as a
>> base class
>> > for other CPUs to reuse. Unfortunately that too is probably too tied to
>> its only
>> > consumer, the O3 CPU, to be realistically reusable.
>> >
>> > I would like to merge the base dynamic instruction class into the O3
>> version,
>> > and then de-templatize the whole O3 CPU. I think that will make the
>> code a lot
>> > easier to work on, and I think our ability to maintain and update O3 is
>> > something we need to improve in at least the medium term.
>> >
>> > Any thoughts? Objections? Votes of support?
>> >
>> > Gabe
>> IMPORTANT NOTICE: The contents of this email and any attachments are
>> confidential and may also be privileged. If you are not the intended
>> recipient, please notify the sender immediately and do not disclose the
>> contents to any other person, use it for any purpose, or store or copy the
>> information in any medium. Thank you.
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>
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[gem5-dev] Change in gem5/gem5[develop]: cpu: De-templatize the O3ThreadContext.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42115 )



Change subject: cpu: De-templatize the O3ThreadContext.
..

cpu: De-templatize the O3ThreadContext.

Change-Id: I1559760949031bd63bd3a48e62c37448c1f6f5b6
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/thread_context.cc
M src/cpu/o3/thread_context.hh
D src/cpu/o3/thread_context_impl.hh
5 files changed, 294 insertions(+), 365 deletions(-)



diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 8985262..3d9fff3 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -321,15 +321,15 @@
 ThreadContext *tc;

 // Setup the TC that will serve as the interface to the  
threads/CPU.

-O3ThreadContext *o3_tc = new O3ThreadContext;
+O3ThreadContext *o3_tc = new O3ThreadContext;

 tc = o3_tc;

 // If we're using a checker, then the TC should be the
 // CheckerThreadContext.
 if (params.checker) {
-tc = new CheckerThreadContext >(
-o3_tc, this->checker);
+tc = new CheckerThreadContext(
+o3_tc, this->checker);
 }

 o3_tc->cpu = this;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 8a6a09d..2d39cc7 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -76,7 +76,6 @@
 template 
 class Checker;
 class ThreadContext;
-template 
 class O3ThreadContext;

 class Checkpoint;
@@ -106,7 +105,7 @@

 typedef typename std::list::iterator ListIt;

-friend class O3ThreadContext;
+friend class O3ThreadContext;

   public:
 enum Status {
diff --git a/src/cpu/o3/thread_context.cc b/src/cpu/o3/thread_context.cc
index db07162..10dc1a2 100644
--- a/src/cpu/o3/thread_context.cc
+++ b/src/cpu/o3/thread_context.cc
@@ -1,4 +1,17 @@
 /*
+ * Copyright (c) 2010-2012, 2016-2017, 2019 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -28,8 +41,278 @@

 #include "cpu/o3/thread_context.hh"

-#include "cpu/o3/impl.hh"
-#include "cpu/o3/thread_context_impl.hh"
+#include "arch/generic/traits.hh"
+#include "arch/registers.hh"
+#include "config/the_isa.hh"
+#include "debug/O3CPU.hh"

-template class O3ThreadContext;
+PortProxy&
+O3ThreadContext::getVirtProxy()
+{
+return thread->getVirtProxy();
+}

+void
+O3ThreadContext::takeOverFrom(ThreadContext *old_context)
+{
+::takeOverFrom(*this, *old_context);
+
+getIsaPtr()->takeOverFrom(this, old_context);
+
+TheISA::Decoder *newDecoder = getDecoderPtr();
+TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
+newDecoder->takeOverFrom(oldDecoder);
+
+thread->funcExeInst = old_context->readFuncExeInst();
+
+thread->noSquashFromTC = false;
+thread->trapPending = false;
+}
+
+void
+O3ThreadContext::activate()
+{
+DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
+threadId());
+
+if (thread->status() == ThreadContext::Active)
+return;
+
+thread->lastActivate = curTick();
+thread->setStatus(ThreadContext::Active);
+
+// status() == Suspended
+cpu->activateContext(thread->threadId());
+}
+
+void
+O3ThreadContext::suspend()
+{
+DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
+threadId());
+
+if (thread->status() == ThreadContext::Suspended)
+return;
+
+if (cpu->isDraining()) {
+DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
+return;
+}
+
+thread->lastActivate = curTick();
+thread->lastSuspend = curTick();
+
+thread->setStatus(ThreadContext::Suspended);
+cpu->suspendContext(thread->threadId());
+}
+
+void
+O3ThreadContext::halt()
+{
+DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
+
+if (thread->status() == ThreadContext::Halting ||
+thread->status() == ThreadContext::Halted)
+return;
+
+// the thread is not going to halt/terminate immediately in this cycle.
+// The thread will be removed after an exit trap is processed
+// 

[gem5-dev] Change in gem5/gem5[develop]: cpu: De-templatize the O3ThreadState.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42118 )



Change subject: cpu: De-templatize the O3ThreadState.
..

cpu: De-templatize the O3ThreadState.

Change-Id: Ifa6342abe396e131ae8edcb8111453852cdbefd7
---
M src/cpu/o3/SConscript
M src/cpu/o3/commit.cc
M src/cpu/o3/commit.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/thread_context.hh
A src/cpu/o3/thread_state.cc
M src/cpu/o3/thread_state.hh
9 files changed, 92 insertions(+), 62 deletions(-)



diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index 62d01a1..c61c7cf 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -54,6 +54,7 @@
 Source('scoreboard.cc')
 Source('store_set.cc')
 Source('thread_context.cc')
+Source('thread_state.cc')

 DebugFlag('CommitRate')
 DebugFlag('IEW')
diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc
index ffca6ab..b1c2890 100644
--- a/src/cpu/o3/commit.cc
+++ b/src/cpu/o3/commit.cc
@@ -237,7 +237,7 @@
 }

 void
-DefaultCommit::setThreads(std::vector )
+DefaultCommit::setThreads(std::vector )
 {
 thread = threads;
 }
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index ccf6e7c..4319ed8 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -58,8 +58,7 @@

 struct DerivO3CPUParams;

-template 
-struct O3ThreadState;
+class O3ThreadState;

 /**
  * DefaultCommit handles single threaded and SMT commit. Its width is
@@ -86,8 +85,6 @@
 class DefaultCommit
 {
   public:
-typedef O3ThreadState Thread;
-
 /** Overall commit status. Used to determine if the CPU can deschedule
  * itself due to a lack of activity.
  */
@@ -136,7 +133,7 @@
 void regProbePoints();

 /** Sets the list of threads. */
-void setThreads(std::vector );
+void setThreads(std::vector );

 /** Sets the main time buffer pointer, used for backwards  
communication. */

 void setTimeBuffer(TimeBuffer *tb_ptr);
@@ -351,7 +348,7 @@
 FullO3CPU *cpu;

 /** Vector of all of the threads. */
-std::vector thread;
+std::vector thread;

 /** Records that commit has written to the time buffer this cycle.  
Used for
  * the CPU to determine if it can deschedule itself if there is no  
activity.

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 974de29..679d33d 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -290,24 +290,19 @@
 if (FullSystem) {
 // SMT is not supported in FS mode yet.
 assert(numThreads == 1);
-thread[tid] = new O3ThreadState(this, 0, NULL);
+thread[tid] = new O3ThreadState(this, 0, NULL);
 } else {
 if (tid < params.workload.size()) {
 DPRINTF(O3CPU, "Workload[%i] process is %#x", tid,
 thread[tid]);
-thread[tid] = new O3ThreadState(this, tid,
+thread[tid] = new O3ThreadState(this, tid,
 params.workload[tid]);
-
-//usedTids[tid] = true;
-//threadMap[tid] = tid;
 } else {
 //Allocate Empty thread so M5 can use later
 //when scheduling threads to CPU
 Process* dummy_proc = NULL;

-thread[tid] = new O3ThreadState(this, tid,
-dummy_proc);
-//usedTids[tid] = false;
+thread[tid] = new O3ThreadState(this, tid, dummy_proc);
 }
 }

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index e1746a8..cc4d516 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -650,7 +650,7 @@
 System *system;

 /** Pointers to all of the threads in the CPU. */
-std::vector *> thread;
+std::vector thread;

 /** Threads Scheduled to Enter CPU */
 std::list cpuWaitList;
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 252a6b7..41fafba 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -106,7 +106,7 @@
 BaseCPU *getCpuPtr() { return cpu; }

 /** Pointer to the thread state. */
-O3ThreadState *thread = nullptr;
+O3ThreadState *thread = nullptr;

 /** The kind of fault this instruction has generated. */
 Fault fault = NoFault;
@@ -1014,11 +1014,7 @@
 void setTid(ThreadID tid) { threadNumber = tid; }

 /** Sets the pointer to the thread state. */
-void
-setThreadState(O3ThreadState *state)
-{
-thread = state;
-}
+void setThreadState(O3ThreadState *state) { thread = state; }

 /** Returns the thread context. */
 ThreadContext *tcBase() const override { return thread->getTC(); }
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 245ef62..384635e 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -94,7 +94,7 @@
 

[gem5-dev] Change in gem5/gem5[develop]: cpu: Delete the now unused cpu/o3/impl.hh.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42119 )



Change subject: cpu: Delete the now unused cpu/o3/impl.hh.
..

cpu: Delete the now unused cpu/o3/impl.hh.

Change-Id: I99b6ec745066c154079c3f44086d2e8721c0ed82
---
M src/cpu/o3/checker.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/decode.hh
M src/cpu/o3/fetch.hh
D src/cpu/o3/impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/isa_specific.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/o3/probe/simple_trace.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rob.hh
M src/cpu/o3/thread_context.hh
15 files changed, 1 insertion(+), 57 deletions(-)



diff --git a/src/cpu/o3/checker.hh b/src/cpu/o3/checker.hh
index 4a2fbbc..da00798 100644
--- a/src/cpu/o3/checker.hh
+++ b/src/cpu/o3/checker.hh
@@ -43,7 +43,6 @@

 #include "cpu/checker/cpu.hh"
 #include "cpu/o3/dyn_inst.hh"
-#include "cpu/o3/impl.hh"

 /**
  * Specific non-templated derived class used for SimObject configuration.
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index cc4d516..8a30b5f 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -60,7 +60,6 @@
 #include "cpu/o3/fetch.hh"
 #include "cpu/o3/free_list.hh"
 #include "cpu/o3/iew.hh"
-#include "cpu/o3/impl.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/rename.hh"
 #include "cpu/o3/rob.hh"
diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh
index 6e70049..c45bbba 100644
--- a/src/cpu/o3/decode.hh
+++ b/src/cpu/o3/decode.hh
@@ -46,7 +46,6 @@
 #include "base/statistics.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/dyn_inst_ptr.hh"
-#include "cpu/o3/impl.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/timebuf.hh"

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index c998ceb..9df25ed 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -46,7 +46,6 @@
 #include "base/statistics.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/comm.hh"
-#include "cpu/o3/impl.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/pred/bpred_unit.hh"
diff --git a/src/cpu/o3/impl.hh b/src/cpu/o3/impl.hh
deleted file mode 100644
index b3b21e9..000
--- a/src/cpu/o3/impl.hh
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __CPU_O3_IMPL_HH__
-#define __CPU_O3_IMPL_HH__
-
-/** Implementation specific struct that defines several key types to the
- *  CPU, the stages within the CPU, the time buffers, and the DynInst.
- *  The struct defines the ISA, the CPU policy, the specific DynInst, the
- *  specific O3CPU, and all of the structs from the time buffers to do
- *  communication.
- *  This is one of the key things that must be defined for each hardware
- *  specific CPU implementation.
- */
-struct O3CPUImpl {};
-
-#endif // __CPU_O3_SPARC_IMPL_HH__
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index ab4e575..32c5a7e 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -53,7 +53,6 @@
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/dep_graph.hh"
 #include &qu

[gem5-dev] Change in gem5/gem5[develop]: cpu: Delete the unnecessary BaseO3CPU class.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42116 )



Change subject: cpu: Delete the unnecessary BaseO3CPU class.
..

cpu: Delete the unnecessary BaseO3CPU class.

This class has no content, and is not used for anything except as an
extra layer between FullO3CPU and BaseCPU.

Change-Id: Idb6258a655b0fb614e94b0fc0e281696d5081ab0
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
2 files changed, 2 insertions(+), 16 deletions(-)



diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 3d9fff3..0f172e1 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -65,14 +65,9 @@

 struct BaseCPUParams;

-BaseO3CPU::BaseO3CPU(const BaseCPUParams )
-: BaseCPU(params)
-{
-}
-
 template 
 FullO3CPU::FullO3CPU(const DerivO3CPUParams )
-: BaseO3CPU(params),
+: BaseCPU(params),
   mmu(params.mmu),
   tickEvent([this]{ tick(); }, "FullO3CPU tick",
 false, Event::CPU_Tick_Pri),
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 2d39cc7..25b9f52 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -81,22 +81,13 @@
 class Checkpoint;
 class Process;

-struct BaseCPUParams;
-
-class BaseO3CPU : public BaseCPU
-{
-//Stuff that's pretty ISA independent will go here.
-  public:
-BaseO3CPU(const BaseCPUParams );
-};
-
 /**
  * FullO3CPU class, has each of the stages (fetch through commit)
  * within it, as well as all of the time buffers between stages.  The
  * tick() function for the CPU is defined here.
  */
 template 
-class FullO3CPU : public BaseO3CPU
+class FullO3CPU : public BaseCPU
 {
   public:
 // Typedefs from the Impl here.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42116
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idb6258a655b0fb614e94b0fc0e281696d5081ab0
Gerrit-Change-Number: 42116
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu: De-templatize the O3 ROB.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42106 )



Change subject: cpu: De-templatize the O3 ROB.
..

cpu: De-templatize the O3 ROB.

Change-Id: I257d2a71be5d4254437d84a5bfa59e2e8dc6420a
---
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/rob.cc
M src/cpu/o3/rob.hh
D src/cpu/o3/rob_impl.hh
6 files changed, 513 insertions(+), 572 deletions(-)



diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 35223d6..227feb8 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -166,7 +166,7 @@
 void setRenameMap(UnifiedRenameMap rm_ptr[O3MaxThreads]);

 /** Sets pointer to the ROB. */
-void setROB(ROB *rob_ptr);
+void setROB(ROB *rob_ptr);

 /** Initializes stage by sending back the number of free entries. */
 void startupStage();
@@ -345,7 +345,7 @@

   public:
 /** ROB interface. */
-ROB *rob;
+ROB *rob;

   private:
 /** Pointer to O3CPU. */
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 8e73e39..1781416 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -318,7 +318,7 @@

 template 
 void
-DefaultCommit::setROB(ROB *rob_ptr)
+DefaultCommit::setROB(ROB *rob_ptr)
 {
 rob = rob_ptr;
 }
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index f1f2a17..879dc81 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -572,7 +572,7 @@
 UnifiedRenameMap commitRenameMap[O3MaxThreads];

 /** The re-order buffer. */
-ROB rob;
+ROB rob;

 /** Active Threads List */
 std::list activeThreads;
diff --git a/src/cpu/o3/rob.cc b/src/cpu/o3/rob.cc
index 6f1af96..5418dcf 100644
--- a/src/cpu/o3/rob.cc
+++ b/src/cpu/o3/rob.cc
@@ -1,5 +1,17 @@
 /*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -26,8 +38,497 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

-#include "cpu/o3/isa_specific.hh"
-#include "cpu/o3/rob_impl.hh"
+#include "cpu/o3/rob.hh"

-// Force instantiation of InstructionQueue.
-template class ROB;
+#include 
+
+#include "base/logging.hh"
+#include "cpu/o3/dyn_inst.hh"
+#include "cpu/o3/limits.hh"
+#include "debug/Fetch.hh"
+#include "debug/ROB.hh"
+#include "params/DerivO3CPU.hh"
+
+ROB::ROB(FullO3CPU *_cpu, const DerivO3CPUParams )
+: robPolicy(params.smtROBPolicy),
+  cpu(_cpu),
+  numEntries(params.numROBEntries),
+  squashWidth(params.squashWidth),
+  numInstsInROB(0),
+  numThreads(params.numThreads),
+  stats(_cpu)
+{
+//Figure out rob policy
+if (robPolicy == SMTQueuePolicy::Dynamic) {
+//Set Max Entries to Total ROB Capacity
+for (ThreadID tid = 0; tid < numThreads; tid++) {
+maxEntries[tid] = numEntries;
+}
+
+} else if (robPolicy == SMTQueuePolicy::Partitioned) {
+DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n");
+
+//@todo:make work if part_amt doesnt divide evenly.
+int part_amt = numEntries / numThreads;
+
+//Divide ROB up evenly
+for (ThreadID tid = 0; tid < numThreads; tid++) {
+maxEntries[tid] = part_amt;
+}
+
+} else if (robPolicy == SMTQueuePolicy::Threshold) {
+DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
+
+int threshold =  params.smtROBThreshold;;
+
+//Divide up by threshold amount
+for (ThreadID tid = 0; tid < numThreads; tid++) {
+maxEntries[tid] = threshold;
+}
+}
+
+for (ThreadID tid = numThreads; tid < O3MaxThreads; tid++) {
+maxEntries[tid] = 0;
+}
+
+resetState();
+}
+
+void
+ROB::resetState()
+{
+for (ThreadID tid = 0; tid  < O3MaxThreads; tid++) {
+threadEntries[tid] = 0;
+squashIt[tid] = instList[tid].end();
+squashedSeqNum[tid] = 0;
+doneSquashing[tid] = true;
+}
+numInstsInROB = 0;
+
+// Initialize the "universal" ROB head &

[gem5-dev] Change in gem5/gem5[develop]: cpu: Remove comm types from O3CPUImpl.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42103 )



Change subject: cpu: Remove comm types from O3CPUImpl.
..

cpu: Remove comm types from O3CPUImpl.

This struct is now empty, although we still need to keep it until all
the types within O3 have been de-templated and no longer need a template
argument.

Change-Id: I3889bdbb1b8d638f7b04e5bfb7698e35eb7f2e57
---
M src/cpu/o3/comm.hh
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/decode.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
17 files changed, 110 insertions(+), 168 deletions(-)



diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index eb85e5e..c35c2bd 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -51,9 +51,11 @@
 #include "cpu/o3/limits.hh"
 #include "sim/faults.hh"

+namespace O3Comm
+{
+
 /** Struct that defines the information passed from fetch to decode. */
-template
-struct DefaultFetchDefaultDecode
+struct FetchStruct
 {
 int size;

@@ -64,8 +66,7 @@
 };

 /** Struct that defines the information passed from decode to rename. */
-template
-struct DefaultDecodeDefaultRename
+struct DecodeStruct
 {
 int size;

@@ -73,8 +74,7 @@
 };

 /** Struct that defines the information passed from rename to IEW. */
-template
-struct DefaultRenameDefaultIEW
+struct RenameStruct
 {
 int size;

@@ -82,8 +82,7 @@
 };

 /** Struct that defines the information passed from IEW to commit. */
-template
-struct DefaultIEWDefaultCommit
+struct IEWStruct
 {
 int size;

@@ -99,7 +98,6 @@
 bool includeSquashInst[O3MaxThreads];
 };

-template
 struct IssueStruct
 {
 int size;
@@ -108,8 +106,7 @@
 };

 /** Struct that defines all backwards communication. */
-template
-struct TimeBufStruct
+struct TimeStruct
 {
 struct DecodeComm
 {
@@ -225,4 +222,6 @@
 bool iewUnblock[O3MaxThreads];
 };

+} // namespace O3Comm
+
 #endif //__CPU_O3_COMM_HH__
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 312d7a7..35223d6 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -46,6 +46,7 @@
 #include "base/statistics.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/inst_seq.hh"
+#include "cpu/o3/comm.hh"
 #include "cpu/o3/dyn_inst_ptr.hh"
 #include "cpu/o3/iew.hh"
 #include "cpu/o3/limits.hh"
@@ -86,12 +87,6 @@
 class DefaultCommit
 {
   public:
-// Typedefs from the Impl.
-typedef typename Impl::TimeStruct TimeStruct;
-typedef typename Impl::FetchStruct FetchStruct;
-typedef typename Impl::IEWStruct IEWStruct;
-typedef typename Impl::RenameStruct RenameStruct;
-
 typedef O3ThreadState Thread;

 /** Overall commit status. Used to determine if the CPU can deschedule
@@ -145,15 +140,15 @@
 void setThreads(std::vector );

 /** Sets the main time buffer pointer, used for backwards  
communication. */

-void setTimeBuffer(TimeBuffer *tb_ptr);
+void setTimeBuffer(TimeBuffer *tb_ptr);

-void setFetchQueue(TimeBuffer *fq_ptr);
+void setFetchQueue(TimeBuffer *fq_ptr);

 /** Sets the pointer to the queue coming from rename. */
-void setRenameQueue(TimeBuffer *rq_ptr);
+void setRenameQueue(TimeBuffer *rq_ptr);

 /** Sets the pointer to the queue coming from IEW. */
-void setIEWQueue(TimeBuffer *iq_ptr);
+void setIEWQueue(TimeBuffer *iq_ptr);

 /** Sets the pointer to the IEW stage. */
 void setIEWStage(DefaultIEW *iew_stage);
@@ -324,29 +319,29 @@

   private:
 /** Time buffer interface. */
-TimeBuffer *timeBuffer;
+TimeBuffer *timeBuffer;

 /** Wire to write information heading to previous stages. */
-typename TimeBuffer::wire toIEW;
+typename TimeBuffer::wire toIEW;

 /** Wire to read information from IEW (for ROB). */
-typename TimeBuffer::wire robInfoFromIEW;
+typename TimeBuffer::wire robInfoFromIEW;

-TimeBuffer *fetchQueue;
+TimeBuffer *fetchQueue;

-typename TimeBuffer::wire fromFetch;
+typename TimeBuffer::wire fromFetch;

 /** IEW instruction queue interface. */
-TimeBuffer *iewQueue;
+TimeBuffer *iewQueue;

 /** Wire to read information from IEW queue. */
-typename TimeBuffer::wire fromIEW;
+typename TimeBuffer::wire fromIEW;

 /** Rename instruction queue interface, for ROB. */
-TimeBuffer *renameQueue;
+TimeBuffer *renameQueue;

 /** Wire to read information from rename queue. */
-typename TimeBuffer::wire fromRename;
+typename TimeBuffer::wire fromRename;

   public:
 /** ROB interface. */
diff --git a/src/cpu/o3

[gem5-dev] Change in gem5/gem5[develop]: cpu: Remove the MemDepPred template parameter from MemDepUnit.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42104 )



Change subject: cpu: Remove the MemDepPred template parameter from  
MemDepUnit.

..

cpu: Remove the MemDepPred template parameter from MemDepUnit.

Hard code this to StoreSet, the only value ever used with this
parameter. If the dependency predictor needs to be updatable, there
should be a well defined interface for it which can be connected at run
time.

Change-Id: Ie30a742eac98220cc39679d26ada5d08099659a0
---
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/mem_dep_unit.cc
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/mem_dep_unit_impl.hh
4 files changed, 63 insertions(+), 67 deletions(-)



diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 8cfbfeb..3c97e64 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -291,7 +291,7 @@
 /** The memory dependence unit, which tracks/predicts memory  
dependences

  *  between instructions.
  */
-MemDepUnit memDepUnit[O3MaxThreads];
+MemDepUnit memDepUnit[O3MaxThreads];

 /** The queue to the execute stage.  Issued instructions will be  
written

  *  into it.
diff --git a/src/cpu/o3/mem_dep_unit.cc b/src/cpu/o3/mem_dep_unit.cc
index 21c91d7..963d614 100644
--- a/src/cpu/o3/mem_dep_unit.cc
+++ b/src/cpu/o3/mem_dep_unit.cc
@@ -28,20 +28,15 @@

 #include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/mem_dep_unit_impl.hh"
-#include "cpu/o3/store_set.hh"

 #ifdef DEBUG
 template <>
-int
-MemDepUnit::MemDepEntry::memdep_count = 0;
+int MemDepUnit::MemDepEntry::memdep_count = 0;
 template <>
-int
-MemDepUnit::MemDepEntry::memdep_insert = 0;
+int MemDepUnit::MemDepEntry::memdep_insert = 0;
 template <>
-int
-MemDepUnit::MemDepEntry::memdep_erase = 0;
+int MemDepUnit::MemDepEntry::memdep_erase = 0;
 #endif

-// Force instantation of memory dependency unit using store sets and
-// O3CPUImpl.
-template class MemDepUnit;
+// Force instantation of memory dependency unit using O3CPUImpl.
+template class MemDepUnit;
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index cd81939..0b8a852 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -51,6 +51,7 @@
 #include "cpu/inst_seq.hh"
 #include "cpu/o3/dyn_inst_ptr.hh"
 #include "cpu/o3/limits.hh"
+#include "cpu/o3/store_set.hh"
 #include "debug/MemDepUnit.hh"

 struct SNHash {
@@ -81,7 +82,7 @@
  * utilize.  Thus this class should be most likely be rewritten for other
  * dependence prediction schemes.
  */
-template 
+template 
 class MemDepUnit
 {
   protected:
@@ -257,7 +258,7 @@
  *  this unit what instruction the newly added instruction is dependent
  *  upon.
  */
-MemDepPred depPred;
+StoreSet depPred;

 /** Sequence numbers of outstanding load barriers. */
 std::unordered_set loadBarrierSNs;
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh  
b/src/cpu/o3/mem_dep_unit_impl.hh

index 1efb91c..de5764b 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -52,15 +52,15 @@
 #include "debug/MemDepUnit.hh"
 #include "params/DerivO3CPU.hh"

-template 
-MemDepUnit::MemDepUnit()
+template 
+MemDepUnit::MemDepUnit()
 : iqPtr(NULL),
   stats(nullptr)
 {
 }

-template 
-MemDepUnit::MemDepUnit(const DerivO3CPUParams )
+template 
+MemDepUnit::MemDepUnit(const DerivO3CPUParams )
 : _name(params.name + ".memdepunit"),
   depPred(params.store_set_clear_period, params.SSITSize,
   params.LFSTSize),
@@ -70,8 +70,8 @@
 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
 }

-template 
-MemDepUnit::~MemDepUnit()
+template 
+MemDepUnit::~MemDepUnit()
 {
 for (ThreadID tid = 0; tid < O3MaxThreads; tid++) {

@@ -95,9 +95,9 @@
 #endif
 }

-template 
+template 
 void
-MemDepUnit::init(
+MemDepUnit::init(
 const DerivO3CPUParams , ThreadID tid, FullO3CPU *cpu)
 {
 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
@@ -112,8 +112,8 @@
 cpu->addStatGroup(stats_group_name.c_str(), );
 }

-template 
-MemDepUnit::
+template 
+MemDepUnit::
 MemDepUnitStats::MemDepUnitStats(Stats::Group *parent)
 : Stats::Group(parent),
   ADD_STAT(insertedLoads, UNIT_COUNT,
@@ -125,9 +125,9 @@
 {
 }

-template 
+template 
 bool
-MemDepUnit::isDrained() const
+MemDepUnit::isDrained() const
 {
 bool drained = instsToReplay.empty()
  && memDepHash.empty()
@@ -138,9 +138,9 @@
 return drained;
 }

-template 
+template 
 void
-MemDepUnit::drainSanityCheck() const
+MemDepUnit::drainSanityCheck() const
 {
 assert(instsToReplay.empty());
 assert(memDepHash.empty());
@@ -150,9 +150,9 @@
 assert(memDepHash.empty());
 }

-template 
+template 
 void
-MemDepUnit::takeOverFrom()
+MemDepUn

[gem5-dev] Change in gem5/gem5[develop]: cpu: Move MaxWidth and MaxThreads from O3CPUImpl to cpu/o3/limits.hh.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42097 )



Change subject: cpu: Move MaxWidth and MaxThreads from O3CPUImpl to  
cpu/o3/limits.hh.

..

cpu: Move MaxWidth and MaxThreads from O3CPUImpl to cpu/o3/limits.hh.

Change-Id: I2534661bbdbd8537129403f97c8fb767a2eb85d6
---
M src/cpu/o3/comm.hh
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/decode.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/inst_queue_impl.hh
A src/cpu/o3/limits.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/mem_dep_unit_impl.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob.hh
M src/cpu/o3/rob_impl.hh
23 files changed, 197 insertions(+), 148 deletions(-)



diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index efb044f..43515ac 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -47,6 +47,7 @@
 #include "arch/types.hh"
 #include "base/types.hh"
 #include "cpu/inst_seq.hh"
+#include "cpu/o3/limits.hh"
 #include "sim/faults.hh"

 /** Struct that defines the information passed from fetch to decode. */
@@ -56,7 +57,7 @@

 int size;

-DynInstPtr insts[Impl::MaxWidth];
+DynInstPtr insts[O3MaxWidth];
 Fault fetchFault;
 InstSeqNum fetchFaultSN;
 bool clearFetchFault;
@@ -69,7 +70,7 @@

 int size;

-DynInstPtr insts[Impl::MaxWidth];
+DynInstPtr insts[O3MaxWidth];
 };

 /** Struct that defines the information passed from rename to IEW. */
@@ -79,7 +80,7 @@

 int size;

-DynInstPtr insts[Impl::MaxWidth];
+DynInstPtr insts[O3MaxWidth];
 };

 /** Struct that defines the information passed from IEW to commit. */
@@ -89,16 +90,16 @@

 int size;

-DynInstPtr insts[Impl::MaxWidth];
-DynInstPtr mispredictInst[Impl::MaxThreads];
-Addr mispredPC[Impl::MaxThreads];
-InstSeqNum squashedSeqNum[Impl::MaxThreads];
-TheISA::PCState pc[Impl::MaxThreads];
+DynInstPtr insts[O3MaxWidth];
+DynInstPtr mispredictInst[O3MaxThreads];
+Addr mispredPC[O3MaxThreads];
+InstSeqNum squashedSeqNum[O3MaxThreads];
+TheISA::PCState pc[O3MaxThreads];

-bool squash[Impl::MaxThreads];
-bool branchMispredict[Impl::MaxThreads];
-bool branchTaken[Impl::MaxThreads];
-bool includeSquashInst[Impl::MaxThreads];
+bool squash[O3MaxThreads];
+bool branchMispredict[O3MaxThreads];
+bool branchTaken[O3MaxThreads];
+bool includeSquashInst[O3MaxThreads];
 };

 template
@@ -107,7 +108,7 @@

 int size;

-DynInstPtr insts[Impl::MaxWidth];
+DynInstPtr insts[O3MaxWidth];
 };

 /** Struct that defines all backwards communication. */
@@ -128,12 +129,12 @@
 bool branchTaken;
 };

-decodeComm decodeInfo[Impl::MaxThreads];
+decodeComm decodeInfo[O3MaxThreads];

 struct renameComm {
 };

-renameComm renameInfo[Impl::MaxThreads];
+renameComm renameInfo[O3MaxThreads];

 struct iewComm {
 // Also eventually include skid buffer space.
@@ -151,7 +152,7 @@
 bool usedLSQ;
 };

-iewComm iewInfo[Impl::MaxThreads];
+iewComm iewInfo[O3MaxThreads];

 struct commitComm {
  
/

@@ -216,14 +217,14 @@

 };

-commitComm commitInfo[Impl::MaxThreads];
+commitComm commitInfo[O3MaxThreads];

-bool decodeBlock[Impl::MaxThreads];
-bool decodeUnblock[Impl::MaxThreads];
-bool renameBlock[Impl::MaxThreads];
-bool renameUnblock[Impl::MaxThreads];
-bool iewBlock[Impl::MaxThreads];
-bool iewUnblock[Impl::MaxThreads];
+bool decodeBlock[O3MaxThreads];
+bool decodeUnblock[O3MaxThreads];
+bool renameBlock[O3MaxThreads];
+bool renameUnblock[O3MaxThreads];
+bool iewBlock[O3MaxThreads];
+bool iewUnblock[O3MaxThreads];
 };

 #endif //__CPU_O3_COMM_HH__
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 92e87a2..3418bd3 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -46,6 +46,7 @@
 #include "base/statistics.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/inst_seq.hh"
+#include "cpu/o3/limits.hh"
 #include "cpu/timebuf.hh"
 #include "enums/CommitPolicy.hh"
 #include "sim/probe/probe.hh"
@@ -123,7 +124,7 @@
 /** Next commit status, to be set at the end of the cycle. */
 CommitStatus _nextStatus;
 /** Per-thread status. */
-ThreadStatus commitStatus[Impl::MaxThreads];
+ThreadStatus commitStatus[O3MaxThreads];
 /** Commit policy used in SMT mode. */
 CommitPolicy commitPolicy;

@@ -173,7 +174,7 @@
 void setActiveThreads(std:

[gem5-dev] Change in gem5/gem5[develop]: cpu: De-templatize the BaseO3DynInst.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42096 )



Change subject: cpu: De-templatize the BaseO3DynInst.
..

cpu: De-templatize the BaseO3DynInst.

Change-Id: If77561b811e10adf54a8b9e28f61e143ed3ead33
---
M src/cpu/o3/dyn_inst.cc
M src/cpu/o3/dyn_inst.hh
D src/cpu/o3/dyn_inst_impl.hh
M src/cpu/o3/impl.hh
4 files changed, 314 insertions(+), 367 deletions(-)



diff --git a/src/cpu/o3/dyn_inst.cc b/src/cpu/o3/dyn_inst.cc
index e6da0a7..42204cf 100644
--- a/src/cpu/o3/dyn_inst.cc
+++ b/src/cpu/o3/dyn_inst.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2010-2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2004-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -26,9 +38,292 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

-#include "cpu/o3/dyn_inst_impl.hh"
-#include "cpu/o3/impl.hh"
+#include "cpu/o3/dyn_inst.hh"

-// Force instantiation of BaseO3DynInst for all the implementations that
-// are needed.
-template class BaseO3DynInst;
+#include 
+
+#include "debug/DynInst.hh"
+#include "debug/IQ.hh"
+#include "debug/O3PipeView.hh"
+
+BaseO3DynInst::BaseO3DynInst(const StaticInstPtr _inst,
+ const StaticInstPtr &_macroop,
+ TheISA::PCState _pc, TheISA::PCState pred_pc,
+ InstSeqNum seq_num, FullO3CPU  
*_cpu)

+: seqNum(seq_num), staticInst(static_inst), cpu(_cpu), pc(_pc),
+  regs(staticInst->numSrcRegs(), staticInst->numDestRegs()),
+  predPC(pred_pc), macroop(_macroop)
+{
+this->regs.init();
+
+status.reset();
+
+instFlags.reset();
+instFlags[RecordResult] = true;
+instFlags[Predicate] = true;
+instFlags[MemAccPredicate] = true;
+
+#ifndef NDEBUG
+++cpu->instcount;
+
+if (cpu->instcount > 1500) {
+#ifdef DEBUG
+cpu->dumpInsts();
+dumpSNList();
+#endif
+assert(cpu->instcount <= 1500);
+}
+
+DPRINTF(DynInst,
+"DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
+seqNum, cpu->name(), cpu->instcount);
+#endif
+
+#ifdef DEBUG
+cpu->snList.insert(seqNum);
+#endif
+
+}
+
+BaseO3DynInst::BaseO3DynInst(const StaticInstPtr &_staticInst,
+ const StaticInstPtr &_macroop)
+: BaseO3DynInst(_staticInst, _macroop, {}, {}, 0, nullptr)
+{}
+
+BaseO3DynInst::~BaseO3DynInst()
+{
+#if TRACING_ON
+if (DTRACE(O3PipeView)) {
+Tick fetch = this->fetchTick;
+// fetchTick can be -1 if the instruction fetched outside the trace
+// window.
+if (fetch != -1) {
+Tick val;
+// Print info needed by the pipeline activity viewer.
+ 
DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",

+ fetch,
+ this->instAddr(),
+ this->microPC(),
+ this->seqNum,
+ this->staticInst->disassemble(this->instAddr()));
+
+val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
+DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
+val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
+DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
+val = (this->dispatchTick == -1) ? 0 : fetch +  
this->dispatchTick;

+DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
+val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
+DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
+val = (this->completeTick == -1) ? 0 : fetch +  
this->completeTick;

+DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
+val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
+
+Tick valS = (this->storeTick == -1) ? 0 : fetch +  
this->storeTick;

+DPRINTFR(O3PipeView, "O3PipeView:retire:%llu:store:%llu\n",
+val, valS);
+}
+}
+#endif
+
+delete [] mem

[gem5-dev] Change in gem5/gem5[develop]: cpu: Remove the O3CPU type from the O3CPUImpl.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42102 )



Change subject: cpu: Remove the O3CPU type from the O3CPUImpl.
..

cpu: Remove the O3CPU type from the O3CPUImpl.

Change-Id: I4dca10ea3ae1c9bb0f2cb55c7d303f1fd8d25283
---
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/decode.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/mem_dep_unit_impl.hh
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob.hh
M src/cpu/o3/rob_impl.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_state.hh
26 files changed, 85 insertions(+), 102 deletions(-)



diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 7cad7fe..312d7a7 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -87,7 +87,6 @@
 {
   public:
 // Typedefs from the Impl.
-typedef typename Impl::O3CPU O3CPU;
 typedef typename Impl::TimeStruct TimeStruct;
 typedef typename Impl::FetchStruct FetchStruct;
 typedef typename Impl::IEWStruct IEWStruct;
@@ -134,7 +133,7 @@

   public:
 /** Construct a DefaultCommit with the given parameters. */
-DefaultCommit(O3CPU *_cpu, const DerivO3CPUParams );
+DefaultCommit(FullO3CPU *_cpu, const DerivO3CPUParams );

 /** Returns the name of the DefaultCommit. */
 std::string name() const;
@@ -355,7 +354,7 @@

   private:
 /** Pointer to O3CPU. */
-O3CPU *cpu;
+FullO3CPU *cpu;

 /** Vector of all of the threads. */
 std::vector thread;
@@ -477,7 +476,7 @@
 int htmStops[O3MaxThreads];

 struct CommitStats : public Stats::Group {
-CommitStats(O3CPU *cpu, DefaultCommit *commit);
+CommitStats(FullO3CPU *cpu, DefaultCommit *commit);
 /** Stat for the total number of squashed instructions discarded by
  * commit.
  */
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index e0311bc..ad037c8 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -78,7 +78,8 @@
 }

 template 
-DefaultCommit::DefaultCommit(O3CPU *_cpu, const DerivO3CPUParams  
)

+DefaultCommit::DefaultCommit(FullO3CPU *_cpu,
+const DerivO3CPUParams )
 : commitPolicy(params.smtCommitPolicy),
   cpu(_cpu),
   iewToCommitDelay(params.iewToCommitDelay),
@@ -149,7 +150,7 @@
 }

 template 
-DefaultCommit::CommitStats::CommitStats(O3CPU *cpu,
+DefaultCommit::CommitStats::CommitStats(FullO3CPU *cpu,
   DefaultCommit *commit)
 : Stats::Group(cpu, "commit"),
   ADD_STAT(commitSquashedInsts, UNIT_COUNT,
@@ -338,7 +339,7 @@

 // Commit must broadcast the number of free entries it has at the
 // start of the simulation, so it starts as active.
-cpu->activateStage(O3CPU::CommitIdx);
+cpu->activateStage(FullO3CPU::CommitIdx);

 cpu->activityThisCycle();
 }
@@ -490,10 +491,10 @@

 if (_nextStatus == Inactive && _status == Active) {
 DPRINTF(Activity, "Deactivating stage.\n");
-cpu->deactivateStage(O3CPU::CommitIdx);
+cpu->deactivateStage(FullO3CPU::CommitIdx);
 } else if (_nextStatus == Active && _status == Inactive) {
 DPRINTF(Activity, "Activating stage.\n");
-cpu->activateStage(O3CPU::CommitIdx);
+cpu->activateStage(FullO3CPU::CommitIdx);
 }

 _status = _nextStatus;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 9dd1ae2..8985262 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -302,7 +302,7 @@
 DPRINTF(O3CPU, "Workload[%i] process is %#x",
 tid, this->thread[tid]);
 this->thread[tid] = new typename FullO3CPU::Thread(
-(typename Impl::O3CPU *)(this),
+(FullO3CPU *)(this),
 tid, params.workload[tid]);

 //usedTids[tid] = true;
@@ -313,8 +313,7 @@
 Process* dummy_proc = NULL;

 this->thread[tid] = new typename FullO3CPU::Thread(
-(typename Impl::O3CPU *)(this),
-tid, dummy_proc);
+this, tid, dummy_proc);
 //usedTids[tid] = false;
 }
 }
@@ -333,8 +332,7 @@
 o3_tc, this->checker);
 }

-o3_tc->cpu = (typename Impl::O3CPU *)(this);
-assert(o3_tc->cpu);
+o3_tc->cpu = this;
 o3_tc->thread = 

[gem5-dev] Change in gem5/gem5[develop]: cpu: Collapse the SimpleCPUPolicy into O3CPUImpl.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42100 )



Change subject: cpu: Collapse the SimpleCPUPolicy into O3CPUImpl.
..

cpu: Collapse the SimpleCPUPolicy into O3CPUImpl.

Change-Id: I0bc160f28f084c8873c3e19be9a4d7a45f9480a0
---
M src/cpu/o3/commit.hh
M src/cpu/o3/cpu.hh
D src/cpu/o3/cpu_policy.hh
M src/cpu/o3/decode.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/rename.hh
10 files changed, 44 insertions(+), 111 deletions(-)



diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index ce5c889..f72f32e 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -88,12 +88,10 @@
 // Typedefs from the Impl.
 typedef typename Impl::O3CPU O3CPU;
 typedef typename Impl::DynInstPtr DynInstPtr;
-typedef typename Impl::CPUPol CPUPol;
-
-typedef typename CPUPol::TimeStruct TimeStruct;
-typedef typename CPUPol::FetchStruct FetchStruct;
-typedef typename CPUPol::IEWStruct IEWStruct;
-typedef typename CPUPol::RenameStruct RenameStruct;
+typedef typename Impl::TimeStruct TimeStruct;
+typedef typename Impl::FetchStruct FetchStruct;
+typedef typename Impl::IEWStruct IEWStruct;
+typedef typename Impl::RenameStruct RenameStruct;

 typedef O3ThreadState Thread;

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 9f0d001..4f21a34 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -55,11 +55,11 @@
 #include "config/the_isa.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/commit.hh"
-#include "cpu/o3/cpu_policy.hh"
 #include "cpu/o3/decode.hh"
 #include "cpu/o3/fetch.hh"
 #include "cpu/o3/free_list.hh"
 #include "cpu/o3/iew.hh"
+#include "cpu/o3/impl.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/rename.hh"
 #include "cpu/o3/rob.hh"
@@ -100,7 +100,6 @@
 {
   public:
 // Typedefs from the Impl here.
-typedef typename Impl::CPUPol CPUPolicy;
 typedef typename Impl::DynInstPtr DynInstPtr;
 typedef typename Impl::O3CPU O3CPU;

@@ -608,15 +607,15 @@
 /** Typedefs from the Impl to get the structs that each of the
  *  time buffers should use.
  */
-typedef typename CPUPolicy::TimeStruct TimeStruct;
+typedef typename Impl::TimeStruct TimeStruct;

-typedef typename CPUPolicy::FetchStruct FetchStruct;
+typedef typename Impl::FetchStruct FetchStruct;

-typedef typename CPUPolicy::DecodeStruct DecodeStruct;
+typedef typename Impl::DecodeStruct DecodeStruct;

-typedef typename CPUPolicy::RenameStruct RenameStruct;
+typedef typename Impl::RenameStruct RenameStruct;

-typedef typename CPUPolicy::IEWStruct IEWStruct;
+typedef typename Impl::IEWStruct IEWStruct;

 /** The main time buffer to do backwards communication. */
 TimeBuffer timeBuffer;
diff --git a/src/cpu/o3/cpu_policy.hh b/src/cpu/o3/cpu_policy.hh
deleted file mode 100644
index e016548..000
--- a/src/cpu/o3/cpu_policy.hh
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * Copyright (c) 2013 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __CPU_O3_CPU_POLICY_HH__
-#define __CPU_O3_CPU_POLICY_HH__
-
-#include "cpu/o3/comm.hh&

[gem5-dev] Change in gem5/gem5[develop]: cpu: Extract stage classes from O3's SimpleCPUPolicy.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42098 )



Change subject: cpu: Extract stage classes from O3's SimpleCPUPolicy.
..

cpu: Extract stage classes from O3's SimpleCPUPolicy.

Use the target types directly without that layer of indirection. This
also narrows the scope of some includes.

Change-Id: I152f2ce0684781a9b61bd9d5a38620c39a4c60e8
---
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/cpu_policy.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/rename.hh
11 files changed, 41 insertions(+), 48 deletions(-)



diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 3418bd3..f4c1305 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -46,6 +46,7 @@
 #include "base/statistics.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/inst_seq.hh"
+#include "cpu/o3/iew.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/timebuf.hh"
 #include "enums/CommitPolicy.hh"
@@ -95,9 +96,6 @@
 typedef typename CPUPol::IEWStruct IEWStruct;
 typedef typename CPUPol::RenameStruct RenameStruct;

-typedef typename CPUPol::Fetch Fetch;
-typedef typename CPUPol::IEW IEW;
-
 typedef O3ThreadState Thread;

 /** Overall commit status. Used to determine if the CPU can deschedule
@@ -162,13 +160,13 @@
 void setIEWQueue(TimeBuffer *iq_ptr);

 /** Sets the pointer to the IEW stage. */
-void setIEWStage(IEW *iew_stage);
+void setIEWStage(DefaultIEW *iew_stage);

 /** The pointer to the IEW stage. Used solely to ensure that
  * various events (traps, interrupts, syscalls) do not occur until
  * all stores have written back.
  */
-IEW *iewStage;
+DefaultIEW *iewStage;

 /** Sets pointer to list of active threads. */
 void setActiveThreads(std::list *at_ptr);
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 2cb24c0..c72c83c 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -291,7 +291,7 @@

 template 
 void
-DefaultCommit::setIEWStage(IEW *iew_stage)
+DefaultCommit::setIEWStage(DefaultIEW *iew_stage)
 {
 iewStage = iew_stage;
 }
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 9519d3b..2bc1fd4 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -54,8 +54,13 @@
 #include "base/statistics.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/comm.hh"
+#include "cpu/o3/commit.hh"
 #include "cpu/o3/cpu_policy.hh"
+#include "cpu/o3/decode.hh"
+#include "cpu/o3/fetch.hh"
+#include "cpu/o3/iew.hh"
 #include "cpu/o3/limits.hh"
+#include "cpu/o3/rename.hh"
 #include "cpu/o3/scoreboard.hh"
 #include "cpu/o3/thread_state.hh"
 #include "cpu/activity.hh"
@@ -538,19 +543,19 @@

   protected:
 /** The fetch stage. */
-typename CPUPolicy::Fetch fetch;
+DefaultFetch fetch;

 /** The decode stage. */
-typename CPUPolicy::Decode decode;
+DefaultDecode decode;

 /** The dispatch stage. */
-typename CPUPolicy::Rename rename;
+DefaultRename rename;

 /** The issue/execute/writeback stages. */
-typename CPUPolicy::IEW iew;
+DefaultIEW iew;

 /** The commit stage. */
-typename CPUPolicy::Commit commit;
+DefaultCommit commit;

 /** The rename mode of the vector registers */
 Enums::VecRegRenameMode vecMode;
diff --git a/src/cpu/o3/cpu_policy.hh b/src/cpu/o3/cpu_policy.hh
index 82dcd09..c5af880 100644
--- a/src/cpu/o3/cpu_policy.hh
+++ b/src/cpu/o3/cpu_policy.hh
@@ -31,17 +31,12 @@
 #define __CPU_O3_CPU_POLICY_HH__

 #include "cpu/o3/comm.hh"
-#include "cpu/o3/commit.hh"
-#include "cpu/o3/decode.hh"
-#include "cpu/o3/fetch.hh"
 #include "cpu/o3/free_list.hh"
-#include "cpu/o3/iew.hh"
 #include "cpu/o3/inst_queue.hh"
 #include "cpu/o3/lsq.hh"
 #include "cpu/o3/lsq_unit.hh"
 #include "cpu/o3/mem_dep_unit.hh"
 #include "cpu/o3/regfile.hh"
-#include "cpu/o3/rename.hh"
 #include "cpu/o3/rename_map.hh"
 #include "cpu/o3/rob.hh"
 #include "cpu/o3/store_set.hh"
@@ -73,17 +68,6 @@
 /** Typedef for the thread-specific LSQ units. */
 typedef ::LSQUnit LSQUnit;

-/** Typedef for fetch. */
-typedef DefaultFetch Fetch;
-/** Typedef for decode. */
-typedef DefaultDecode Decode;
-/** Typedef for rename. */
-typedef DefaultRename Rename;
-/** Typedef for Issue/Execute/Writeback. */
-typedef DefaultIEW IEW;
-/** Typedef for commit. */
-typedef DefaultCommit Commit;
-
 /** The str

[gem5-dev] Change in gem5/gem5[develop]: cpu: Pull all remaining non-comm types out of SimpleCPUPolicy.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42099 )



Change subject: cpu: Pull all remaining non-comm types out of  
SimpleCPUPolicy.

..

cpu: Pull all remaining non-comm types out of SimpleCPUPolicy.

Change-Id: I79c56533cf6a9d1c982cea3ca9bedc83e6afda49
---
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/cpu_policy.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
13 files changed, 59 insertions(+), 85 deletions(-)



diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index f4c1305..ce5c889 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -48,6 +48,8 @@
 #include "cpu/inst_seq.hh"
 #include "cpu/o3/iew.hh"
 #include "cpu/o3/limits.hh"
+#include "cpu/o3/rename_map.hh"
+#include "cpu/o3/rob.hh"
 #include "cpu/timebuf.hh"
 #include "enums/CommitPolicy.hh"
 #include "sim/probe/probe.hh"
@@ -88,9 +90,6 @@
 typedef typename Impl::DynInstPtr DynInstPtr;
 typedef typename Impl::CPUPol CPUPol;

-typedef typename CPUPol::RenameMap RenameMap;
-typedef typename CPUPol::ROB ROB;
-
 typedef typename CPUPol::TimeStruct TimeStruct;
 typedef typename CPUPol::FetchStruct FetchStruct;
 typedef typename CPUPol::IEWStruct IEWStruct;
@@ -172,10 +171,10 @@
 void setActiveThreads(std::list *at_ptr);

 /** Sets pointer to the commited state rename map. */
-void setRenameMap(RenameMap rm_ptr[O3MaxThreads]);
+void setRenameMap(UnifiedRenameMap rm_ptr[O3MaxThreads]);

 /** Sets pointer to the ROB. */
-void setROB(ROB *rob_ptr);
+void setROB(ROB *rob_ptr);

 /** Initializes stage by sending back the number of free entries. */
 void startupStage();
@@ -354,7 +353,7 @@

   public:
 /** ROB interface. */
-ROB *rob;
+ROB *rob;

   private:
 /** Pointer to O3CPU. */
@@ -461,7 +460,7 @@
 std::list *activeThreads;

 /** Rename map interface. */
-RenameMap *renameMap[O3MaxThreads];
+UnifiedRenameMap *renameMap[O3MaxThreads];

 /** True if last committed microop can be followed by an interrupt */
 bool canHandleInterrupts;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index c72c83c..4e5d05e 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -305,7 +305,7 @@

 template 
 void
-DefaultCommit::setRenameMap(RenameMap rm_ptr[])
+DefaultCommit::setRenameMap(UnifiedRenameMap rm_ptr[])
 {
 for (ThreadID tid = 0; tid < numThreads; tid++)
 renameMap[tid] = _ptr[tid];
@@ -313,7 +313,7 @@

 template 
 void
-DefaultCommit::setROB(ROB *rob_ptr)
+DefaultCommit::setROB(ROB *rob_ptr)
 {
 rob = rob_ptr;
 }
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 2bc1fd4..9f0d001 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -58,9 +58,11 @@
 #include "cpu/o3/cpu_policy.hh"
 #include "cpu/o3/decode.hh"
 #include "cpu/o3/fetch.hh"
+#include "cpu/o3/free_list.hh"
 #include "cpu/o3/iew.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/rename.hh"
+#include "cpu/o3/rob.hh"
 #include "cpu/o3/scoreboard.hh"
 #include "cpu/o3/thread_state.hh"
 #include "cpu/activity.hh"
@@ -564,16 +566,16 @@
 PhysRegFile regFile;

 /** The free list. */
-typename CPUPolicy::FreeList freeList;
+UnifiedFreeList freeList;

 /** The rename map. */
-typename CPUPolicy::RenameMap renameMap[O3MaxThreads];
+UnifiedRenameMap renameMap[O3MaxThreads];

 /** The commit rename map. */
-typename CPUPolicy::RenameMap commitRenameMap[O3MaxThreads];
+UnifiedRenameMap commitRenameMap[O3MaxThreads];

 /** The re-order buffer. */
-typename CPUPolicy::ROB rob;
+ROB rob;

 /** Active Threads List */
 std::list activeThreads;
diff --git a/src/cpu/o3/cpu_policy.hh b/src/cpu/o3/cpu_policy.hh
index c5af880..e016548 100644
--- a/src/cpu/o3/cpu_policy.hh
+++ b/src/cpu/o3/cpu_policy.hh
@@ -31,15 +31,6 @@
 #define __CPU_O3_CPU_POLICY_HH__

 #include "cpu/o3/comm.hh"
-#include "cpu/o3/free_list.hh"
-#include "cpu/o3/inst_queue.hh"
-#include "cpu/o3/lsq.hh"
-#include "cpu/o3/lsq_unit.hh"
-#include "cpu/o3/mem_dep_unit.hh"
-#include "cpu/o3/regfile.hh"
-#include "cpu/o3/rename_map.hh"
-#include "cpu/o3/rob.hh"
-#include "cpu/o3/store_set.hh"

 /**
  * Struct that defines the key classes to be used by the CPU.  All
@@ -53,21 +44,6 @@
 template
 struct SimpleCPUPolicy
 {
-/** Typedef for the freelist of registers. */
-typedef Unif

[gem5-dev] Change in gem5/gem5[develop]: cpu: Style fixes in the base and O3 dynamic inst classes.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42093 )



Change subject: cpu: Style fixes in the base and O3 dynamic inst classes.
..

cpu: Style fixes in the base and O3 dynamic inst classes.

Change-Id: Idfd8e71856931fa101e00c58a2aa4018d076
---
M src/cpu/base_dyn_inst.hh
M src/cpu/o3/dyn_inst.hh
2 files changed, 27 insertions(+), 20 deletions(-)



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 68a6bb3..a5a842a 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -729,8 +729,11 @@
 OpClass opClass() const { return staticInst->opClass(); }

 /** Returns the branch target address. */
-TheISA::PCState branchTarget() const
-{ return staticInst->branchTarget(pc); }
+TheISA::PCState
+branchTarget() const
+{
+return staticInst->branchTarget(pc);
+}

 /** Returns the number of source registers. */
 size_t numSrcRegs() const { return regs.numSrcs(); }
@@ -1016,11 +1019,15 @@

 /** Return whether dest registers' pinning status updated after squash  
*/

 bool
-isPinnedRegsSquashDone() const { return status[PinnedRegsSquashDone]; }
+isPinnedRegsSquashDone() const
+{
+return status[PinnedRegsSquashDone];
+}

 /** Sets dest registers' status updated after squash */
 void
-setPinnedRegsSquashDone() {
+setPinnedRegsSquashDone()
+{
 assert(!status[PinnedRegsSquashDone]);
 status.set(PinnedRegsSquashDone);
 }
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index f084368..7a54c7f 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -184,37 +184,37 @@
 this->thread->noSquashFromTC = no_squash_from_TC;
 }

-void forwardOldRegs()
+void
+forwardOldRegs()
 {

 for (int idx = 0; idx < this->numDestRegs(); idx++) {
 PhysRegIdPtr prev_phys_reg = this->regs.prevDestIdx(idx);
-const RegId& original_dest_reg =
-this->staticInst->destRegIdx(idx);
+const RegId& original_dest_reg =  
this->staticInst->destRegIdx(idx);

 switch (original_dest_reg.classValue()) {
   case IntRegClass:
 this->setIntRegOperand(this->staticInst.get(), idx,
-   this->cpu->readIntReg(prev_phys_reg));
+this->cpu->readIntReg(prev_phys_reg));
 break;
   case FloatRegClass:
 this->setFloatRegOperandBits(this->staticInst.get(), idx,
-   this->cpu->readFloatReg(prev_phys_reg));
+this->cpu->readFloatReg(prev_phys_reg));
 break;
   case VecRegClass:
 this->setVecRegOperand(this->staticInst.get(), idx,
-   this->cpu->readVecReg(prev_phys_reg));
+this->cpu->readVecReg(prev_phys_reg));
 break;
   case VecElemClass:
 this->setVecElemOperand(this->staticInst.get(), idx,
-   this->cpu->readVecElem(prev_phys_reg));
+this->cpu->readVecElem(prev_phys_reg));
 break;
   case VecPredRegClass:
 this->setVecPredRegOperand(this->staticInst.get(), idx,
-   this->cpu->readVecPredReg(prev_phys_reg));
+this->cpu->readVecPredReg(prev_phys_reg));
 break;
   case CCRegClass:
 this->setCCRegOperand(this->staticInst.get(), idx,
-   this->cpu->readCCReg(prev_phys_reg));
+this->cpu->readCCReg(prev_phys_reg));
 break;
   case MiscRegClass:
 // no need to forward misc reg values
@@ -309,25 +309,25 @@
 {
 return cpu->template setVecLane(this->regs.renamedDestIdx(idx),  
val);

 }
-virtual void
+void
 setVecLaneOperand(const StaticInst *si, int idx,
 const LaneData& val) override
 {
 return setVecLaneOperandT(si, idx, val);
 }
-virtual void
+void
 setVecLaneOperand(const StaticInst *si, int idx,
 const LaneData& val) override
 {
 return setVecLaneOperandT(si, idx, val);
 }
-virtual void
+void
 setVecLaneOperand(const StaticInst *si, int idx,
 const LaneData& val) override
 {
 return setVecLaneOperandT(si, idx, val);
 }
-virtual void
+void
 setVecLaneOperand(const StaticInst *si, int idx,
 const LaneData& val) override
 {
@@ -402,12 +402,12 @@
 

[gem5-dev] Change in gem5/gem5[develop]: cpu: Get rid of the unused eaSrcsReady method.

2021-03-03 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42095 )



Change subject: cpu: Get rid of the unused eaSrcsReady method.
..

cpu: Get rid of the unused eaSrcsReady method.

This method wasn't used by anything, and also made very unsafe
assumptions about what different source registers were used for.

Change-Id: I8f58aa70e139d3895499e04c86d8de2530e17d5a
---
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/dyn_inst_impl.hh
2 files changed, 0 insertions(+), 20 deletions(-)



diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 330c3e5..7ed4904 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -1022,9 +1022,6 @@
 ThreadContext *tcBase() const override { return thread->getTC(); }

   public:
-/** Returns whether or not the eff. addr. source registers are ready.  
*/

-bool eaSrcsReady() const;
-
 /** Is this instruction's memory access strictly ordered? */
 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
 void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; }
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 5e4d3c1..7bb9dde 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -202,23 +202,6 @@
 markSrcRegReady();
 }

-template 
-bool
-BaseO3DynInst::eaSrcsReady() const
-{
-// For now I am assuming that src registers 1..n-1 are the ones that  
the

-// EA calc depends on.  (i.e. src reg 0 is the source of the data to be
-// stored)
-
-for (int i = 1; i < numSrcRegs(); ++i) {
-if (!regs.readySrcIdx(i))
-return false;
-}
-
-return true;
-}
-
-

 template 
 void

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8f58aa70e139d3895499e04c86d8de2530e17d5a
Gerrit-Change-Number: 42095
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base: Add a macro to expand parameter pack expressions in order.

2021-03-02 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42033 )



Change subject: base: Add a macro to expand parameter pack expressions in  
order.

..

base: Add a macro to expand parameter pack expressions in order.

This wraps up the strange compiler goop necessary to evaluate
expressions based on parameter pack expansions in order.

Change-Id: I16fbd53d22492a8c20524e3ef8bb8ff5e5d59b14
---
M src/base/compiler.hh
1 file changed, 10 insertions(+), 0 deletions(-)



diff --git a/src/base/compiler.hh b/src/base/compiler.hh
index 643352c..9830e74 100644
--- a/src/base/compiler.hh
+++ b/src/base/compiler.hh
@@ -112,6 +112,16 @@
 // we can't do that with direct substitution.
 #  define M5_LIKELY(cond) __builtin_expect(!!(cond), 1)
 #  define M5_UNLIKELY(cond) __builtin_expect(!!(cond), 0)
+
+// Evaluate an expanded parameter pack in order. Multiple arguments can be
+// passed in which be evaluated in order relative to each other as a group.
+// The argument(s) must include a parameter pack to expand. This works  
because
+// the elements of a brace inclosed initializer list are evaluated in  
order,

+// as are the arguments to the comma operator, which evaluates to the later
+// value. This is compiler specific because it uses variadic templates.
+#define M5_EXPAND_IN_ORDER(...) \
+do { M5_VAR_USED int dummy[] = { 0, (__VA_ARGS__, 0)... }; } while (false)
+
 #else
 #  error "Don't know what to do for your compiler."
 #endif

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I16fbd53d22492a8c20524e3ef8bb8ff5e5d59b14
Gerrit-Change-Number: 42033
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch,arch-arm: Eliminate the "zeroing" field of vec reg elements.

2021-03-02 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41895 )


Change subject: arch,arch-arm: Eliminate the "zeroing" field of vec reg  
elements.

..

arch,arch-arm: Eliminate the "zeroing" field of vec reg elements.

This field wasn't used for anything.

Change-Id: I81f38743a7b4f87c56adb8ffeda6f9a096d09842
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41895
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/isa/operands.isa
M src/arch/isa_parser/operand_types.py
2 files changed, 80 insertions(+), 80 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 0f18ffd..da78561 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -131,8 +131,8 @@
 def vectorReg(idx, elems = None):
 return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)

-def vectorRegElem(elem, ext = 'sf', zeroing = False):
-return (elem, ext, zeroing)
+def vectorRegElem(elem, ext = 'sf'):
+return (elem, ext)

 def vecPredReg(idx):
 return ('VecPredReg', 'pc', idx, None, srtNormal)
@@ -354,9 +354,9 @@
 'AA64FpOp1P1': vectorRegElem('1'),
 'AA64FpOp1P2': vectorRegElem('2'),
 'AA64FpOp1P3': vectorRegElem('3'),
-'AA64FpOp1S':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpOp1D':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpOp1Q':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpOp1S':  vectorRegElem('0', 'sf'),
+'AA64FpOp1D':  vectorRegElem('0', 'df'),
+'AA64FpOp1Q':  vectorRegElem('0', 'tud')
 }),

 'AA64FpOp2':   vectorReg('op2',
@@ -365,9 +365,9 @@
 'AA64FpOp2P1': vectorRegElem('1'),
 'AA64FpOp2P2': vectorRegElem('2'),
 'AA64FpOp2P3': vectorRegElem('3'),
-'AA64FpOp2S':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpOp2D':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpOp2Q':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpOp2S':  vectorRegElem('0', 'sf'),
+'AA64FpOp2D':  vectorRegElem('0', 'df'),
+'AA64FpOp2Q':  vectorRegElem('0', 'tud')
 }),

 'AA64FpOp3':   vectorReg('op3',
@@ -376,9 +376,9 @@
 'AA64FpOp3P1': vectorRegElem('1'),
 'AA64FpOp3P2': vectorRegElem('2'),
 'AA64FpOp3P3': vectorRegElem('3'),
-'AA64FpOp3S':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpOp3D':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpOp3Q':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpOp3S':  vectorRegElem('0', 'sf'),
+'AA64FpOp3D':  vectorRegElem('0', 'df'),
+'AA64FpOp3Q':  vectorRegElem('0', 'tud')
 }),

 'AA64FpDest':   vectorReg('dest',
@@ -387,9 +387,9 @@
 'AA64FpDestP1': vectorRegElem('1'),
 'AA64FpDestP2': vectorRegElem('2'),
 'AA64FpDestP3': vectorRegElem('3'),
-'AA64FpDestS':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpDestD':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpDestQ':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpDestS':  vectorRegElem('0', 'sf'),
+'AA64FpDestD':  vectorRegElem('0', 'df'),
+'AA64FpDestQ':  vectorRegElem('0', 'tud')
 }),

 'AA64FpDest2':   vectorReg('dest2',
@@ -398,9 +398,9 @@
 'AA64FpDest2P1': vectorRegElem('1'),
 'AA64FpDest2P2': vectorRegElem('2'),
 'AA64FpDest2P3': vectorRegElem('3'),
-'AA64FpDest2S':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpDest2D':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpDest2Q':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpDest2S':  vectorRegElem('0', 'sf'),
+'AA64FpDest2D':  vectorRegElem('0', 'df'),
+'AA64FpDest2Q':  vectorRegElem('0', 'tud')
 }),

 'AA64FpOp1V0':   vectorReg('op1',
@@ -409,9 +409,9 @@
 'AA64FpOp1P1V0': vectorRegElem('1'),
 'AA64FpOp1P2V0': vectorRegElem('2'),
 'AA64FpOp1P3V0': vectorRegElem('3'),
-'AA64FpOp1SV0':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpOp1DV0':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpOp1QV0':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpOp1SV0':  vectorRegElem('0', 'sf'),
+'AA64FpOp1DV0':  vectorRegElem('0', 'df'),
+'AA64FpOp1QV0':  vectorRegElem('0', 'tud')
 }),

 'AA64FpOp1V1':   vectorReg('op1+1',
@@ -420,9 +420,9 @@
 'AA64FpOp1P1V1': vectorRegElem('1'),
 'AA64FpOp1P2V1': vectorRegElem('2'),
 'AA64FpOp1P3V1': vectorRegElem('3'),
-'AA64FpOp1SV1':  vectorRegElem('0', 'sf', zeroing = True),
- 

[gem5-dev] Re: review backlog

2021-03-01 Thread Gabe Black via gem5-dev
Ok, thanks, just want to make sure they don't get forgotten. This was also
a reminder for folks not working directly on the release.

Gabe

On Mon, Mar 1, 2021 at 4:02 PM Jason Lowe-Power  wrote:

> Hey Gabe,
>
> Just FYI, those of use working on the release still have to test and fix
> bugs that we find on the staging branch. In releases past, this has taken
> 2-4 weeks of 100% effort. We'll get to these new changes when we can!
>
> Cheers,
> Jason
>
> On Mon, Mar 1, 2021 at 3:56 PM Gabe Black via gem5-dev 
> wrote:
>
>> Hi folks. Now that the release branch has been created, I'd appreciate it
>> if we could start draining out the review backlog that has built up. I have
>> the following series of changes out and ready for review if you're so
>> inclined, link to the last change in the set.
>>
>> Eliminating the arch/utility.hh header (5 CLs)
>> https://gem5-review.googlesource.com/c/public/gem5/+/39337
>>
>> Mostly eliminate the arch/types.hh header, and some other cleanups (12
>> CLs)
>> https://gem5-review.googlesource.com/c/public/gem5/+/41893
>>
>> SCons cleanup (24 CLs)
>> https://gem5-review.googlesource.com/c/public/gem5/+/41599
>>
>> Guest ABI implementation rework (1 CL)
>> https://gem5-review.googlesource.com/c/public/gem5/+/41600
>>
>> Drain most of the contents out of arch/registers.hh (10 CLs)
>> https://gem5-review.googlesource.com/c/public/gem5/+/41742
>>
>> Vector (predicate) register simplification, cleanup, streamlining (17 CLs)
>> https://gem5-review.googlesource.com/c/public/gem5/+/42003
>>
>> Some of these ~70 CLs have been reviewed already, but are being held up
>> by CLs ahead of them which have not. I've generally tried to pluck out CLs
>> which are already reviewed and which can jump the queue, but I think I've
>> already done that for all the CLs where it makes sense. Many of these are
>> really simple CLs which just delete things which aren't being used, so they
>> should be pretty easy to review.
>>
>> Gabe
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>
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[gem5-dev] review backlog

2021-03-01 Thread Gabe Black via gem5-dev
Hi folks. Now that the release branch has been created, I'd appreciate it
if we could start draining out the review backlog that has built up. I have
the following series of changes out and ready for review if you're so
inclined, link to the last change in the set.

Eliminating the arch/utility.hh header (5 CLs)
https://gem5-review.googlesource.com/c/public/gem5/+/39337

Mostly eliminate the arch/types.hh header, and some other cleanups (12 CLs)
https://gem5-review.googlesource.com/c/public/gem5/+/41893

SCons cleanup (24 CLs)
https://gem5-review.googlesource.com/c/public/gem5/+/41599

Guest ABI implementation rework (1 CL)
https://gem5-review.googlesource.com/c/public/gem5/+/41600

Drain most of the contents out of arch/registers.hh (10 CLs)
https://gem5-review.googlesource.com/c/public/gem5/+/41742

Vector (predicate) register simplification, cleanup, streamlining (17 CLs)
https://gem5-review.googlesource.com/c/public/gem5/+/42003

Some of these ~70 CLs have been reviewed already, but are being held up by
CLs ahead of them which have not. I've generally tried to pluck out CLs
which are already reviewed and which can jump the queue, but I think I've
already done that for all the CLs where it makes sense. Many of these are
really simple CLs which just delete things which aren't being used, so they
should be pretty easy to review.

Gabe
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[gem5-dev] Re: de-templating the O3 CPU

2021-03-01 Thread Gabe Black via gem5-dev
Hi Nathanael, I intend to split it into multiple steps, if nothing else
just to make reviewing the changes more feasible.

Gabe

On Mon, Mar 1, 2021 at 1:51 AM Nathanael Premillieu <
nathanael.premill...@huawei.com> wrote:

> Hi Gabe,
>
>
>
> I totally agree with you on this.
>
> I think it’s also quite a blocker when learning gem5 as it makes the code
> difficult to follow and understand.
>
> Do you intend to do it as one big patch or split that into several steps
> (if that’s possible)?
>
>
>
> Thanks,
>
> Nathanael
>
>
>
> *From:* Gabe Black via gem5-dev [mailto:gem5-dev@gem5.org]
> *Sent:* Saturday, February 27, 2021 11:13 AM
> *To:* gem5 Developer List 
> *Cc:* Gabe Black 
> *Subject:* [gem5-dev] de-templating the O3 CPU
>
>
>
> Hi folks. The O3 CPU uses templates pretty heavily, I think nominally to
> make it possible to switch in different parts of the CPU to change how, for
> example, a pipeline stage is implemented.
>
>
>
> Realistically, the different parts of the CPU are probably too
> interdependent for that to actually work, and all the templates and
> indirection make the code a lot more complicated than it really needs to be.
>
>
>
> Also, there is a pseudo-generic dynamic instruction base class in
> cpu/base_dyn_inst.hh which could, again theoretically, be used as a base
> class for other CPUs to reuse. Unfortunately that too is probably too tied
> to its only consumer, the O3 CPU, to be realistically reusable.
>
>
>
> I would like to merge the base dynamic instruction class into the O3
> version, and then de-templatize the whole O3 CPU. I think that will make
> the code a lot easier to work on, and I think our ability to maintain and
> update O3 is something we need to improve in at least the medium term.
>
>
>
> Any thoughts? Objections? Votes of support?
>
>
>
> Gabe
>
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[gem5-dev] de-templating the O3 CPU

2021-02-27 Thread Gabe Black via gem5-dev
Hi folks. The O3 CPU uses templates pretty heavily, I think nominally to
make it possible to switch in different parts of the CPU to change how, for
example, a pipeline stage is implemented.

Realistically, the different parts of the CPU are probably too
interdependent for that to actually work, and all the templates and
indirection make the code a lot more complicated than it really needs to be.

Also, there is a pseudo-generic dynamic instruction base class in
cpu/base_dyn_inst.hh which could, again theoretically, be used as a base
class for other CPUs to reuse. Unfortunately that too is probably too tied
to its only consumer, the O3 CPU, to be realistically reusable.

I would like to merge the base dynamic instruction class into the O3
version, and then de-templatize the whole O3 CPU. I think that will make
the code a lot easier to work on, and I think our ability to maintain and
update O3 is something we need to improve in at least the medium term.

Any thoughts? Objections? Votes of support?

Gabe
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[gem5-dev] Change in gem5/gem5[develop]: arch: Delete a few unused vector register types/constants.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42003 )



Change subject: arch: Delete a few unused vector register types/constants.
..

arch: Delete a few unused vector register types/constants.

These are used internally in ARM, but dummy versions of them were being
published by all ISAs even though nobody was consuming them.

Change-Id: I93d9e53c503e375a2f901bb6f7f4c00a7cdadb20
---
M src/arch/generic/vec_pred_reg.hh
M src/arch/generic/vec_reg.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/registers.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/registers.hh
M src/arch/x86/registers.hh
8 files changed, 1 insertion(+), 30 deletions(-)



diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index 86e3b83..432cccf 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -376,10 +376,7 @@
 /// Dummy type aliases and constants for architectures that do not  
implement

 /// vector predicate registers.
 /// @{
-using DummyVecPredReg = VecPredRegT;
-using DummyConstVecPredReg = VecPredRegT;
-using DummyVecPredRegContainer = DummyVecPredReg::Container;
-constexpr size_t DummyVecPredRegSizeBits = 8;
+using DummyVecPredRegContainer = VecPredRegContainer<8>;
 /// @}

 #endif  // __ARCH_GENERIC_VEC_PRED_REG_HH__
diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index 1f0df1c..caa2d34 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -264,8 +264,6 @@
 constexpr unsigned DummyNumVecElemPerVecReg = 2;
 using DummyVecRegContainer =
 VecRegContainer;
-constexpr size_t DummyVecRegSizeBytes = DummyNumVecElemPerVecReg *
-sizeof(DummyVecElem);
 /** @} */

 #endif /* __ARCH_GENERIC_VEC_REG_HH__ */
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 4ca73d8..a19b174 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -272,13 +272,9 @@
 using VecElem = ::DummyVecElem;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
-constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;

 // Not applicable to MIPS
-using VecPredReg = ::DummyVecPredReg;
-using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
-constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;

 } // namespace MipsISA

diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index aa01945..27a481e 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -51,13 +51,9 @@
 using VecElem = ::DummyVecElem;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
-constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;

 // Not applicable to null
-using VecPredReg = ::DummyVecPredReg;
-using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
-constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;

 }

diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 5f5f67b..5395149 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -41,13 +41,9 @@
 using VecElem = ::DummyVecElem;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
-constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;

 // Not applicable to Power
-using VecPredReg = ::DummyVecPredReg;
-using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
-constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;

 // Constants Related to the number of registers
 const int NumIntArchRegs = 32;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 126132f..445cef4 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -95,13 +95,9 @@
 using VecElem = ::DummyVecElem;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
-constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;

 // Not applicable to RISC-V
-using VecPredReg = ::DummyVecPredReg;
-using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
-constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;

 const int NumIntArchRegs = 32;
 const int NumMicroIntRegs = 1;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index bf92f02..73946db 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -42,13 +42,9 @@
 using VecElem = ::DummyVecElem;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
-constexpr size_t VecRegSiz

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu,gpu-compute: Further simplify VecRegContainer.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41995 )



Change subject: arch,cpu,gpu-compute: Further simplify VecRegContainer.
..

arch,cpu,gpu-compute: Further simplify VecRegContainer.

Get rid of VecRegT, and a few redundant or unused methods.

Change-Id: I6c88c40653e1939fe74b8ffb847ef50ab8064670
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/nativetrace.cc
M src/arch/arm/registers.hh
M src/arch/gcn3/operand.hh
M src/arch/gcn3/registers.hh
M src/arch/generic/vec_reg.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/registers.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/registers.hh
M src/arch/x86/registers.hh
M src/cpu/o3/rename_map.cc
M src/gpu-compute/wavefront.cc
16 files changed, 58 insertions(+), 191 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index c7f82e0..c86cd17 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2348,15 +2348,6 @@
 }

 void
-ISA::zeroSveVecRegUpperPart(VecRegContainer , unsigned eCount)
-{
-auto vv = vc.as();
-for (int i = 2; i < eCount; ++i) {
-vv[i] = 0;
-}
-}
-
-void
 ISA::serialize(CheckpointOut ) const
 {
 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 7888229..62979fc 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -852,8 +852,16 @@

 unsigned getCurSveVecLenInBitsAtReset() const { return sveVL *  
128; }


-static void zeroSveVecRegUpperPart(VecRegContainer ,
-   unsigned eCount);
+template 
+static void
+zeroSveVecRegUpperPart(Elem *v, unsigned eCount)
+{
+static_assert(sizeof(Elem) <= sizeof(uint64_t));
+eCount *= (sizeof(uint64_t) / sizeof(Elem));
+for (int i = 16 / sizeof(Elem); i < eCount; ++i) {
+v[i] = 0;
+}
+}

 void serialize(CheckpointOut ) const override;
 void unserialize(CheckpointIn ) override;
diff --git a/src/arch/arm/isa/templates/sve_mem.isa  
b/src/arch/arm/isa/templates/sve_mem.isa

index f635870..9b1ab84 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -170,7 +170,7 @@

 %(rden_code)s;

-fault = readMemAtomic(xc, EA, memData.raw_ptr(),
+fault = readMemAtomic(xc, EA, memData.as(),
 memAccessSize, this->memAccessFlags, rdEn);

 %(fault_code)s;
@@ -228,7 +228,7 @@
 auto memDataView = memData.as();

 if (xc->readMemAccPredicate()) {
-memcpy(memData.raw_ptr(), pkt->getPtr(),
+memcpy(memData.as(), pkt->getPtr(),
pkt->getSize());
 }

@@ -265,7 +265,7 @@
 }

 if (fault == NoFault) {
-fault = writeMemAtomic(xc, memData.raw_ptr(),
+fault = writeMemAtomic(xc, memData.as(),
 EA, memAccessSize, this->memAccessFlags, nullptr, wrEn);
 }

@@ -303,7 +303,7 @@
 }

 if (fault == NoFault) {
-fault = writeMemTiming(xc, memData.raw_ptr(),
+fault = writeMemTiming(xc, memData.as(),
 EA, memAccessSize, this->memAccessFlags, nullptr, wrEn);
 }

@@ -1001,7 +1001,7 @@
 auto memDataView = memData.as();

 if (fault == NoFault) {
-fault = readMemAtomic(xc, EA, memData.raw_ptr(),
+fault = readMemAtomic(xc, EA, memData.as(),
 memAccessSize, this->memAccessFlags,
 std::vector(memAccessSize, true));
 %(memacc_code)s;
@@ -1059,7 +1059,7 @@
 ArmISA::VecRegContainer memData;
 auto memDataView = memData.as();

-memcpy(memData.raw_ptr(), pkt->getPtr(),
+memcpy(memData.as(), pkt->getPtr(),
 pkt->getSize());

 if (fault == NoFault) {
@@ -1100,7 +1100,7 @@
 }

 if (fault == NoFault) {
-fault = writeMemAtomic(xc, memData.raw_ptr(),
+fault = writeMemAtomic(xc, memData.as(),
 EA, memAccessSize, this->memAccessFlags, nullptr, wrEn);
 }

@@ -1138,7 +1138,7 @@
 }

 if (fault == NoFault) {
-fault = writeMemTiming(xc, memData.raw_ptr(),
+fault = writeMemTiming(xc, memData.as(),
 EA, memAccessSize, this->memAccessFlags, nullptr, wrEn);
 }

diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index 7075adb..f37ee4d 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -126,8 +126,7 @@
 changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);

 for (int i = 0; i < NumVecV7ArchRegs

[gem5-dev] Change in gem5/gem5[develop]: cpu: Use the built in << for VecReg and VecPredReg in ExeTrace.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42001 )



Change subject: cpu: Use the built in << for VecReg and VecPredReg in  
ExeTrace.

..

cpu: Use the built in << for VecReg and VecPredReg in ExeTrace.

There's no reason to reimplement printing code when VecReg and
VecPredReg types already know how to print themselves.

Change-Id: I092c28143de286d765312122b81ce865a5184091
---
M src/cpu/exetrace.cc
1 file changed, 2 insertions(+), 23 deletions(-)



diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 76db4d7..cf4a734 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -116,31 +116,10 @@
 if (Debug::ExecResult && data_status != DataInvalid) {
 switch (data_status) {
   case DataVec:
-{
-ccprintf(outs, " D=0x[");
-auto dv = data.as_vec->as();
-for (int i = TheISA::VecRegSizeBytes / 4 - 1; i >= 0;
- i--) {
-ccprintf(outs, "%08x", dv[i]);
-if (i != 0) {
-ccprintf(outs, "_");
-}
-}
-ccprintf(outs, "]");
-}
+ccprintf(outs, " D=%s", *data.as_vec);
 break;
   case DataVecPred:
-{
-ccprintf(outs, " D=0b[");
-auto pv = data.as_pred->as();
-for (int i = TheISA::VecPredRegSizeBits - 1; i >= 0;  
i--) {

-ccprintf(outs, pv[i] ? "1" : "0");
-if (i != 0 && i % 4 == 0) {
-ccprintf(outs, "_");
-}
-}
-ccprintf(outs, "]");
-}
+ccprintf(outs, " D=%s", *data.as_pred);
 break;
   default:
 ccprintf(outs, " D=%#018x", data.as_int);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I092c28143de286d765312122b81ce865a5184091
Gerrit-Change-Number: 42001
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Don't needlessly recreate ISA types in InstRecord.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42002 )



Change subject: sim: Don't needlessly recreate ISA types in InstRecord.
..

sim: Don't needlessly recreate ISA types in InstRecord.

The ISAs already define fully realized types. We don't need to
separately track what parameters they used and then feed them into the
same templates again elsewhere.

Change-Id: Iac18bb9374ff684259c6aa00036eac4d1026dcfc
---
M src/sim/insttracer.hh
1 file changed, 6 insertions(+), 7 deletions(-)



diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 636bf76..a2ecad4 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -94,8 +94,8 @@
 union {
 uint64_t as_int;
 double as_double;
-::VecRegContainer* as_vec;
-::VecPredRegContainer* as_pred;
+TheISA::VecRegContainer* as_vec;
+TheISA::VecPredRegContainer* as_pred;
 } data;

 /** @defgroup fetch_seq
@@ -201,17 +201,16 @@
 void setData(double d) { data.as_double = d; data_status = DataDouble;  
}


 void
-setData(::VecRegContainer& d)
+setData(TheISA::VecRegContainer& d)
 {
-data.as_vec = new ::VecRegContainer(d);
+data.as_vec = new TheISA::VecRegContainer(d);
 data_status = DataVec;
 }

 void
-setData(::VecPredRegContainer& d)
+setData(TheISA::VecPredRegContainer& d)
 {
-data.as_pred =
-new ::VecPredRegContainer(d);
+data.as_pred = new TheISA::VecPredRegContainer(d);
 data_status = DataVecPred;
 }


--
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Gerrit-Branch: develop
Gerrit-Change-Id: Iac18bb9374ff684259c6aa00036eac4d1026dcfc
Gerrit-Change-Number: 42002
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Separate printing and serialization of VecPredReg.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41999 )



Change subject: arch,cpu: Separate printing and serialization of VecPredReg.
..

arch,cpu: Separate printing and serialization of VecPredReg.

This is equivalent to what was done with VecReg recently.

Change-Id: I8e28c9796bf5cabd35a6bf5b89e55efcf9324d92
---
M src/arch/generic/vec_pred_reg.hh
M src/cpu/o3/regfile.hh
M src/cpu/simple_thread.hh
3 files changed, 37 insertions(+), 29 deletions(-)



diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index 6db0e1e..cdf5eb5 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -44,6 +44,7 @@
 #include 

 #include "base/cprintf.hh"
+#include "sim/serialize_handlers.hh"

 template 
 class VecPredRegContainer;
@@ -145,18 +146,13 @@
 friend std::ostream&
 operator<<(std::ostream& os, const MyClass& p)
 {
-// 0-sized is not allowed
-os << '[' << p.container[0];
-for (int i = 0; i < p.NUM_BITS; ++i) {
-os << " " << (p.container[i] ? 1 : 0);
-}
-os << ']';
+// Size must be greater than 0.
+for (int i = 0; i < NUM_BITS; i++)
+ccprintf(os, "%s%d", i ? " " : "[", (int)p.container[i]);
+ccprintf(os, "]");
 return os;
 }

-/// Returns a string representation of the register content.
-const std::string print() const { return csprintf("%s", *this); }
-
 /// Returns true if the first active element of the register is true.
 /// @param mask Input mask used to filter the predicates to be tested.
 /// @param actual_num_elems Actual number of vector elements  
considered for

@@ -318,18 +314,18 @@
 }
 }

-/// Returns a string representation of the register content.
-const std::string print() const { return csprintf("%s", *this); }
-
 friend std::ostream&
-operator<<(std::ostream& os, const MyClass& v)
+operator<<(std::ostream& os, const MyClass& p)
 {
-for (auto b: v.container) {
-os << csprintf("%d", b);
-}
+// Size must be greater than 0.
+for (int i = 0; i < NumBits; i++)
+ccprintf(os, "%s%d", i ? " " : "[", (int)p.container[i]);
+ccprintf(os, "]");
 return os;
 }

+friend ShowParam>;
+
 /// Create a view of this container.
 ///
 /// If NumElems is provided, the size of the container is  
bounds-checked,

@@ -359,17 +355,29 @@
 /// @}
 };

-/// Helper functions used for serialization/de-serialization
 template 
-inline bool
-to_number(const std::string& value, VecPredRegContainer& p)
+struct ParseParam>
 {
-int i = 0;
-for (const auto& c: value) {
-p[i] = (c == '1');
+static bool
+parse(const std::string , VecPredRegContainer )
+{
+int i = 0;
+for (const auto& c: s)
+value[i++] = (c == '1');
+return true;
 }
-return true;
-}
+};
+
+template 
+struct ShowParam>
+{
+static void
+show(std::ostream , const VecPredRegContainer )
+{
+for (auto b: value.container)
+ccprintf(os, "%d", b);
+}
+};

 /// Dummy type aliases and constants for architectures that do not  
implement

 /// vector predicate registers.
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 6c6b9b3..65a5338 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -238,7 +238,7 @@

 DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
 "data %s\n", int(phys_reg->index()),
-vecPredRegFile[phys_reg->index()].print());
+vecPredRegFile[phys_reg->index()]);

 return vecPredRegFile[phys_reg->index()];
 }
@@ -322,7 +322,7 @@
 assert(phys_reg->isVecPredPhysReg());

 DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
-int(phys_reg->index()), val.print());
+int(phys_reg->index()), val);

 vecPredRegFile[phys_reg->index()] = val;
 }
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 8f65ea3..7a4a4b7 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -330,7 +330,7 @@
 const TheISA::VecPredRegContainer& regVal =
 readVecPredRegFlat(flatIndex);
 DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n",
-reg.index(), flatIndex, regVal.print());
+reg.index(), flatIndex, regVal);
 return regVal;
 }

@@ -343,

[gem5-dev] Change in gem5/gem5[develop]: arch: Remove unnecessary "typename"s from VecPredRegT.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41998 )



Change subject: arch: Remove unnecessary "typename"s from VecPredRegT.
..

arch: Remove unnecessary "typename"s from VecPredRegT.

Change-Id: If38e71ac79105b111d68df1e572f9a8e32a131ad
---
M src/arch/generic/vec_pred_reg.hh
1 file changed, 5 insertions(+), 5 deletions(-)



diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index e932418..6db0e1e 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -83,14 +83,14 @@

 /// Reset the register to an all-false value.
 template
-typename std::enable_if_t reset() {  
container.reset(); }

+std::enable_if_t reset() { container.reset(); }

 /// Reset the register to an all-true value.
 template
-typename std::enable_if_t set() { container.set(); }
+std::enable_if_t set() { container.set(); }

 template
-typename std::enable_if_t
+std::enable_if_t
 operator=(const MyClass& that)
 {
 container = that.container;
@@ -104,7 +104,7 @@
 }

 template
-typename std::enable_if_t
+std::enable_if_t
 operator[](size_t idx)
 {
 return container[idx * sizeof(VecElem)];
@@ -120,7 +120,7 @@

 /// Write a raw value in an element of the predicate register
 template
-typename std::enable_if_t
+std::enable_if_t
 set_raw(size_t idx, uint8_t val)
 {
 container.set_bits(idx * sizeof(VecElem), sizeof(VecElem), val);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If38e71ac79105b111d68df1e572f9a8e32a131ad
Gerrit-Change-Number: 41998
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: arch,sim: Get rid of unused "Packed" vector predicate registers.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41996 )



Change subject: arch,sim: Get rid of unused "Packed" vector predicate  
registers.

..

arch,sim: Get rid of unused "Packed" vector predicate registers.

Change-Id: Iecff7476bbd775e113788ced469fe85a467feede
---
M src/arch/arm/isa/insts/sve.isa
M src/arch/arm/registers.hh
M src/arch/arm/types.hh
M src/arch/generic/vec_pred_reg.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/registers.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/registers.hh
M src/arch/x86/registers.hh
M src/sim/insttracer.hh
11 files changed, 50 insertions(+), 78 deletions(-)



diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 03775ca..354fe65 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -2396,8 +2396,8 @@
 extraPrologCode = ''
 if isFlagSetting:
 code += '''
-VecPredRegT::Container  
c;
-VecPredRegT  
predOnes(c);

+VecPredRegT::Container c;
+VecPredRegT predOnes(c);
 for (unsigned i = 0; i < eCount; i++) {
 predOnes[i] = 1;
 }
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 62fb0d3..663b83a 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -61,10 +61,8 @@
 using VecRegContainer =
 ::VecRegContainer;

-using VecPredReg = ::VecPredRegT;
-using ConstVecPredReg = ::VecPredRegT;
+using VecPredReg = ::VecPredRegT;
+using ConstVecPredReg = ::VecPredRegT;
 using VecPredRegContainer = VecPredReg::Container;

 // Constants Related to the number of registers
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index fa877be..f2c997f 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -817,7 +817,6 @@

 constexpr unsigned VecRegSizeBytes = MaxSveVecLenInBytes;
 constexpr unsigned VecPredRegSizeBits = MaxSveVecLenInBytes;
-constexpr unsigned VecPredRegHasPackedRepr = false;
 } // namespace ArmISA

 #endif
diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index 84047f6..67ee9e5 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -43,7 +43,7 @@
 #include "arch/generic/vec_reg.hh"
 #include "base/cprintf.hh"

-template 
+template 
 class VecPredRegContainer;

 /// Predicate register view.
@@ -54,32 +54,25 @@
 /// templated on the vector element type to simplify ISA definitions.
 /// @tparam VecElem Type of the vector elements.
 /// @tparam NumElems Number of vector elements making up the view.
-/// @tparam Packed True if the predicate register relies on a packed
-/// representation, i.e. adjacent bits refer to different vector elements
-/// irrespective of the vector element size (e.g. this is the case for
-/// AVX-512). If false, the predicate register relies on an unpacked
-/// representation, where each bit refers to the corresponding byte in a  
vector

-/// register (e.g. this is the case for ARM SVE).
 /// @tparam Const True if the underlying container can be modified through
 /// the view.
-template 
+template 
 class VecPredRegT
 {
   protected:
 /// Size of the register in bits.
-static constexpr size_t NUM_BITS = Packed ? NumElems :
-sizeof(VecElem) * NumElems;
+static constexpr size_t NUM_BITS = sizeof(VecElem) * NumElems;

   public:
 /// Container type alias.
 using Container = typename std::conditional<
 Const,
-const VecPredRegContainer,
-VecPredRegContainer>::type;
+const VecPredRegContainer,
+VecPredRegContainer>::type;

   protected:
 // Alias for this type
-using MyClass = VecPredRegT;
+using MyClass = VecPredRegT;
 /// Container corresponding to this view.
 Container& container;

@@ -88,13 +81,11 @@

 /// Reset the register to an all-false value.
 template
-typename std::enable_if_t
-reset() { container.reset(); }
+typename std::enable_if_t reset() {  
container.reset(); }


 /// Reset the register to an all-true value.
 template
-typename std::enable_if_t
-set() { container.set(); }
+typename std::enable_if_t set() { container.set(); }

 template
 typename std::enable_if_t
@@ -107,14 +98,14 @@
 const bool&
 operator[](size_t idx) const
 {
-return container[idx * (Packed ? 1 : sizeof(VecElem))];
+return container[idx * sizeof(VecElem)];
 }

 template
 typename std::enable_if_t
 operator[](size_t idx)
 {
-return container[idx * (Packed ? 1 : sizeof(VecElem))];
+return container[idx * sizeof(VecElem)];
 }

 /// Return an element of the predicate register as it appears
@@ -122,8 +113,7 @@
 u

[gem5-dev] Change in gem5/gem5[develop]: arch: Collapse unused size parameter from "as" VecPredReg method.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42000 )



Change subject: arch: Collapse unused size parameter from "as" VecPredReg  
method.

..

arch: Collapse unused size parameter from "as" VecPredReg method.

Change-Id: Ibdaf38b2e2d8f37ef76d6b8874ac3620982e78a2
---
M src/arch/generic/vec_pred_reg.hh
1 file changed, 6 insertions(+), 12 deletions(-)



diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index cdf5eb5..86e3b83 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -333,24 +333,18 @@
 /// @tparam VecElem Type of the vector elements.
 /// @tparam NumElems Number of vector elements making up the view.
 /// @{
-template sizeof(VecElem)>

-VecPredRegT
+template 
+VecPredRegT
 as() const
 {
-static_assert(NumBits % sizeof(VecElem) == 0 &&
-  sizeof(VecElem) * NumElems <= NumBits,
-  "Container size incompatible with view size");
-return VecPredRegT(*this);
+return VecPredRegTtrue>(*this);

 }

-template sizeof(VecElem)>

-VecPredRegT
+template 
+VecPredRegT
 as()
 {
-static_assert(NumBits % sizeof(VecElem) == 0 &&
-  sizeof(VecElem) * NumElems <= NumBits,
-  "Container size incompatible with view size");
-return VecPredRegT(*this);
+return VecPredRegTfalse>(*this);

 }
 /// @}
 };

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibdaf38b2e2d8f37ef76d6b8874ac3620982e78a2
Gerrit-Change-Number: 42000
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Stop using << and to_number for VecReg serialization.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41994 )



Change subject: arch,cpu: Stop using << and to_number for VecReg  
serialization.

..

arch,cpu: Stop using << and to_number for VecReg serialization.

Override ParseParam<>::parse and ShowParam<>::parse directly. This will
allow using a different format for serializing and displaying registers.

Also get rid of the print() methods. When any cprintf based mechanism is
used (like DPRINTF), the underlying mechanism will use << to output the
value. Since we already override <<, there's no reason to wrap that in a
method which calls csprintf which calls << anyway.

Change-Id: Id65b9a657507f2f2cdf9673fd961cfeb0590f48c
---
M src/arch/generic/vec_reg.hh
M src/cpu/o3/regfile.hh
M src/cpu/simple_thread.hh
3 files changed, 38 insertions(+), 44 deletions(-)



diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index c8e7938..48cd4bd 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -97,14 +97,13 @@
 #define __ARCH_GENERIC_VEC_REG_HH__

 #include 
-#include 
 #include 
 #include 
 #include 
-#include 

 #include "base/cprintf.hh"
 #include "base/logging.hh"
+#include "sim/serialize_handlers.hh"

 constexpr unsigned MaxVecRegLenInBytes = 4096;

@@ -175,8 +174,6 @@
 return os;
 }

-const std::string print() const { return csprintf("%s", *this); }
-
 /**
  * Cast to VecRegContainer&
  * It is useful to get the reference to the container for ISA tricks,
@@ -211,12 +208,6 @@
   public:
 VecRegContainer() {}
 VecRegContainer(const VecRegContainer &) = default;
-/* This is required for de-serialisation. */
-VecRegContainer(const std::vector& that)
-{
-assert(that.size() >= SIZE);
-std::memcpy(container.data(), [0], SIZE);
-}

 /** Zero the container. */
 void zero() { memset(container.data(), 0, SIZE); }
@@ -239,17 +230,6 @@
 std::memcpy(container.data(), that.data(), SIZE);
 return *this;
 }
-
-/** From vector.
- * This is required for de-serialisation.
- * */
-MyClass&
-operator=(const std::vector& that)
-{
-assert(that.size() >= SIZE);
-std::memcpy(container.data(), that.data(), SIZE);
-return *this;
-}
 /** @} */

 /** Equality operator.
@@ -272,7 +252,6 @@
 return !operator==(that);
 }

-const std::string print() const { return csprintf("%s", *this); }
 /** Get pointer to bytes. */
 template 
 const Ret* raw_ptr() const { return (const Ret*)container.data(); }
@@ -313,19 +292,20 @@
 return VecRegT(*this);
 }

-/** @} */
-/**
- * Output operator.
- * Used for serialization.
- */
 friend std::ostream&
 operator<<(std::ostream& os, const MyClass& v)
 {
 for (auto& b: v.container) {
-os << csprintf("%02x", b);
+ccprintf(os, "%02x", b);
 }
 return os;
 }
+
+/** @} */
+/**
+ * Used for serialization.
+ */
+friend ShowParam;
 };

 /**
@@ -333,20 +313,34 @@
  */
 /** @{ */
 template 
-inline bool
-to_number(const std::string& value, VecRegContainer& v)
+struct ParseParam>
 {
-fatal_if(value.size() > 2 * VecRegContainer::size(),
- "Vector register value overflow at unserialize");
+static bool
+parse(const std::string , VecRegContainer )
+{
+fatal_if(s.size() > 2 * Sz,
+ "Vector register value overflow at unserialize");

-for (int i = 0; i < VecRegContainer::size(); i++) {
-uint8_t b = 0;
-if (2 * i < value.size())
-b = stoul(value.substr(i * 2, 2), nullptr, 16);
-v.template raw_ptr()[i] = b;
+for (int i = 0; i < Sz; i++) {
+uint8_t b = 0;
+if (2 * i < value.size())
+b = stoul(s.substr(i * 2, 2), nullptr, 16);
+value.template raw_ptr()[i] = b;
+}
+return true;
 }
-return true;
-}
+};
+
+template 
+struct ShowParam>
+{
+static void
+show(std::ostream , const VecRegContainer )
+{
+for (auto& b: value.container)
+ccprintf(os, "%02x", b);
+}
+};
 /** @} */

 /**
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 71f2e72..6c6b9b3 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -203,7 +203,7 @@

 DPRINTF(IEW, "RegFile: Access to vector register %i, has "
 "data %s\n", int(phys_reg->index()),
-vectorRegFile[phys_reg->index()].print());
+vectorRegFile[phys_re

[gem5-dev] Change in gem5/gem5[develop]: arch: Break the dependence between (non)-predicate vector regs.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41997 )



Change subject: arch: Break the dependence between (non)-predicate vector  
regs.

..

arch: Break the dependence between (non)-predicate vector regs.

Change-Id: I6c3cd7c1ce9c5d509c332be9bfc107a329f1
---
M src/arch/generic/vec_pred_reg.hh
1 file changed, 5 insertions(+), 6 deletions(-)



diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index 67ee9e5..e932418 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -38,9 +38,11 @@

 #include 
 #include 
+#include 
+#include 
+#include 
 #include 

-#include "arch/generic/vec_reg.hh"
 #include "base/cprintf.hh"

 template 
@@ -372,11 +374,8 @@
 /// Dummy type aliases and constants for architectures that do not  
implement

 /// vector predicate registers.
 /// @{
-using DummyVecPredReg = VecPredRegT;
-using DummyConstVecPredReg = VecPredRegT;
+using DummyVecPredReg = VecPredRegT;
+using DummyConstVecPredReg = VecPredRegT;
 using DummyVecPredRegContainer = DummyVecPredReg::Container;
 constexpr size_t DummyVecPredRegSizeBits = 8;
 /// @}

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6c3cd7c1ce9c5d509c332be9bfc107a329f1
Gerrit-Change-Number: 41997
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: arch: Simplify and correct style of VecReg types.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41993 )



Change subject: arch: Simplify and correct style of VecReg types.
..

arch: Simplify and correct style of VecReg types.

Change-Id: Ib15d2e03c3e9cabcf56b316d5c57d2e892ad255d
---
M src/arch/generic/vec_reg.hh
1 file changed, 23 insertions(+), 63 deletions(-)



diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index 7828108..c8e7938 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -125,12 +125,14 @@
 template 
 class VecRegT
 {
+  private:
 /** Size of the register in bytes. */
 static constexpr inline size_t
 size()
 {
 return sizeof(VecElem) * NumElems;
 }
+
   public:
 /** Container type alias. */
 using Container = typename std::conditional
-typename std::enable_if_t
-zero() { container.zero(); }
-
-template
-typename std::enable_if_t
-operator=(const MyClass& that)
-{
-container = that.container;
-return *this;
-}
-
 /** Index operator. */
-const VecElem& operator[](size_t idx) const
+const VecElem &
+operator[](size_t idx) const
 {
 return container.template raw_ptr()[idx];
 }
@@ -173,25 +163,6 @@
 return container.template raw_ptr()[idx];
 }

-/** Equality operator.
- * Required to compare thread contexts.
- */
-template
-bool
-operator==(const VecRegT& that) const
-{
-return container == that.container;
-}
-/** Inequality operator.
- * Required to compare thread contexts.
- */
-template
-bool
-operator!=(const VecRegT& that) const
-{
-return !operator==(that);
-}
-
 /** Output stream operator. */
 friend std::ostream&
 operator<<(std::ostream& os, const MyClass& vr)
@@ -205,6 +176,7 @@
 }

 const std::string print() const { return csprintf("%s", *this); }
+
 /**
  * Cast to VecRegContainer&
  * It is useful to get the reference to the container for ISA tricks,
@@ -223,10 +195,11 @@
 template 
 class VecRegContainer
 {
-  static_assert(SIZE > 0,
-  "Cannot create Vector Register Container of zero size");
-  static_assert(SIZE <= MaxVecRegLenInBytes,
-  "Vector Register size limit exceeded");
+  private:
+static_assert(SIZE > 0,
+"Cannot create Vector Register Container of zero size");
+static_assert(SIZE <= MaxVecRegLenInBytes,
+"Vector Register size limit exceeded");
   public:
 static constexpr inline size_t size() { return SIZE; };
 using Container = std::array;
@@ -251,16 +224,17 @@
 /** Assignment operators. */
 /** @{ */
 /** From VecRegContainer */
-MyClass& operator=(const MyClass& that)
+MyClass&
+operator=(const MyClass& that)
 {
 if ( == this)
 return *this;
-memcpy(container.data(), that.container.data(), SIZE);
-return *this;
+return *this = that.container;
 }

 /** From appropriately sized uint8_t[]. */
-MyClass& operator=(const Container& that)
+MyClass&
+operator=(const Container& that)
 {
 std::memcpy(container.data(), that.data(), SIZE);
 return *this;
@@ -269,7 +243,8 @@
 /** From vector.
  * This is required for de-serialisation.
  * */
-MyClass& operator=(const std::vector& that)
+MyClass&
+operator=(const std::vector& that)
 {
 assert(that.size() >= SIZE);
 std::memcpy(container.data(), that.data(), SIZE);
@@ -277,24 +252,6 @@
 }
 /** @} */

-/** Copy the contents into the input buffer. */
-/** @{ */
-/** To appropriately sized uint8_t[] */
-void copyTo(Container& dst) const
-{
-std::memcpy(dst.data(), container.data(), SIZE);
-}
-
-/** To vector
- * This is required for serialisation.
- * */
-void copyTo(std::vector& dst) const
-{
-dst.resize(SIZE);
-std::memcpy(dst.data(), container.data(), SIZE);
-}
-/** @} */
-
 /** Equality operator.
  * Required to compare thread contexts.
  */
@@ -335,7 +292,8 @@
  */
 /** @{ */
 template 
-VecRegT as() const
+VecRegT
+as() const
 {
 static_assert(SIZE % sizeof(VecElem) == 0,
 "VecElem does not evenly divide the register size");
@@ -345,7 +303,8 @@
 }

 template 
-VecRegT as()
+VecRegT
+as()
 {
 static_assert(SIZE % sizeof(VecElem) == 0,
 "VecElem does not evenly divide the register size");
@@ -359,7 +318,8 @@
  * Output operator.
  * Used for serialization.
  */
-frie

[gem5-dev] Re: vector register indexing modes and renaming?

2021-02-26 Thread Gabe Black via gem5-dev
Another question/clarification:

Does any data actually get shared between the two rename modes? I think you
said there is not, but now I can't find that. Would it work just as well to
have two register files which operate entirely independently? From what I
can tell the "V" registers of Neon in aarch64 overlap with the SVE
registers, and the "Q" registers of armv7 Neon overlap with the "S", "D",
"Q" registers of the same, but I think "V" and "Q" are independent? Maybe
reused but not guaranteed to alias?

BTW, test cases would be very helpful if possible. I've made good progress
cleaning away debris and am getting to the point where I'll want to make
changes which I'm a lot less comfortable making blind.

Gabe

On Thu, Feb 25, 2021 at 10:40 PM Gabe Black  wrote:

> I will ask within Arm if there's something we can provide to you.
>>> In the meantime I gave a quick look at NEON enabled libraries [1]; the
>>> Ne10 library provides a set of functions optimized for NEON  and a set
>>> of examples making use of it [2] (e.g FIR filter, GEMM etc etc).
>>>
>>> You could probably cross-compile those examples and use them in SE mode
>>> (recommending to use the O3 model)
>>>
>>
>>
>> Ok, thanks, I'll take a look. This might even be something we want in the
>> testing infrastructure? I might look into that when I have a chance.
>>
>
> I took a look at this, and unfortunately I don't think I can use it. The
> example only builds for armv7 and not aarch64, and when I tried to build it
> for armv7 I get a bunch of compiler errors. Do you have any other
> suggestions?
>
> Gabe
>
>>
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[gem5-dev] Re: Upstreaming power-gem5

2021-02-25 Thread Gabe Black via gem5-dev
You can go ahead, Sandipan. Since my series has fairly broad impact, I'm
thinking I'll wait until after the release to check it in.

Gabe

On Thu, Feb 25, 2021 at 12:08 AM Sandipan Das 
wrote:

> Hi Gabe,
>
> On 25/02/21 1:10 pm, Gabe Black wrote:
> > Hi Sandipan. You are correct, except that I would say you don't need to
> > force push, just regular push. If I were at the head of a branch I wanted
> > to (re)upload to gerrit, I would run:
> >
> > git push origin HEAD:refs/for/develop
> >
> > Gerrit will look at the Change-Id field in the commit message and use
> that
> > to identify reviews. If one already exists, it will create a new patchset
> > version (you can look at and compare them in the review UI if you like),
> > and if it doesn't it will make a new review. In the output of the git
> > command it will tell you which ones are new and which ones are updated if
> > you're curious.
> >
> > While it can be mildly disorienting clicking around a series where the
> > ordering of reviews has changed (gerrit tries to go off of the patchset
> > version you're currently looking at), it has no problem keeping track of
> > everything.
> >
>
> Great. Thanks!
> I have made amends for most of the current review comments. As soon as
> your register class related changes are merged, I will rebase my patches
> and push them.
>
> - Sandipan
>
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[gem5-dev] Re: vector register indexing modes and renaming?

2021-02-25 Thread Gabe Black via gem5-dev
>
> I will ask within Arm if there's something we can provide to you.
>> In the meantime I gave a quick look at NEON enabled libraries [1]; the
>> Ne10 library provides a set of functions optimized for NEON  and a set
>> of examples making use of it [2] (e.g FIR filter, GEMM etc etc).
>>
>> You could probably cross-compile those examples and use them in SE mode
>> (recommending to use the O3 model)
>>
>
>
> Ok, thanks, I'll take a look. This might even be something we want in the
> testing infrastructure? I might look into that when I have a chance.
>

I took a look at this, and unfortunately I don't think I can use it. The
example only builds for armv7 and not aarch64, and when I tried to build it
for armv7 I get a bunch of compiler errors. Do you have any other
suggestions?

Gabe

>
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[gem5-dev] Change in gem5/gem5[develop]: arch: Eliminate the "Lane" view of vector registers.

2021-02-25 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41900 )



Change subject: arch: Eliminate the "Lane" view of vector registers.
..

arch: Eliminate the "Lane" view of vector registers.

Nothing uses it.

Change-Id: I1b8a629cfff5c9a58584045ac25424fa8b6dfb24
---
M src/arch/generic/vec_reg.hh
1 file changed, 3 insertions(+), 270 deletions(-)



diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index a647cd8..7828108 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -47,8 +47,8 @@
  * As the (maximum) length of the physical vector register is a  
compile-time

  * constant, it is defined as a template parameter.
  *
- * This file also describes two views of the container that have semantic
- * information about the bytes. The first of this views is VecRegT.
+ * This file also describe one views of the container that has semantic
+ * information about the bytes, the VecRegT.
  *A VecRegT is a view of a VecRegContainer (by reference). The VecRegT  
has

  *a type (VecElem) to which bytes are casted, and the amount of such
  *elements that the vector contains (NumElems). The size of a view,
@@ -56,18 +56,9 @@
  *underlying container. As VecRegT has some degree of type information  
it

  *has vector semantics, and defines the index operator ([]) to get
  *references to particular bytes understood as a VecElem.
- * The second view of a container implemented in this file is VecLaneT,  
which

- * is a view of a subset of the container.
- *A VecLaneT is a view of a lane of a vector register, where a lane is
- *identified by a type (VecElem) and an index (although the view is
- *unaware of its index). Operations on the lane are directly applied to
- *the corresponding bytes of the underlying VecRegContainer through a
- *reference.
  *
  * The intended usage is requesting views to the VecRegContainer via the
- * member 'as' for VecRegT and the member 'laneView' for VecLaneT. Kindly
- * find an example of usage in the following.
- *
+ * member 'as' for VecRegT.
  *
  * // We declare 512 bits vectors
  * using Vec512 = VecRegContainer<64>;
@@ -100,41 +91,6 @@
  *xc->setWriteRegOperand(this, 0, vdstraw);
  * }
  *
- * // Usage example, for a micro op that operates over lane number _lidx:
- * VecFloatLaneAdd(ExecContext* xd) {
- *// Request source vector register to the execution context (const as  
it

- *// is read only).
- *const Vec512& vsrc1raw = xc->readVecRegOperand(this, 0);
- *// View it as a lane of a vector of floats (we could just specify the
- *// first template parametre, the second is derived by the constness  
of

- *// vsrc1raw).
- *VecLaneT& src1 = vsrc1raw->laneView(this->_lidx);
- *
- *// Second source and view
- *const Vec512& vsrc2raw = xc->readVecRegOperand(this, 1);
- *VecLaneT& src2 = vsrc2raw->laneView(this->_lidx);
- *
- *// (Writable) destination and view
- *// As this is a partial write, we need the exec context to support  
that

- *// through, e.g., 'readVecRegOperandToWrite' returning a writable
- *// reference to the register
- *Vec512 vdstraw = xc->readVecRegOperandToWrite(this, 3);
- *VecLaneT& dst = vdstraw->laneView(this->_lidx);
- *
- *dst = src1 + src2;
- *// There is no need to copy the value back into the exec context, as
- *// the assignment to dst modifies the appropriate bytes in vdstraw  
which

- *// is in turn, a reference to the register in the cpu model.
- *// For operations that do conditional writeback, we can decouple the
- *// write by doing:
- *//   auto tmp = src1 + src2;
- *//   if (test) {
- *//   dst = tmp; // do writeback
- *//   } else {
- *//  // do not do writeback
- *//   }
- * }
- *
  */

 #ifndef __ARCH_GENERIC_VEC_REG_HH__
@@ -257,10 +213,6 @@
 operator Container&() { return container; }
 };

-/* Forward declaration. */
-template 
-class VecLaneT;
-
 /**
  * Vector Register Abstraction
  * This generic class is the model in a particularization of MVC, to vector
@@ -402,14 +354,6 @@
 return VecRegT(*this);
 }

-template 
-VecLaneT laneView();
-template 
-VecLaneT laneView() const;
-template 
-VecLaneT laneView(int laneIdx);
-template 
-VecLaneT laneView(int laneIdx) const;
 /** @} */
 /**
  * Output operator.
@@ -424,217 +368,6 @@
 }
 };

-/** We define an auxiliary abstraction for LaneData. The ISA should care
- * about the semantics of a, e.g., 32bit element, treating it as a signed  
or

- * unsigned int, or a float depending on the semantics of a particular
- * instruction. On the other hand, the cpu model should only care about it
- * being a 32-bit value. */
-enum class La

[gem5-dev] Change in gem5/gem5[develop]: cpu: Eliminate the unused "lane" interface from the ThreadContext.

2021-02-25 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41899 )



Change subject: cpu: Eliminate the unused "lane" interface from the  
ThreadContext.

..

cpu: Eliminate the unused "lane" interface from the ThreadContext.

If someone needs to access a component of a vector register, they can do
so through the other interfaces.

Change-Id: Idf1d9b68339eb31b95d4a347548240aa9d2a85cc
---
M src/cpu/checker/thread_context.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
6 files changed, 0 insertions(+), 337 deletions(-)



diff --git a/src/cpu/checker/thread_context.hh  
b/src/cpu/checker/thread_context.hh

index 338e871..661c710 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -249,63 +249,6 @@
 return actualTC->getWritableVecReg(reg);
 }

-/** Vector Register Lane Interfaces. */
-/** @{ */
-/** Reads source vector 8bit operand. */
-ConstVecLane8
-readVec8BitLaneReg(const RegId ) const override
-{
-return actualTC->readVec8BitLaneReg(reg);
-}
-
-/** Reads source vector 16bit operand. */
-ConstVecLane16
-readVec16BitLaneReg(const RegId ) const override
-{
-return actualTC->readVec16BitLaneReg(reg);
-}
-
-/** Reads source vector 32bit operand. */
-ConstVecLane32
-readVec32BitLaneReg(const RegId ) const override
-{
-return actualTC->readVec32BitLaneReg(reg);
-}
-
-/** Reads source vector 64bit operand. */
-ConstVecLane64
-readVec64BitLaneReg(const RegId ) const override
-{
-return actualTC->readVec64BitLaneReg(reg);
-}
-
-/** Write a lane of the destination vector register. */
-virtual void
-setVecLane(const RegId ,
-   const LaneData ) override
-{
-return actualTC->setVecLane(reg, val);
-}
-virtual void
-setVecLane(const RegId ,
-   const LaneData ) override
-{
-return actualTC->setVecLane(reg, val);
-}
-virtual void
-setVecLane(const RegId ,
-   const LaneData ) override
-{
-return actualTC->setVecLane(reg, val);
-}
-virtual void
-setVecLane(const RegId ,
-   const LaneData ) override
-{
-return actualTC->setVecLane(reg, val);
-}
-/** @} */
-
 const TheISA::VecElem &
 readVecElem(const RegId& reg) const override
 {
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 596fa19..73b86af 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -345,37 +345,6 @@
 void vecRenameMode(Enums::VecRegRenameMode vec_mode)
 { vecMode = vec_mode; }

-/**
- * Read physical vector register lane
- */
-template
-VecLaneT
-readVecLane(PhysRegIdPtr phys_reg) const
-{
-cpuStats.vecRegfileReads++;
-return regFile.readVecLane(phys_reg);
-}
-
-/**
- * Read physical vector register lane
- */
-template
-VecLaneT
-readVecLane(PhysRegIdPtr phys_reg) const
-{
-cpuStats.vecRegfileReads++;
-return regFile.readVecLane(phys_reg);
-}
-
-/** Write a lane of the destination vector register. */
-template
-void
-setVecLane(PhysRegIdPtr phys_reg, const LD& val)
-{
-cpuStats.vecRegfileWrites++;
-return regFile.setVecLane(phys_reg, val);
-}
-
 const TheISA::VecElem& readVecElem(PhysRegIdPtr reg_idx) const;

 const TheISA::VecPredRegContainer&
@@ -407,27 +376,6 @@
 /** Read architectural vector register for modification. */
 TheISA::VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID  
tid);


-/** Read architectural vector register lane. */
-template
-VecLaneT
-readArchVecLane(int reg_idx, int lId, ThreadID tid) const
-{
-PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
-RegId(VecRegClass, reg_idx));
-return readVecLane(phys_reg);
-}
-
-
-/** Write a lane of the destination vector register. */
-template
-void
-setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
-{
-PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
-RegId(VecRegClass, reg_idx));
-setVecLane(phys_reg, val);
-}
-
 const TheISA::VecElem& readArchVecElem(const RegIndex& reg_idx,
 const ElemIndex& ldx, ThreadID tid) const;

diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index ec8716b..71f2e72 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -216,36 +216,6 @@
 return const_cast(readVecReg(phys_reg));
 }

-/** Reads a vector register lane. */
-template 
-VecLaneT
-readVecLane(PhysRegIdPtr phys_reg

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Switch the AAPCS ABIs to .as<>() instead of .laneView<>().

2021-02-25 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41898 )



Change subject: arch-arm: Switch the AAPCS ABIs to .as<>() instead  
of .laneView<>().

..

arch-arm: Switch the AAPCS ABIs to .as<>() instead of .laneView<>().

Change-Id: I9e9c7163db4c061af00111b8dc959c364c6b7ae6
---
M src/arch/arm/aapcs32.hh
M src/arch/arm/aapcs64.hh
2 files changed, 6 insertions(+), 6 deletions(-)



diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index a1345bd..c450237 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -463,7 +463,7 @@

 RegId id(VecRegClass, 0);
 auto reg = tc->readVecReg(id);
-reg.laneView() = f;
+reg.as()[0] = f;
 tc->setVecReg(id, reg);
 };
 };
@@ -487,7 +487,7 @@

 RegId id(VecRegClass, reg);
 auto val = tc->readVecReg(id);
-return val.laneView(lane);
+return val.as()[lane];
 }

 return loadFromStack(tc, state);
@@ -558,7 +558,7 @@

 RegId id(VecRegClass, reg);
 auto val = tc->readVecReg(id);
-ha[i] = val.laneView(lane);
+ha[i] = val.as()[lane];
 }
 return ha;
 }
@@ -605,7 +605,7 @@

 RegId id(VecRegClass, reg);
 auto val = tc->readVecReg(id);
-val.laneView(lane) = ha[i];
+val.as()[lane] = ha[i];
 tc->setVecReg(id, val);
 }
 }
diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index fb7b8f8..ddd5606 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -186,7 +186,7 @@
 {
 if (state.nsrn <= state.MAX_SRN) {
 RegId id(VecRegClass, state.nsrn++);
-return tc->readVecReg(id).laneView();
+return tc->readVecReg(id).as()[0];
 }

 return loadFromStack(tc, state);
@@ -203,7 +203,7 @@
 {
 RegId id(VecRegClass, 0);
 auto reg = tc->readVecReg(id);
-reg.laneView() = f;
+reg.as()[0] = f;
 tc->setVecReg(id, reg);
 }
 };

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41898
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9e9c7163db4c061af00111b8dc959c364c6b7ae6
Gerrit-Change-Number: 41898
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch,arch-arm: Eliminate the "zeroing" field of vec reg elements.

2021-02-25 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41895 )



Change subject: arch,arch-arm: Eliminate the "zeroing" field of vec reg  
elements.

..

arch,arch-arm: Eliminate the "zeroing" field of vec reg elements.

This field wasn't used for anything.

Change-Id: I81f38743a7b4f87c56adb8ffeda6f9a096d09842
---
M src/arch/arm/isa/operands.isa
M src/arch/isa_parser/operand_types.py
2 files changed, 80 insertions(+), 80 deletions(-)



diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 0f18ffd..da78561 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -131,8 +131,8 @@
 def vectorReg(idx, elems = None):
 return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)

-def vectorRegElem(elem, ext = 'sf', zeroing = False):
-return (elem, ext, zeroing)
+def vectorRegElem(elem, ext = 'sf'):
+return (elem, ext)

 def vecPredReg(idx):
 return ('VecPredReg', 'pc', idx, None, srtNormal)
@@ -354,9 +354,9 @@
 'AA64FpOp1P1': vectorRegElem('1'),
 'AA64FpOp1P2': vectorRegElem('2'),
 'AA64FpOp1P3': vectorRegElem('3'),
-'AA64FpOp1S':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpOp1D':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpOp1Q':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpOp1S':  vectorRegElem('0', 'sf'),
+'AA64FpOp1D':  vectorRegElem('0', 'df'),
+'AA64FpOp1Q':  vectorRegElem('0', 'tud')
 }),

 'AA64FpOp2':   vectorReg('op2',
@@ -365,9 +365,9 @@
 'AA64FpOp2P1': vectorRegElem('1'),
 'AA64FpOp2P2': vectorRegElem('2'),
 'AA64FpOp2P3': vectorRegElem('3'),
-'AA64FpOp2S':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpOp2D':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpOp2Q':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpOp2S':  vectorRegElem('0', 'sf'),
+'AA64FpOp2D':  vectorRegElem('0', 'df'),
+'AA64FpOp2Q':  vectorRegElem('0', 'tud')
 }),

 'AA64FpOp3':   vectorReg('op3',
@@ -376,9 +376,9 @@
 'AA64FpOp3P1': vectorRegElem('1'),
 'AA64FpOp3P2': vectorRegElem('2'),
 'AA64FpOp3P3': vectorRegElem('3'),
-'AA64FpOp3S':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpOp3D':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpOp3Q':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpOp3S':  vectorRegElem('0', 'sf'),
+'AA64FpOp3D':  vectorRegElem('0', 'df'),
+'AA64FpOp3Q':  vectorRegElem('0', 'tud')
 }),

 'AA64FpDest':   vectorReg('dest',
@@ -387,9 +387,9 @@
 'AA64FpDestP1': vectorRegElem('1'),
 'AA64FpDestP2': vectorRegElem('2'),
 'AA64FpDestP3': vectorRegElem('3'),
-'AA64FpDestS':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpDestD':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpDestQ':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpDestS':  vectorRegElem('0', 'sf'),
+'AA64FpDestD':  vectorRegElem('0', 'df'),
+'AA64FpDestQ':  vectorRegElem('0', 'tud')
 }),

 'AA64FpDest2':   vectorReg('dest2',
@@ -398,9 +398,9 @@
 'AA64FpDest2P1': vectorRegElem('1'),
 'AA64FpDest2P2': vectorRegElem('2'),
 'AA64FpDest2P3': vectorRegElem('3'),
-'AA64FpDest2S':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpDest2D':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpDest2Q':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpDest2S':  vectorRegElem('0', 'sf'),
+'AA64FpDest2D':  vectorRegElem('0', 'df'),
+'AA64FpDest2Q':  vectorRegElem('0', 'tud')
 }),

 'AA64FpOp1V0':   vectorReg('op1',
@@ -409,9 +409,9 @@
 'AA64FpOp1P1V0': vectorRegElem('1'),
 'AA64FpOp1P2V0': vectorRegElem('2'),
 'AA64FpOp1P3V0': vectorRegElem('3'),
-'AA64FpOp1SV0':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpOp1DV0':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpOp1QV0':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpOp1SV0':  vectorRegElem('0', 'sf'),
+'AA64FpOp1DV0':  vectorRegElem('0', 'df'),
+'AA64FpOp1QV0':  vectorRegElem('0', 'tud')
 }),

 'AA64FpOp1V1':   vectorReg('op1+1',
@@ -420,9 +420,9 @@
 'AA64FpOp1P1V1': vectorRegElem('1'),
 'AA64FpOp1P2V1': vectorRegElem('2'),
 'AA64FpOp1P3V1': vectorRegElem('3'),
-'AA64FpOp1SV1':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpOp1DV1':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpOp1QV1':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpOp1SV1':  vectorRegElem('0', 'sf'),
+'AA64FpOp1DV1':  vectorRegElem('0', 'df'),
+'AA64FpOp1QV1':  vec

[gem5-dev] Change in gem5/gem5[develop]: cpu: Remove "lane" accessors from the ExecContext classes.

2021-02-25 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41897 )



Change subject: cpu: Remove "lane" accessors from the ExecContext classes.
..

cpu: Remove "lane" accessors from the ExecContext classes.

These are not used by instructions. If something other than instructions
needs that style of access, it would use the ThreadContext, not the
ExecContext.

Change-Id: Ic74dcfd34f8bb0786bd2688b44d0d90714503637
---
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/simple/exec_context.hh
5 files changed, 0 insertions(+), 316 deletions(-)



diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 42a38fc..0900125 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -218,79 +218,6 @@
 return thread->getWritableVecReg(reg);
 }

-/** Vector Register Lane Interfaces. */
-/** @{ */
-/** Reads source vector 8bit operand. */
-virtual ConstVecLane8
-readVec8BitLaneOperand(const StaticInst *si, int idx) const override
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->readVec8BitLaneReg(reg);
-}
-
-/** Reads source vector 16bit operand. */
-virtual ConstVecLane16
-readVec16BitLaneOperand(const StaticInst *si, int idx) const override
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->readVec16BitLaneReg(reg);
-}
-
-/** Reads source vector 32bit operand. */
-virtual ConstVecLane32
-readVec32BitLaneOperand(const StaticInst *si, int idx) const override
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->readVec32BitLaneReg(reg);
-}
-
-/** Reads source vector 64bit operand. */
-virtual ConstVecLane64
-readVec64BitLaneOperand(const StaticInst *si, int idx) const override
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->readVec64BitLaneReg(reg);
-}
-
-/** Write a lane of the destination vector operand. */
-template 
-void
-setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->setVecLane(reg, val);
-}
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{
-setVecLaneOperandT(si, idx, val);
-}
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{
-setVecLaneOperandT(si, idx, val);
-}
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{
-setVecLaneOperandT(si, idx, val);
-}
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{
-setVecLaneOperandT(si, idx, val);
-}
-/** @} */
-
 TheISA::VecElem
 readVecElemOperand(const StaticInst *si, int idx) const override
 {
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 42dafbc..3c40f31 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -117,36 +117,6 @@
 const TheISA::VecRegContainer& val) = 0;
 /** @} */

-/** Vector Register Lane Interfaces. */
-/** @{ */
-/** Reads source vector 8bit operand. */
-virtual ConstVecLane8 readVec8BitLaneOperand(
-const StaticInst *si, int idx) const = 0;
-
-/** Reads source vector 16bit operand. */
-virtual ConstVecLane16 readVec16BitLaneOperand(
-const StaticInst *si, int idx) const = 0;
-
-/** Reads source vector 32bit operand. */
-virtual ConstVecLane32 readVec32BitLaneOperand(
-const StaticInst *si, int idx) const = 0;
-
-/** Reads source vector 64bit operand. */
-virtual ConstVecLane64 readVec64BitLaneOperand(
-const StaticInst *si, int idx) const = 0;
-
-/** Write a lane of the destination vector operand. */
-/** @{ */
-virtual void setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) = 0;
-virtual void setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) = 0;
-virtual void setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) = 0;
-virtual void setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) = 0;
-/** @} */
-
 /** Vector Elem Interfaces. */
 /** @{ */
 /** Reads an element of a vector register. */
diff --git a/src/cpu/minor/exec_c

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Consolidate defintions of vectorReg operands.

2021-02-25 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41896 )



Change subject: arch-arm: Consolidate defintions of vectorReg operands.
..

arch-arm: Consolidate defintions of vectorReg operands.

Each vectorReg operand defined a set of seven elements which all
followed a very predictable pattern. Since we already have a small
utility function to help generate those definitions, we can just
generate the elements at the same time and save a lot of boilerplate.

Change-Id: I065c6c319612b79c53570b313bf5ad8770796252
---
M src/arch/arm/isa/operands.isa
1 file changed, 36 insertions(+), 278 deletions(-)



diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index da78561..f50144e 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -128,11 +128,17 @@
 def vectorElem(idx, elem):
 return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)

-def vectorReg(idx, elems = None):
-return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
-
-def vectorRegElem(elem, ext = 'sf'):
-return (elem, ext)
+def vectorReg(idx, base, suffix = ''):
+elems = {
+base + 'P0' + suffix : ('0', 'sf'),
+base + 'P1' + suffix : ('1', 'sf'),
+base + 'P2' + suffix : ('2', 'sf'),
+base + 'P3' + suffix : ('3', 'sf'),
+base + 'S' + suffix : ('0', 'sf'),
+base + 'D' + suffix : ('0', 'df'),
+base + 'Q' + suffix : ('0', 'tud')
+}
+return ('VecReg', 'vc', (idx, elems), 'IsVector', srtNormal)

 def vecPredReg(idx):
 return ('VecPredReg', 'pc', idx, None, srtNormal)
@@ -348,281 +354,33 @@
 # All the constituents are hierarchically defined as part of the Vector
 # Register they belong to

-'AA64FpOp1':   vectorReg('op1',
-{
-'AA64FpOp1P0': vectorRegElem('0'),
-'AA64FpOp1P1': vectorRegElem('1'),
-'AA64FpOp1P2': vectorRegElem('2'),
-'AA64FpOp1P3': vectorRegElem('3'),
-'AA64FpOp1S':  vectorRegElem('0', 'sf'),
-'AA64FpOp1D':  vectorRegElem('0', 'df'),
-'AA64FpOp1Q':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp2':   vectorReg('op2',
-{
-'AA64FpOp2P0': vectorRegElem('0'),
-'AA64FpOp2P1': vectorRegElem('1'),
-'AA64FpOp2P2': vectorRegElem('2'),
-'AA64FpOp2P3': vectorRegElem('3'),
-'AA64FpOp2S':  vectorRegElem('0', 'sf'),
-'AA64FpOp2D':  vectorRegElem('0', 'df'),
-'AA64FpOp2Q':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp3':   vectorReg('op3',
-{
-'AA64FpOp3P0': vectorRegElem('0'),
-'AA64FpOp3P1': vectorRegElem('1'),
-'AA64FpOp3P2': vectorRegElem('2'),
-'AA64FpOp3P3': vectorRegElem('3'),
-'AA64FpOp3S':  vectorRegElem('0', 'sf'),
-'AA64FpOp3D':  vectorRegElem('0', 'df'),
-'AA64FpOp3Q':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpDest':   vectorReg('dest',
-{
-'AA64FpDestP0': vectorRegElem('0'),
-'AA64FpDestP1': vectorRegElem('1'),
-'AA64FpDestP2': vectorRegElem('2'),
-'AA64FpDestP3': vectorRegElem('3'),
-'AA64FpDestS':  vectorRegElem('0', 'sf'),
-'AA64FpDestD':  vectorRegElem('0', 'df'),
-'AA64FpDestQ':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpDest2':   vectorReg('dest2',
-{
-'AA64FpDest2P0': vectorRegElem('0'),
-'AA64FpDest2P1': vectorRegElem('1'),
-'AA64FpDest2P2': vectorRegElem('2'),
-'AA64FpDest2P3': vectorRegElem('3'),
-'AA64FpDest2S':  vectorRegElem('0', 'sf'),
-'AA64FpDest2D':  vectorRegElem('0', 'df'),
-'AA64FpDest2Q':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp1V0':   vectorReg('op1',
-{
-'AA64FpOp1P0V0': vectorRegElem('0'),
-'AA64FpOp1P1V0': vectorRegElem('1'),
-'AA64FpOp1P2V0': vectorRegElem('2'),
-'AA64FpOp1P3V0': vectorRegElem('3'),
-'AA64FpOp1SV0':  vectorRegElem('0', 'sf'),
-'AA64FpOp1DV0':  vectorRegElem('0', 'df'),
-'AA64FpOp1QV0':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp1V1':   vectorReg('op1+1',
-{
-'AA64FpOp1P0V1': vectorRegElem('0'),
-'AA64FpOp1P1V1': vectorRegElem('1'),
-'AA64FpOp1P2V1': vectorRegElem('2'),
-'AA64FpOp1P3V1': vectorRegElem('3'),
-'AA64FpOp1SV1':  vectorRegElem('0', 'sf'),
-'AA64FpOp1DV1':  vectorRegElem('0', 'df'),
-'AA64FpOp1QV1':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp1V2':   vectorReg('op1+2',
-{
-'AA64FpOp1P0V2': vectorRegElem('0'),
-'AA64FpOp1P1V2': vectorRegElem('1'),
-'AA64FpOp1P2V2': vectorRegElem('2'),
-'AA64FpOp1P3V2': vectorRegElem('3'),
-'AA64FpOp1SV2':  vectorRegElem('0', 'sf'),
-'AA64FpOp1DV2

[gem5-dev] Re: Upstreaming power-gem5

2021-02-24 Thread Gabe Black via gem5-dev
Hi Sandipan. You are correct, except that I would say you don't need to
force push, just regular push. If I were at the head of a branch I wanted
to (re)upload to gerrit, I would run:

git push origin HEAD:refs/for/develop

Gerrit will look at the Change-Id field in the commit message and use that
to identify reviews. If one already exists, it will create a new patchset
version (you can look at and compare them in the review UI if you like),
and if it doesn't it will make a new review. In the output of the git
command it will tell you which ones are new and which ones are updated if
you're curious.

While it can be mildly disorienting clicking around a series where the
ordering of reviews has changed (gerrit tries to go off of the patchset
version you're currently looking at), it has no problem keeping track of
everything.

Gabe

On Wed, Feb 24, 2021 at 10:18 PM Sandipan Das 
wrote:

> Hello Boris, Gabe,
>
> I think I now have a good amount of changes to address from the initial
> posting of the patch series. In case of mailing list based reviews, we
> would typically post the whole series again with a V2 tag but I guess
> Gerrit tracks changes based on Change-Id.
>
> So as long as the Change-Id is preserved, force pushing the branch with
> revised patches will upload the new revision to Gerrit while still
> preserving all of the historical data such as review comments, etc.
> Is this correct?
>
> I am also planning to add a new patch that splits makeCRField() into
> signed and unsigned variants (like Gabe suggested) and that would now
> be the first patch of the series. Can that create any problems?
>
>
> - Sandipan
>
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[gem5-dev] Change in gem5/gem5[develop]: WIP

2021-02-24 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41894 )



Change subject: WIP
..

WIP

Change-Id: I0ccbd634cc3374d28c0e79ea82cef39f1ba2c141
---
M src/arch/generic/isa.hh
M src/arch/x86/isa.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
9 files changed, 76 insertions(+), 31 deletions(-)



diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 2fc8df4..78303ac 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -45,6 +45,15 @@

 class ThreadContext;

+class RegisterClassInfo
+{
+  protected:
+size_t _size = 0;
+
+  public:
+size_t size() const { return _size; }
+};
+
 class BaseISA : public SimObject
 {
   protected:
@@ -70,6 +79,8 @@
 {
 return initVecRegRenameMode();
 }
+
+const RegisterClassInfo (RegClass reg_class) const =  
0;

 };

 #endif // __ARCH_GENERIC_ISA_HH__
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 5d31d87..a653bbb 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -53,6 +53,16 @@

 std::string vendorString;

+RegisterClassInfo regClassInfo[NumRegClasses] = {
+{ NumIntRegs },
+{ NumFloatRegs },
+{ 1 },
+{ 1 },
+{ 1 },
+{ NumCCRegs },
+{ NUM_MISCREGS }
+};
+
   public:
 void clear();

@@ -115,6 +125,12 @@
 void setThreadContext(ThreadContext *_tc) override;

 std::string getVendorString() const;
+
+const RegisterClassInfo &
+registerClassInfo(RegClass reg_class) const override
+{
+return regClassInfo[reg_class];
+}
 };

 }
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index ed582ad..0f33954 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -168,6 +168,9 @@
 for (ThreadID tid = 0; tid < params.numThreads; tid++) {
 std::string tid_str = std::to_string(tid);

+ThreadContext *tc = cpu.threads[tid]->getTC();
+const int numRegs = ;
+
 /* Input Buffers */
 inputBuffer.push_back(
 InputBuffer(
@@ -175,7 +178,11 @@
 params.executeInputBufferSize));

 /* Scoreboards */
-scoreboard.push_back(Scoreboard(name_ + ".scoreboard" + tid_str));
+scoreboard.emplace_back(name_ + ".scoreboard" + tid_str,
+tc->registerClassInfo(IntRegClass).size(),
+TheISA::NumCCRegs, TheISA::NumFloatRegs,
+TheISA::NumVecRegs, TheISA::NumVecElemPerVecReg,
+TheISA::NumVecPredRegs);

 /* In-flight instruction records */
 executeInfo[tid].inFlightInsts =  new Queue writingInst;

   public:
-Scoreboard(const std::string ) :
+Scoreboard(const std::string ,
+unsigned numIntRegs, unsigned numCcRegs, unsigned numFloatRegs,
+unsigned numVecRegs, unsigned numVecElemPerReg,
+unsigned numVecPredRegs) :
 Named(name),
-numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs +
-TheISA::NumFloatRegs +
-(TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg) +
-TheISA::NumVecPredRegs),
+ccRegOffset(numIntRegs),
+floatRegOffset(ccRegOffset + numCcRegs),
+vecRegOffset(floatRegOffset + numFloatRegs),
+vecPredRegOffset(vecRegOffset + numVecRegs),
+numRegs(numIntRegs + numCcRegs + numFloatRegs +
+(numVecRegs * numVecElemPerReg) + numVecPredRegs),
 numResults(numRegs, 0),
 numUnpredictableResults(numRegs, 0),
 fuIndices(numRegs, 0),
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index f15be91..d293ba0 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -67,6 +67,7 @@
Process *_process, BaseMMU *_mmu,
BaseISA *_isa)
 : ThreadState(_cpu, _thread_num, _process),
+  intRegs(_isa->registerClassInfo(IntRegClass).size()),
   isa(dynamic_cast(_isa)),
   predicate(true), memAccPredicate(true),
   comInstEventQueue("instruction-based event queue"),
@@ -80,6 +81,7 @@
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
BaseMMU *_mmu, BaseISA *_isa)
 : ThreadState(_cpu, _thread_num, NULL),
+  intRegs(_isa->registerClassInfo(IntRegClass).size()),
   isa(dynamic_cast(_isa)),
   predicate(true), memAccPredicate(true),
   comInstEventQueue("instruction-based event queue"),
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 7a13825..9d206b6 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -42,8 +42,6 @@
 #ifndef __CPU_SIMPLE_THREAD_HH__
 #define __CPU_

[gem5-dev] Change in gem5/gem5[develop]: x86: Minor cleanup of the ISA class.

2021-02-24 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41893 )



Change subject: x86: Minor cleanup of the ISA class.
..

x86: Minor cleanup of the ISA class.

Remove namespace indentation, get rid of some unnecessary includes and
class prototypes, and make members consistently private.

Change-Id: If8e6375bf664c125f6776de62aefe44923f73c2e
---
M src/arch/x86/isa.hh
1 file changed, 63 insertions(+), 65 deletions(-)



diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 584933d..5d31d87 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -37,88 +37,86 @@
 #include "arch/x86/regs/misc.hh"
 #include "base/types.hh"
 #include "cpu/reg_class.hh"
-#include "sim/sim_object.hh"

-class Checkpoint;
-class EventManager;
 class ThreadContext;
 struct X86ISAParams;

 namespace X86ISA
 {
-class ISA : public BaseISA
+
+class ISA : public BaseISA
+{
+  private:
+RegVal regVal[NUM_MISCREGS];
+void updateHandyM5Reg(Efer efer, CR0 cr0,
+SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
+
+std::string vendorString;
+
+  public:
+void clear();
+
+using Params = X86ISAParams;
+
+ISA(const Params );
+
+RegVal readMiscRegNoEffect(int miscReg) const;
+RegVal readMiscReg(int miscReg);
+
+void setMiscRegNoEffect(int miscReg, RegVal val);
+void setMiscReg(int miscReg, RegVal val);
+
+RegId
+flattenRegId(const RegId& regId) const
 {
-  protected:
-RegVal regVal[NUM_MISCREGS];
-void updateHandyM5Reg(Efer efer, CR0 cr0,
-SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
-
-  public:
-void clear();
-
-using Params = X86ISAParams;
-
-ISA(const Params );
-
-RegVal readMiscRegNoEffect(int miscReg) const;
-RegVal readMiscReg(int miscReg);
-
-void setMiscRegNoEffect(int miscReg, RegVal val);
-void setMiscReg(int miscReg, RegVal val);
-
-RegId
-flattenRegId(const RegId& regId) const
-{
-switch (regId.classValue()) {
-  case IntRegClass:
-return RegId(IntRegClass, flattenIntIndex(regId.index()));
-  case FloatRegClass:
-return RegId(FloatRegClass,  
flattenFloatIndex(regId.index()));

-  case CCRegClass:
-return RegId(CCRegClass, flattenCCIndex(regId.index()));
-  case MiscRegClass:
-return RegId(MiscRegClass,  
flattenMiscIndex(regId.index()));

-  default:
-break;
-}
-return regId;
+switch (regId.classValue()) {
+  case IntRegClass:
+return RegId(IntRegClass, flattenIntIndex(regId.index()));
+  case FloatRegClass:
+return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+  case CCRegClass:
+return RegId(CCRegClass, flattenCCIndex(regId.index()));
+  case MiscRegClass:
+return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+  default:
+break;
 }
+return regId;
+}

-int flattenIntIndex(int reg) const { return reg & ~IntFoldBit; }
+int flattenIntIndex(int reg) const { return reg & ~IntFoldBit; }

-int
-flattenFloatIndex(int reg) const
-{
-if (reg >= NUM_FLOATREGS) {
-reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
- regVal[MISCREG_X87_TOP]);
-}
-return reg;
+int
+flattenFloatIndex(int reg) const
+{
+if (reg >= NUM_FLOATREGS) {
+reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
+ regVal[MISCREG_X87_TOP]);
 }
+return reg;
+}

-int flattenVecIndex(int reg) const { return reg; }
-int flattenVecElemIndex(int reg) const { return reg; }
-int flattenVecPredIndex(int reg) const { return reg; }
-int flattenCCIndex(int reg) const { return reg; }
-int flattenMiscIndex(int reg) const { return reg; }
+int flattenVecIndex(int reg) const { return reg; }
+int flattenVecElemIndex(int reg) const { return reg; }
+int flattenVecPredIndex(int reg) const { return reg; }
+int flattenCCIndex(int reg) const { return reg; }
+int flattenMiscIndex(int reg) const { return reg; }

-bool
-inUserMode() const override
-{
-HandyM5Reg m5reg = readMiscRegNoEffect(MISCREG_M5_REG);
-return m5reg.cpl == 3;
-}
+bool
+inUserMode() const override
+{
+HandyM5Reg m5reg = readMiscRegNoEffect(MISCREG_M5_REG);
+return m5reg.cpl == 3;
+}

-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
+void serialize(Chec

[gem5-dev] Re: vector register indexing modes and renaming?

2021-02-24 Thread Gabe Black via gem5-dev
On Wed, Feb 24, 2021 at 8:05 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

>
>
> > -Original Message-----
> > From: Gabe Black 
> > Sent: 24 February 2021 15:24
> > To: Giacomo Travaglini 
> > Cc: gem5 Developer List 
> > Subject: Re: [gem5-dev] vector register indexing modes and renaming?
> >
> > So, I started really diving into the interfaces in ThreadContext and
> ExecContext
> > and their various implementations. What I wanted to do was to define a
> much
> > narrower set of maybe 3 virtual functions that actually implements the
> core of
> > what's needed, and not 15-20 different independent virtual methods that
> all
> > need to be reimplemented every time. *That* was quite the rabbit hole,
> and
> > after a number of hours I decided I needed to regroup and come at it from
> > another angle. It definitely looks to me like somebody came in with the
> idea to
> > represent these registers using a data, model, view architecture (or
> something
> > like that) which would make sense in other contexts with other types of
> data,
> > but here I don't think is really the right way to go about this.
> >
> > Right now, I have two questions for you.
> >
> > 1. Are there tests which exercise this stuff? If I start chopping things
> up, I
> > would be a lot more comfortable if I can tell if/when I break something.
>
> I will ask within Arm if there's something we can provide to you.
> In the meantime I gave a quick look at NEON enabled libraries [1]; the
> Ne10 library provides a set of functions optimized for NEON  and a set
> of examples making use of it [2] (e.g FIR filter, GEMM etc etc).
>
> You could probably cross-compile those examples and use them in SE mode
> (recommending to use the O3 model)
>


Ok, thanks, I'll take a look. This might even be something we want in the
testing infrastructure? I might look into that when I have a chance.


>
> > 2. What's the difference between a lane and an element? Those terms seem
> > like they should be synonyms and are treated as almost the same thing,
> but
> > there is clearly a difference between them. What is it, and why does it
> exist?
> >
> > Gabe
> >
>
> I have the hunch the vector lane logic it's not really used.
> My understanding is that Lane/Elem differ in the O3 model only.
> The key point is that VecRegister and VecElems are represented by a
> different set of physical registers; you cannot access a vector element if
> the renaming is set to Full[3]; the physical vector register file will be
> made of valid entries, while the vector element register file will be
> empty. The vector lane getters/setters are probably a way to do a
> functional read of the element anyway [4].
> In a way we could think of VecReg/VecElem as being the interface to the
> vector file for a guest instruction, while the VecLane to be the interface
> for the host (even though it could be used by an instruction as well)
>
> This is my interpretation of the VecLane
>


Ok, thanks. If there are things we can eliminate from the interfaces then
that will make the whole problem simpler. Part of what makes this hard to
work on are that there are so many things that need to move in parallel to
keep everything working (whole registers, elements, lanes, ThreadContext,
ExecContext, SimpleThread, dynamic inst classes, O3 register file and
rename map, minor CPU and O3 scoreboard, parser implementation, operand
definitions, instruction definitions). Finding a place to unravel a small
part of this at a time has been tricky...

Gabe
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[gem5-dev] Re: vector register indexing modes and renaming?

2021-02-24 Thread Gabe Black via gem5-dev
So, I started really diving into the interfaces in ThreadContext and
ExecContext and their various implementations. What I wanted to do was to
define a much narrower set of maybe 3 virtual functions that actually
implements the core of what's needed, and not 15-20 different independent
virtual methods that all need to be reimplemented every time. *That* was
quite the rabbit hole, and after a number of hours I decided I needed to
regroup and come at it from another angle. It definitely looks to me like
somebody came in with the idea to represent these registers using a data,
model, view architecture (or something like that) which would make sense in
other contexts with other types of data, but here I don't think is really
the right way to go about this.

Right now, I have two questions for you.

1. Are there tests which exercise this stuff? If I start chopping things
up, I would be a lot more comfortable if I can tell if/when I break
something.
2. What's the difference between a lane and an element? Those terms seem
like they should be synonyms and are treated as almost the same thing, but
there is clearly a difference between them. What is it, and why does it
exist?

Gabe

On Tue, Feb 23, 2021 at 4:21 AM Gabe Black  wrote:

> That said, the first would avoid adding another register file while that
> would still mean plumbing new interfaces all over the place for all the
> ThreadContext and ExecContexts, etc. Once all that code is generic and you
> can add or remove register files willy-nilly, it might make sense to switch
> to the second option.
>
> Gabe
>
> On Tue, Feb 23, 2021 at 4:15 AM Gabe Black  wrote:
>
>>
>>> > Hey ARM folks. Could someone please explain to me what the deal is
>>> with the
>>> > vector registers and renaming modes? What is fundamentally going on
>>> there?
>>> > My best guess is that the granularity that the registers are being
>>> renamed at
>>> > changes between the modes, or in other words you index by and rename by
>>> > entire registers in one mode, and in the other mode you index by and
>>> rename
>>> > by just the "elements" within the registers?
>>>
>>> Yes that is correct, let me know if you need further info on this
>>>
>>>
>>>
>> Focusing just on this part for now (not to dismiss the other part), this
>> brings me back to an idea in a proposal I sent out a while ago (you
>> commented on it, I think) where there are "normal" register files for
>> integers, etc, which use uint64_ts as entries, and then register files
>> which are for other things which are opaque blobs. Those later register
>> files would be basically an array of bytes with an index scaled by some
>> arbitrary value and sized based on the scale and some register count. The
>> "registers" would be passed around by pointer and cast/copied locally so
>> the accessors can be generic. It sounds like the effect of changing between
>> element/register indexing could be generically implemented by making it
>> possible to reset the scale value for those register files. Another option
>> would be to have two different register files, and then just copy things
>> over to update the new one when switching. That would make the register
>> files themselves simpler, and you have to do something kind of like that
>> anyway to make the elements contiguous when switching from element indexing
>> to register indexing. Which do you think makes more sense? I'm feeling like
>> the second option makes the most sense since it would be easier to
>> implement on the CPU side and would push the part that cares about indexing
>> semantics and what maps equivalently to what into the thing doing the
>> switch which is (presumably) already ISA specific.
>>
>> Gabe
>>
>> Gabe
>>
>
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[gem5-dev] Re: version of pybind11 without everything in the headers

2021-02-23 Thread Gabe Black via gem5-dev
Hey Ciro, any update?

On Mon, Feb 8, 2021 at 5:10 AM Gabe Black  wrote:

> Awesome, it sounds like you've made some great progress. I'm looking
> forward to it!
>
> Gabe
>
> On Mon, Feb 8, 2021 at 2:39 AM Ciro Santilli 
> wrote:
>
>> Gabe,
>>
>> Following a long chain of links from those patches should eventually lead
>> to: https://github.com/pybind/pybind11/pull/2445 passing through
>> https://gem5.atlassian.net/browse/GEM5-572
>>
>> The current status is: upstream has said they will merge my split patch
>> at some point. But since it conflicts with everything, they are waiting for
>> a good moment to do that when their major patches get all merged. Then when
>> tell me to rebase, I'll rebase and they will merge immediately, and then
>> I'll send a patch into gem5 updating pybind11 and updating the build system
>> to take advantage of it.
>>
>> I've been pinging them on major Western holidays :-)
>>
>> --
>> *From:* Giacomo Travaglini 
>> *Sent:* Thursday, February 4, 2021 12:01 PM
>> *To:* gem5 Developer List ; Ciro Santilli <
>> ciro.santi...@arm.com>
>> *Cc:* Gabe Black 
>> *Subject:* RE: [gem5-dev] version of pybind11 without everything in the
>> headers
>>
>> Hi Gabe,
>>
>> I believe you are referring to the following ticket:
>>
>> https://gem5.atlassian.net/browse/GEM5-277
>>
>> Ciro is currently on vacation and he will be back next week so he will be
>> able to update
>> you on his progresses. IIRC pybind folks are reviewing his contribution
>> but I cannot provide
>> you a timeline (Ciro might)
>>
>> Kind Regards
>>
>> Giacomo
>>
>> > -Original Message-
>> > From: Gabe Black via gem5-dev 
>> > Sent: 04 February 2021 09:45
>> > To: gem5 Developer List ; Ciro Santilli
>> > 
>> > Cc: Gabe Black 
>> > Subject: [gem5-dev] version of pybind11 without everything in the
>> headers
>> >
>> > Hey folks and particularly Ciro, I know a while ago there was an
>> attempt to put
>> > the common contents of pybind11 into a lib. Did that go anywhere? That
>> > would reduce build time which would be valuable, but from this change
>> it's
>> > apparent that all those common symbols are *really* blowing up the build
>> > directory.
>> >
>> > https://gem5-review.googlesource.com/c/public/gem5/+/40621/1
>> >
>> >
>> > Gabe
>> IMPORTANT NOTICE: The contents of this email and any attachments are
>> confidential and may also be privileged. If you are not the intended
>> recipient, please notify the sender immediately and do not disclose the
>> contents to any other person, use it for any purpose, or store or copy the
>> information in any medium. Thank you.
>>
>
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[gem5-dev] Change in gem5/gem5[develop]: scons: Create a small helper function for disecting a build target path.

2021-02-23 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40970 )


Change subject: scons: Create a small helper function for disecting a build  
target path.

..

scons: Create a small helper function for disecting a build target path.

This function does about half of the work of the loop which determines
the build root and the list of variants.

Change-Id: I4f44d1e2643244a4be889c677b25b83d41a39b19
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40970
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M SConstruct
M site_scons/gem5_scons/__init__.py
2 files changed, 28 insertions(+), 16 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index b63e2cc..beaf9ae 100755
--- a/SConstruct
+++ b/SConstruct
@@ -124,7 +124,7 @@
   help='Build systemc tests')

 from gem5_scons import Transform, error, warning, summarize_warnings
-from gem5_scons import TempFileSpawn
+from gem5_scons import TempFileSpawn, parse_build_path
 import gem5_scons

 
@@ -182,24 +182,20 @@

 # Generate a list of the unique build roots and configs that the
 # collected targets reference.
-variant_paths = []
+variant_paths = set()
 build_root = None
 for t in BUILD_TARGETS:
-path_dirs = t.split('/')
-try:
-build_top = rfind(path_dirs, 'build', -2)
-except:
-error("No non-leaf 'build' dir found on target path.", t)
-this_build_root = joinpath('/',*path_dirs[:build_top+1])
+this_build_root, variant = parse_build_path(t)
+
+# Make sure all targets use the same build root.
 if not build_root:
 build_root = this_build_root
-else:
-if this_build_root != build_root:
-error("build targets not under same build root\n"
-  "  %s\n  %s" % (build_root, this_build_root))
-variant_path = joinpath('/',*path_dirs[:build_top+2])
-if variant_path not in variant_paths:
-variant_paths.append(variant_path)
+elif this_build_root != build_root:
+error("build targets not under same build root\n  %s\n  %s" %
+(build_root, this_build_root))
+
+# Collect all the variants into a set.
+variant_paths.add(os.path.join('/', build_root, variant))

 # Make sure build_root exists (might not if this is the first build there)
 if not isdir(build_root):
diff --git a/site_scons/gem5_scons/__init__.py  
b/site_scons/gem5_scons/__init__.py

index 5b5777c..6b167af 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -221,4 +221,20 @@
 print_message('Error: ', termcap.Red, message, **kwargs)
 SCons.Script.Exit(1)

-__all__ = ['Configure', 'Transform', 'warning', 'error']
+def parse_build_path(target):
+path_dirs = target.split('/')
+
+# Pop off the target file.
+path_dirs.pop()
+
+# Search backwards for the "build" directory. Whatever was just before  
it

+# was the name of the variant.
+variant_dir = path_dirs.pop()
+while path_dirs and path_dirs[-1] != 'build':
+variant_dir = path_dirs.pop()
+if not path_dirs:
+error("No non-leaf 'build' dir found on target path.", t)
+
+return os.path.join('/', *path_dirs), variant_dir
+
+__all__ = ['Configure', 'Transform', 'warning', 'error', 'parse_build_dir']



8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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[gem5-dev] Change in gem5/gem5[develop]: scons: Eliminate CXX_V and main_dict_keys in SConstruct.

2021-02-23 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40963 )


Change subject: scons: Eliminate CXX_V and main_dict_keys in SConstruct.
..

scons: Eliminate CXX_V and main_dict_keys in SConstruct.

CXX_V isn't used by anything, and main_dict_keys is unnecessary because
using "in" with the whole main environment (which acts like a dict)
checks against the keys without needing a temporary variable.

Change-Id: Iab07246c00b1969858659043cead1dd657b1707b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40963
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 2 insertions(+), 5 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 915c112..b63e2cc 100755
--- a/SConstruct
+++ b/SConstruct
@@ -141,10 +141,8 @@
 from gem5_scons.util import get_termcap
 termcap = get_termcap()

-main_dict_keys = main.Dictionary().keys()
-
 # Check that we have a C/C++ compiler
-if not ('CC' in main_dict_keys and 'CXX' in main_dict_keys):
+if not ('CC' in main and 'CXX' in main):
 error("No C++ compiler installed (package g++ on Ubuntu and RedHat)")

 ###
@@ -302,8 +300,7 @@
 # builds under a given build root run on the same host platform.
 conf = gem5_scons.Configure(main)

-CXX_version = readCommand([main['CXX'],'--version'], exception=False)
-CXX_V = readCommand([main['CXX'],'-V'], exception=False)
+CXX_version = readCommand([main['CXX'], '--version'], exception=False)

 main['GCC'] = CXX_version and CXX_version.find('g++') >= 0
 main['CLANG'] = CXX_version and CXX_version.find('clang') >= 0



7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Change-Number: 40963
Gerrit-PatchSet: 12
Gerrit-Owner: Gabe Black 
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Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Remove an extraneous Exit().

2021-02-23 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40961 )


Change subject: scons: Remove an extraneous Exit().
..

scons: Remove an extraneous Exit().

This isn't necessary after error() which exits on its own.

Change-Id: Icad08c1badc73fa8f41013cc69d6cc5a96ff8fdb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40961
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M SConstruct
1 file changed, 0 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index ed27e58..915c112 100755
--- a/SConstruct
+++ b/SConstruct
@@ -353,7 +353,6 @@
 if compareVersions(main['CXXVERSION'], "5") < 0:
 error('gcc version 5 or newer required.\n'
   'Installed version:', main['CXXVERSION'])
-Exit(1)

 # Add the appropriate Link-Time Optimization (LTO) flags
 # unless LTO is explicitly turned off.



10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Change-Number: 40961
Gerrit-PatchSet: 12
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Enable the clang++ and clang tools.

2021-02-23 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41673 )


Change subject: scons: Enable the clang++ and clang tools.
..

scons: Enable the clang++ and clang tools.

If these tools aren't enabled and CXX isn't set, scons will look for
generically named compiler aliases like cc and c++. These will generally
work, but if scons knows that the compiler is specifically clang, it
will set the CXXCONFIG variable we can use to do compiler version
checking.

Because scons blindly forces a tool into use if you specify it, we need
to use the FindTool method which will check a list of tools and add the
first one that it actually finds.

Change-Id: Ie6bebb8eab531989575c878bee07189541756d2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41673
Reviewed-by: Earl Ou 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 19a5da9..c5dac00 100755
--- a/SConstruct
+++ b/SConstruct
@@ -94,6 +94,7 @@
 import SCons
 import SCons.Node
 import SCons.Node.FS
+import SCons.Tool

 from m5.util import compareVersions, readCommand, readCommandWithReturn

@@ -137,6 +138,9 @@

 main = Environment(tools=['default', 'git', TempFileSpawn])

+main.Tool(SCons.Tool.FindTool(['gcc', 'clang'], main))
+main.Tool(SCons.Tool.FindTool(['g++', 'clang++'], main))
+
 from gem5_scons.util import get_termcap
 termcap = get_termcap()


--
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Gerrit-Change-Number: 41673
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Use SCons' built in CXXVERSION instead of detecting our own.

2021-02-23 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41596 )


Change subject: scons: Use SCons' built in CXXVERSION instead of detecting  
our own.

..

scons: Use SCons' built in CXXVERSION instead of detecting our own.

It's not guaranteed that every compiler will set CXXVERSION, but both
gcc and clang do, and for any check of CXXVERSION to be meaningful, we
have to first check which compiler we're talking about.

Change-Id: Icd15e12832920fec6fa8634bc0fde16cc48e3f41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41596
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M SConstruct
M src/systemc/dt/int/SConscript
2 files changed, 6 insertions(+), 18 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index c5dac00..ed27e58 100755
--- a/SConstruct
+++ b/SConstruct
@@ -79,9 +79,6 @@
 import atexit
 import itertools
 import os
-import re
-import shutil
-import subprocess
 import sys

 from os import mkdir, environ
@@ -353,14 +350,11 @@
   "src/SConscript to support that compiler.")))

 if main['GCC']:
-gcc_version = readCommand([main['CXX'], '-dumpversion'],  
exception=False)

-if compareVersions(gcc_version, "5") < 0:
+if compareVersions(main['CXXVERSION'], "5") < 0:
 error('gcc version 5 or newer required.\n'
-  'Installed version:', gcc_version)
+  'Installed version:', main['CXXVERSION'])
 Exit(1)

-main['GCC_VERSION'] = gcc_version
-
 # Add the appropriate Link-Time Optimization (LTO) flags
 # unless LTO is explicitly turned off.
 if not GetOption('no_lto'):
@@ -387,15 +381,9 @@
   '-fno-builtin-realloc', '-fno-builtin-free'])

 elif main['CLANG']:
-clang_version_re = re.compile(".* version (\d+\.\d+)")
-clang_version_match = clang_version_re.search(CXX_version)
-if (clang_version_match):
-clang_version = clang_version_match.groups()[0]
-if compareVersions(clang_version, "3.9") < 0:
-error('clang version 3.9 or newer required.\n'
-  'Installed version:', clang_version)
-else:
-error('Unable to determine clang version.')
+if compareVersions(main['CXXVERSION'], "3.9") < 0:
+error('clang version 3.9 or newer required.\n'
+  'Installed version:', main['CXXVERSION'])

 # clang has a few additional warnings that we disable, extraneous
 # parantheses are allowed due to Ruby's printing of the AST,
diff --git a/src/systemc/dt/int/SConscript b/src/systemc/dt/int/SConscript
index 92c0f07..b052f04 100644
--- a/src/systemc/dt/int/SConscript
+++ b/src/systemc/dt/int/SConscript
@@ -28,7 +28,7 @@
 from m5.util import compareVersions

 if env['USE_SYSTEMC']:
-if main['GCC'] and compareVersions(main['GCC_VERSION'], '10.0') >= 0:
+if main['GCC'] and compareVersions(main['CXXVERSION'], '10.0') >= 0:
 disable_false_positives = {
 "CCFLAGS": [ "-Wno-array-bounds",
  "-Wno-stringop-overflow" ]



5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Icd15e12832920fec6fa8634bc0fde16cc48e3f41
Gerrit-Change-Number: 41596
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: Design doc for partial rework of instruction execution mechanism

2021-02-23 Thread Gabe Black via gem5-dev
No worries, this will be a big change and will take a while to implement
regardless. I'll probably take a crack at making ISA parser operands either
inputs our outputs exclusively since I think that will be fairly
independent and worth doing on its own.

Gabe

On Tue, Feb 23, 2021 at 11:51 AM Jason Lowe-Power 
wrote:

> Thanks for the effort here, Gabe! I'm excited to dive in.
>
> Just FYI, I will probably not have the bandwidth to deeply look at this
> for at least a few weeks. Between remote teaching and trying to get the
> release out of the door, I'm completely swamped for the near term.
>
> Cheers,
> Jason
>
> On Tue, Feb 23, 2021 at 12:00 AM Gabe Black via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
>> Oh, also, while implementing everything in this new doc would/will be a
>> pretty big undertaking, I think forcing operands in the ISA descriptions to
>> be explicitly sources or destinations but not both would be a major
>> improvement. For most registers that should be pretty trivial (they are
>> already called things like "Dest" or "Src1"), and for the rest the change
>> should just be a lot of find/replace style changes. That could be a first
>> step towards what's in the doc and could be done immediately, independent
>> of anything else.
>>
>> Gabe
>>
>> On Mon, Feb 22, 2021 at 11:57 PM Gabe Black  wrote:
>>
>>> Hey folks.I have a design doc for a moderate in scope but significant in
>>> impact rework of how instruction execution and tracing work in gem5. This
>>> is something I've been thinking about for a while, but threw together just
>>> now to get it out there:
>>>
>>>
>>> https://docs.google.com/document/d/1IqxBYr_arZq5G51oqmXoL5I9HiiwWMQ_t-rvHA78YPE/edit?usp=sharing
>>>
>>> This is strongly informed by an earlier design doc I wrote about how
>>> registers are handled here:
>>>
>>>
>>> https://docs.google.com/document/d/1O_u_Xq14TgreYThuZcbM3kuXFCrKvaFHA2O9poCeHSk/edit#heading=h.r067bn3rmydo
>>>
>>> It is a lot more narrowly scoped though, focusing only on operands and
>>> instruction execution at the StaticInst level, but also extends beyond what
>>> was described in that original doc.
>>>
>>> I'm biased of course, but I think there's a lot of value in reworking
>>> things as described in the doc. Please take a look at let me know what you
>>> think.
>>>
>>> Gabe
>>>
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[gem5-dev] Re: vector register indexing modes and renaming?

2021-02-23 Thread Gabe Black via gem5-dev
That said, the first would avoid adding another register file while that
would still mean plumbing new interfaces all over the place for all the
ThreadContext and ExecContexts, etc. Once all that code is generic and you
can add or remove register files willy-nilly, it might make sense to switch
to the second option.

Gabe

On Tue, Feb 23, 2021 at 4:15 AM Gabe Black  wrote:

>
>> > Hey ARM folks. Could someone please explain to me what the deal is with
>> the
>> > vector registers and renaming modes? What is fundamentally going on
>> there?
>> > My best guess is that the granularity that the registers are being
>> renamed at
>> > changes between the modes, or in other words you index by and rename by
>> > entire registers in one mode, and in the other mode you index by and
>> rename
>> > by just the "elements" within the registers?
>>
>> Yes that is correct, let me know if you need further info on this
>>
>>
>>
> Focusing just on this part for now (not to dismiss the other part), this
> brings me back to an idea in a proposal I sent out a while ago (you
> commented on it, I think) where there are "normal" register files for
> integers, etc, which use uint64_ts as entries, and then register files
> which are for other things which are opaque blobs. Those later register
> files would be basically an array of bytes with an index scaled by some
> arbitrary value and sized based on the scale and some register count. The
> "registers" would be passed around by pointer and cast/copied locally so
> the accessors can be generic. It sounds like the effect of changing between
> element/register indexing could be generically implemented by making it
> possible to reset the scale value for those register files. Another option
> would be to have two different register files, and then just copy things
> over to update the new one when switching. That would make the register
> files themselves simpler, and you have to do something kind of like that
> anyway to make the elements contiguous when switching from element indexing
> to register indexing. Which do you think makes more sense? I'm feeling like
> the second option makes the most sense since it would be easier to
> implement on the CPU side and would push the part that cares about indexing
> semantics and what maps equivalently to what into the thing doing the
> switch which is (presumably) already ISA specific.
>
> Gabe
>
> Gabe
>
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[gem5-dev] Re: vector register indexing modes and renaming?

2021-02-23 Thread Gabe Black via gem5-dev
>
>
> > Hey ARM folks. Could someone please explain to me what the deal is with
> the
> > vector registers and renaming modes? What is fundamentally going on
> there?
> > My best guess is that the granularity that the registers are being
> renamed at
> > changes between the modes, or in other words you index by and rename by
> > entire registers in one mode, and in the other mode you index by and
> rename
> > by just the "elements" within the registers?
>
> Yes that is correct, let me know if you need further info on this
>
>
>
Focusing just on this part for now (not to dismiss the other part), this
brings me back to an idea in a proposal I sent out a while ago (you
commented on it, I think) where there are "normal" register files for
integers, etc, which use uint64_ts as entries, and then register files
which are for other things which are opaque blobs. Those later register
files would be basically an array of bytes with an index scaled by some
arbitrary value and sized based on the scale and some register count. The
"registers" would be passed around by pointer and cast/copied locally so
the accessors can be generic. It sounds like the effect of changing between
element/register indexing could be generically implemented by making it
possible to reset the scale value for those register files. Another option
would be to have two different register files, and then just copy things
over to update the new one when switching. That would make the register
files themselves simpler, and you have to do something kind of like that
anyway to make the elements contiguous when switching from element indexing
to register indexing. Which do you think makes more sense? I'm feeling like
the second option makes the most sense since it would be easier to
implement on the CPU side and would push the part that cares about indexing
semantics and what maps equivalently to what into the thing doing the
switch which is (presumably) already ISA specific.

Gabe

Gabe
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[gem5-dev] vector register indexing modes and renaming?

2021-02-23 Thread Gabe Black via gem5-dev
Hey ARM folks. Could someone please explain to me what the deal is with the
vector registers and renaming modes? What is fundamentally going on there?
My best guess is that the granularity that the registers are being renamed
at changes between the modes, or in other words you index by and rename by
entire registers in one mode, and in the other mode you index by and rename
by just the "elements" within the registers?

Are the "elements" or "lanes" or whatever in the registers fixed in size?
How are these registers organized structurally? I've tried reading the code
for the structures behind them before, but I get lost in the difference
between vector registers, vector register containers, elements, lanes,
predicates, etc etc. I need a big picture of what all these parts are and
how they interrelate.

Also, it's not a *great* sign if in order to understand this supposedly
generic mechanism I need to have knowledge of how vector registers are
implemented in such-and-such extension which is part of ARM. That's not
particularly generic... Although hopefully it could be reworked to be!

Gabe
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[gem5-dev] Re: Design doc for partial rework of instruction execution mechanism

2021-02-23 Thread Gabe Black via gem5-dev
Oh, also, while implementing everything in this new doc would/will be a
pretty big undertaking, I think forcing operands in the ISA descriptions to
be explicitly sources or destinations but not both would be a major
improvement. For most registers that should be pretty trivial (they are
already called things like "Dest" or "Src1"), and for the rest the change
should just be a lot of find/replace style changes. That could be a first
step towards what's in the doc and could be done immediately, independent
of anything else.

Gabe

On Mon, Feb 22, 2021 at 11:57 PM Gabe Black  wrote:

> Hey folks.I have a design doc for a moderate in scope but significant in
> impact rework of how instruction execution and tracing work in gem5. This
> is something I've been thinking about for a while, but threw together just
> now to get it out there:
>
>
> https://docs.google.com/document/d/1IqxBYr_arZq5G51oqmXoL5I9HiiwWMQ_t-rvHA78YPE/edit?usp=sharing
>
> This is strongly informed by an earlier design doc I wrote about how
> registers are handled here:
>
>
> https://docs.google.com/document/d/1O_u_Xq14TgreYThuZcbM3kuXFCrKvaFHA2O9poCeHSk/edit#heading=h.r067bn3rmydo
>
> It is a lot more narrowly scoped though, focusing only on operands and
> instruction execution at the StaticInst level, but also extends beyond what
> was described in that original doc.
>
> I'm biased of course, but I think there's a lot of value in reworking
> things as described in the doc. Please take a look at let me know what you
> think.
>
> Gabe
>
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[gem5-dev] Design doc for partial rework of instruction execution mechanism

2021-02-22 Thread Gabe Black via gem5-dev
Hey folks.I have a design doc for a moderate in scope but significant in
impact rework of how instruction execution and tracing work in gem5. This
is something I've been thinking about for a while, but threw together just
now to get it out there:

https://docs.google.com/document/d/1IqxBYr_arZq5G51oqmXoL5I9HiiwWMQ_t-rvHA78YPE/edit?usp=sharing

This is strongly informed by an earlier design doc I wrote about how
registers are handled here:

https://docs.google.com/document/d/1O_u_Xq14TgreYThuZcbM3kuXFCrKvaFHA2O9poCeHSk/edit#heading=h.r067bn3rmydo

It is a lot more narrowly scoped though, focusing only on operands and
instruction execution at the StaticInst level, but also extends beyond what
was described in that original doc.

I'm biased of course, but I think there's a lot of value in reworking
things as described in the doc. Please take a look at let me know what you
think.

Gabe
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[gem5-dev] Change in gem5/gem5[develop]: scons: Check for "make" when using LTO with gcc.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41773 )


Change subject: scons: Check for "make" when using LTO with gcc.
..

scons: Check for "make" when using LTO with gcc.

gcc uses "make" to parallelize LTO. If we're using gcc and make isn't
found, we have to use single threaded LTO instead. A warning will let
the user know what's happening and that they might want to correct the
situation.

Technically gcc can use the MAKE environment variable to override the
program it uses, although I assume it still has to be "make" compatible.
Given the fairly low likelihood that someone will need that override and
the fact that scons won't pipe that variable through unless we plumb it
up, we'll just ignore that for now.

Change-Id: I891b213ece2a75bd8a915ee91f4130458dab397b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41773
Reviewed-by: Earl Ou 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 12 insertions(+), 2 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index cc3af90..19a5da9 100755
--- a/SConstruct
+++ b/SConstruct
@@ -360,14 +360,24 @@
 # Add the appropriate Link-Time Optimization (LTO) flags
 # unless LTO is explicitly turned off.
 if not GetOption('no_lto'):
+# g++ uses "make" to parallelize LTO. The program can be overriden  
with
+# the environment variable "MAKE", but we currently make no  
attempt to

+# plumb that variable through.
+parallelism = ''
+if main.Detect('make'):
+parallelism = '=%d' % GetOption('num_jobs')
+else:
+warning('"make" not found, link time optimization will be '
+'single threaded.')
+
 # Pass the LTO flag when compiling to produce GIMPLE
 # output, we merely create the flags here and only append
 # them later
-main['LTO_CCFLAGS'] = ['-flto=%d' % GetOption('num_jobs')]
+main['LTO_CCFLAGS'] = ['-flto%s' % parallelism]

 # Use the same amount of jobs for LTO as we are running
 # scons with
-main['LTO_LDFLAGS'] = ['-flto=%d' % GetOption('num_jobs')]
+main['LTO_LDFLAGS'] = ['-flto%s' % parallelism]

  
main.Append(TCMALLOC_CCFLAGS=['-fno-builtin-malloc', '-fno-builtin-calloc',

   '-fno-builtin-realloc', '-fno-builtin-free'])

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I891b213ece2a75bd8a915ee91f4130458dab397b
Gerrit-Change-Number: 41773
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jui-min Lee 
Gerrit-CC: Yu-hsin Wang 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Check for "make" when using LTO with gcc.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41773 )



Change subject: scons: Check for "make" when using LTO with gcc.
..

scons: Check for "make" when using LTO with gcc.

gcc uses "make" to parallelize LTO. If we're using gcc and make isn't
found, we have to use single threaded LTO instead. A warning will let
the user know what's happening and that they might want to correct the
situation.

Technically gcc can use the MAKE environment variable to override the
program it uses, although I assume it still has to be "make" compatible.
Given the fairly low likelihood that someone will need that override and
the fact that scons won't pipe that variable through unless we plumb it
up, we'll just ignore that for now.

Change-Id: I891b213ece2a75bd8a915ee91f4130458dab397b
---
M SConstruct
1 file changed, 12 insertions(+), 2 deletions(-)



diff --git a/SConstruct b/SConstruct
index cc3af90..19a5da9 100755
--- a/SConstruct
+++ b/SConstruct
@@ -360,14 +360,24 @@
 # Add the appropriate Link-Time Optimization (LTO) flags
 # unless LTO is explicitly turned off.
 if not GetOption('no_lto'):
+# g++ uses "make" to parallelize LTO. The program can be overriden  
with
+# the environment variable "MAKE", but we currently make no  
attempt to

+# plumb that variable through.
+parallelism = ''
+if main.Detect('make'):
+parallelism = '=%d' % GetOption('num_jobs')
+else:
+warning('"make" not found, link time optimization will be '
+'single threaded.')
+
 # Pass the LTO flag when compiling to produce GIMPLE
 # output, we merely create the flags here and only append
 # them later
-main['LTO_CCFLAGS'] = ['-flto=%d' % GetOption('num_jobs')]
+main['LTO_CCFLAGS'] = ['-flto%s' % parallelism]

 # Use the same amount of jobs for LTO as we are running
 # scons with
-main['LTO_LDFLAGS'] = ['-flto=%d' % GetOption('num_jobs')]
+main['LTO_LDFLAGS'] = ['-flto%s' % parallelism]

  
main.Append(TCMALLOC_CCFLAGS=['-fno-builtin-malloc', '-fno-builtin-calloc',

   '-fno-builtin-realloc', '-fno-builtin-free'])

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I891b213ece2a75bd8a915ee91f4130458dab397b
Gerrit-Change-Number: 41773
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Create register class descriptors.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41733 )



Change subject: arch,cpu: Create register class descriptors.
..

arch,cpu: Create register class descriptors.

These currently only hold the number of registers in a particular class,
but can be extended in the future to hold other information about each
class. The ISA class holds a vector of descriptors which other parts of
gem5 can retrieve to set up storage for each class, etc.

Currently, the RegClass enum is used to explicitly index into the vector
of descriptors to get information about a particular class. Once enough
information is stored in the descriptors, the other parts of gem5 should
be able to set up for each register class generically, and the ISAs will
be able to leave out or create new register classes without having to
set up global plumbing for it.

The more immediate benefit is that this should (mostly) parameterize
away the ISA register constants to break another TheISA style
dependency. Currently a global set of descriptors are set up in the
BaseISA class using the old TheISA constants, but it should be easy to
break those out and make the ISAs set up their own descriptors. That
will bring arch/registers.hh significantly closer to being eliminated.

Change-Id: I6d6d1256288f880391246b71045482a4a03c4198
---
M src/arch/generic/isa.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/free_list.cc
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/reg_class.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
15 files changed, 249 insertions(+), 167 deletions(-)



diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 4c717c7..8b8b2db 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -40,23 +40,44 @@
 #ifndef __ARCH_GENERIC_ISA_HH__
 #define __ARCH_GENERIC_ISA_HH__

+#include 
+
+#include "arch/registers.hh"
+#include "cpu/reg_class.hh"
 #include "sim/sim_object.hh"

 class ThreadContext;

 class BaseISA : public SimObject
 {
+  public:
+typedef std::vector RegClasses;
+
   protected:
 using SimObject::SimObject;

 ThreadContext *tc = nullptr;

+RegClasses _regClasses = {
+#if THE_ISA != NULL_ISA
+{ TheISA::NumIntRegs },
+{ TheISA::NumFloatRegs },
+{ TheISA::NumVecRegs },
+{ TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg },
+{ TheISA::NumVecPredRegs },
+{ TheISA::NumCCRegs },
+{ TheISA::NumMiscRegs }
+#endif // THE_ISA != NULL_ISA
+};
+
   public:
 virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext  
*old_tc) {}

 virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }

 virtual uint64_t getExecutingAsid() const { return 0; }
 virtual bool inUserMode() const = 0;
+
+const RegClasses () const { return _regClasses; }
 };

 #endif // __ARCH_GENERIC_ISA_HH__
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 3eb7811..7575cf9 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -175,8 +175,10 @@
 name_ + ".inputBuffer" + tid_str, "insts",
 params.executeInputBufferSize));

+const auto  =  
cpu.threads[tid]->getIsaPtr()->regClasses();

+
 /* Scoreboards */
-scoreboard.push_back(Scoreboard(name_ + ".scoreboard" + tid_str));
+scoreboard.emplace_back(name_ + ".scoreboard" + tid_str,  
regClasses);


 /* In-flight instruction records */
 executeInfo[tid].inFlightInsts =  new Queue writingInst;

   public:
-Scoreboard(const std::string ) :
+Scoreboard(const std::string ,
+const BaseISA::RegClasses& reg_classes) :
 Named(name),
-numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs +
-TheISA::NumFloatRegs +
-(TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg) +
-TheISA::NumVecPredRegs),
+regClasses(reg_classes),
+intRegOffset(0),
+floatRegOffset(intRegOffset + reg_classes.at(IntRegClass).size()),
+ccRegOffset(floatRegOffset + reg_classes.at(FloatRegClass).size()),
+vecRegOffset(ccRegOffset + reg_classes.at(CCRegClass).size()),
+vecPredRegOffset(vecRegOffset +  
reg_classes.at(VecElemClass).size()),

+numRegs(vecPredRegOffset + reg_classes.at(VecPredRegClass).size()),
 numResults(numRegs, 0),
 numUnpredictableResults(numRegs, 0),
 fuIndices(numRegs, 0),
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 3b9f991..3cebbf1 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -95,6 +95,7 @@
   params.numPhysVecReg

[gem5-dev] Change in gem5/gem5[develop]: arch: Move setting up RegClassInfos into the arches.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41734 )



Change subject: arch: Move setting up RegClassInfos into the arches.
..

arch: Move setting up RegClassInfos into the arches.

Also remove no longer global constants from arch/registers.hh if they
are no longer used locally.

Change-Id: I1d1589db3dd4c51a5ec11e32348d394261e36d17
---
M src/arch/arm/freebsd/se_workload.hh
M src/arch/arm/htm.cc
M src/arch/arm/htm.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa_device.cc
M src/arch/arm/nativetrace.cc
M src/arch/arm/process.cc
M src/arch/arm/registers.hh
M src/arch/arm/tracers/tarmac_base.cc
M src/arch/arm/tracers/tarmac_record.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/generic/isa.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/mips/registers.hh
M src/arch/mips/utility.cc
M src/arch/power/isa.cc
M src/arch/power/isa.hh
M src/arch/power/isa/includes.isa
M src/arch/power/registers.hh
M src/arch/power/se_workload.hh
M src/arch/power/utility.cc
M src/arch/riscv/isa.cc
M src/arch/riscv/registers.hh
M src/arch/sparc/insts/static_inst.cc
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/isa/includes.isa
M src/arch/sparc/process.cc
M src/arch/sparc/registers.hh
M src/arch/sparc/remote_gdb.cc
M src/arch/sparc/tlb.cc
M src/arch/sparc/utility.cc
M src/arch/sparc/utility.hh
M src/arch/x86/isa.cc
M src/arch/x86/registers.hh
39 files changed, 126 insertions(+), 106 deletions(-)



diff --git a/src/arch/arm/freebsd/se_workload.hh  
b/src/arch/arm/freebsd/se_workload.hh

index a228ee0..6f13201 100644
--- a/src/arch/arm/freebsd/se_workload.hh
+++ b/src/arch/arm/freebsd/se_workload.hh
@@ -34,8 +34,8 @@
 #ifndef __ARCH_ARM_FREEBSD_SE_WORKLOAD_HH__
 #define __ARCH_ARM_FREEBSD_SE_WORKLOAD_HH__

+#include "arch/arm/ccregs.hh"
 #include "arch/arm/freebsd/freebsd.hh"
-#include "arch/arm/registers.hh"
 #include "arch/arm/se_workload.hh"
 #include "params/ArmEmuFreebsd.hh"
 #include "sim/syscall_desc.hh"
diff --git a/src/arch/arm/htm.cc b/src/arch/arm/htm.cc
index 276406a..3129b3f 100644
--- a/src/arch/arm/htm.cc
+++ b/src/arch/arm/htm.cc
@@ -36,6 +36,9 @@
  */

 #include "arch/arm/htm.hh"
+
+#include "arch/arm/intregs.hh"
+#include "arch/arm/miscregs.hh"
 #include "cpu/thread_context.hh"

 void
@@ -70,7 +73,7 @@
 //tme_checkpoint->iccPmrEl1 = tc->readMiscReg(MISCREG_ICC_PMR_EL1);
 nzcv = tc->readMiscReg(MISCREG_NZCV);
 daif = tc->readMiscReg(MISCREG_DAIF);
-for (auto n = 0; n < NumIntArchRegs; n++) {
+for (auto n = 0; n < NUM_ARCH_INTREGS; n++) {
 x[n] = tc->readIntReg(n);
 }
 // TODO first detect if FP is enabled at this EL
@@ -97,7 +100,7 @@
 //tc->setMiscReg(MISCREG_ICC_PMR_EL1, tme_checkpoint->iccPmrEl1);
 tc->setMiscReg(MISCREG_NZCV, nzcv);
 tc->setMiscReg(MISCREG_DAIF, daif);
-for (auto n = 0; n < NumIntArchRegs; n++) {
+for (auto n = 0; n < NUM_ARCH_INTREGS; n++) {
 tc->setIntReg(n, x[n]);
 }
 // TODO first detect if FP is enabled at this EL
diff --git a/src/arch/arm/htm.hh b/src/arch/arm/htm.hh
index 3fa7c1d..d32c58e 100644
--- a/src/arch/arm/htm.hh
+++ b/src/arch/arm/htm.hh
@@ -44,6 +44,7 @@
  * ISA-specific types for hardware transactional memory.
  */

+#include "arch/arm/intregs.hh"
 #include "arch/arm/registers.hh"
 #include "arch/generic/htm.hh"
 #include "base/types.hh"
@@ -70,7 +71,7 @@
   private:
 uint8_t rt; // TSTART destination register
 Addr nPc; // Fallback instruction address
-std::array x; // General purpose registers
+std::array x; // General purpose registers
 std::array z; // Vector registers
 std::array p; // Predicate registers
 Addr sp; // Stack Pointer at current EL
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index c7f82e0..039224f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -47,6 +47,7 @@
 #include "arch/arm/tlbi_op.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
+#include "cpu/reg_class.hh"
 #include "debug/Arm.hh"
 #include "debug/MiscRegs.hh"
 #include "dev/arm/generic_timer.hh"
@@ -65,6 +66,16 @@
 pmu(p.pmu), impdefAsNop(p.impdef_nop),
 afterStartup(false)
 {
+_regClasses.insert(_regClasses.end(), {
+{ NUM_INTREGS },
+{ 0 },
+{ NumVecRegs },
+{ NumVecRegs * TheISA::NumVecElemPerVecReg },
+{ NumVecPredRegs },
+{ NUM_CCREGS },
+{ NUM_MISCREGS }
+});
+
 miscRegs[MISCREG_SCTLR_RST] = 0;

 // Hook up a dummy device if we haven't been configured with a
@@ -484,7 +495,7 @@
 RegVal
 ISA:

[gem5-dev] Change in gem5/gem5[develop]: arch-sparc: Move non-public values out of registers.hh.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41741 )



Change subject: arch-sparc: Move non-public values out of registers.hh.
..

arch-sparc: Move non-public values out of registers.hh.

Change-Id: If5f1c09b3988bc009821330ca128ff22a54c0e88
---
M src/arch/sparc/decoder.hh
M src/arch/sparc/faults.cc
M src/arch/sparc/insts/static_inst.cc
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/isa/includes.isa
M src/arch/sparc/linux/linux.hh
M src/arch/sparc/nativetrace.cc
M src/arch/sparc/process.cc
M src/arch/sparc/registers.hh
A src/arch/sparc/regs/float.hh
A src/arch/sparc/regs/int.hh
R src/arch/sparc/regs/misc.hh
M src/arch/sparc/remote_gdb.cc
M src/arch/sparc/se_workload.cc
M src/arch/sparc/se_workload.hh
M src/arch/sparc/tlb.cc
M src/arch/sparc/ua2005.cc
M src/arch/sparc/utility.cc
M src/arch/sparc/utility.hh
21 files changed, 153 insertions(+), 67 deletions(-)



diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh
index ece3b9c..6e2e203 100644
--- a/src/arch/sparc/decoder.hh
+++ b/src/arch/sparc/decoder.hh
@@ -31,7 +31,6 @@

 #include "arch/generic/decode_cache.hh"
 #include "arch/generic/decoder.hh"
-#include "arch/sparc/registers.hh"
 #include "arch/sparc/types.hh"
 #include "cpu/static_inst.hh"
 #include "debug/Decode.hh"
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index a80e649..408c5c4 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -33,6 +33,7 @@
 #include "arch/sparc/mmu.hh"
 #include "arch/sparc/process.hh"
 #include "arch/sparc/se_workload.hh"
+#include "arch/sparc/sparc_traits.hh"
 #include "arch/sparc/types.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
diff --git a/src/arch/sparc/insts/static_inst.cc  
b/src/arch/sparc/insts/static_inst.cc

index 65a38ff..72e4c6b 100644
--- a/src/arch/sparc/insts/static_inst.cc
+++ b/src/arch/sparc/insts/static_inst.cc
@@ -29,8 +29,8 @@

 #include "arch/sparc/insts/static_inst.hh"

-#include "arch/sparc/miscregs.hh"
-#include "arch/sparc/registers.hh"
+#include "arch/sparc/regs/int.hh"
+#include "arch/sparc/regs/misc.hh"
 #include "base/bitunion.hh"

 namespace SparcISA
diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh
index 18646fa..cd1e5dc 100644
--- a/src/arch/sparc/interrupts.hh
+++ b/src/arch/sparc/interrupts.hh
@@ -32,8 +32,7 @@
 #include "arch/generic/interrupts.hh"
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/miscregs.hh"
-#include "arch/sparc/registers.hh"
+#include "arch/sparc/regs/misc.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Interrupt.hh"
 #include "params/SparcInterrupts.hh"
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 12e2908..6fe79be 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -31,7 +31,10 @@
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/decoder.hh"
 #include "arch/sparc/interrupts.hh"
-#include "arch/sparc/miscregs.hh"
+#include "arch/sparc/regs/float.hh"
+#include "arch/sparc/regs/int.hh"
+#include "arch/sparc/regs/misc.hh"
+#include "arch/sparc/sparc_traits.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 2d75b0a..54cd763 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -33,7 +33,9 @@
 #include 

 #include "arch/generic/isa.hh"
-#include "arch/sparc/miscregs.hh"
+#include "arch/sparc/regs/int.hh"
+#include "arch/sparc/regs/misc.hh"
+#include "arch/sparc/sparc_traits.hh"
 #include "arch/sparc/types.hh"
 #include "cpu/reg_class.hh"
 #include "sim/sim_object.hh"
diff --git a/src/arch/sparc/isa/includes.isa  
b/src/arch/sparc/isa/includes.isa

index c2c44a7..679ddf3 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -47,8 +47,8 @@
 #include "arch/sparc/insts/unimp.hh"
 #include "arch/sparc/insts/unknown.hh"
 #include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/miscregs.hh"
-#include "arch/sparc/registers.hh"
+#include "arch/sparc/regs/int.hh"
+#include "arch/sparc/regs/misc.hh"
 #include "base/condcodes.hh"
 #include "base/logging.hh"
 #include "cpu/static_inst.hh"
diff --git a/src/arch/sparc/linux/linux.hh b/src/arch/sparc/linux/linux.hh
index 431ec06..8d43c91 

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Pull everything not purely public out of registers.hh.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41738 )



Change subject: arch-arm: Pull everything not purely public out of  
registers.hh.

..

arch-arm: Pull everything not purely public out of registers.hh.

There are currently only two types of values exported from registers.hh,
vector register definitions, and the zero reg index. The ZeroReg
constant is still defined in registers.hh. The vector register
information has been moved into a new file called arch/arm/regs/vec.hh
since it's used internally by the ISA itself, and then included in
registers.hh so it can be consumed externally too.

Change-Id: I31d8dd5bcb21818efa32ccc42f26b0e598a2c88e
---
M src/arch/arm/registers.hh
M src/arch/arm/regs/int.hh
A src/arch/arm/regs/vec.hh
3 files changed, 112 insertions(+), 61 deletions(-)



diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 15a84a5..8d5cfdf 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -42,73 +42,13 @@
 #define __ARCH_ARM_REGISTERS_HH__

 #include "arch/arm/regs/int.hh"
-#include "arch/generic/vec_pred_reg.hh"
-#include "arch/generic/vec_reg.hh"
+#include "arch/arm/regs/vec.hh"

 namespace ArmISA
 {

-// Number of VecElem per Vector Register considering only pre-SVE
-// Advanced SIMD registers.
-constexpr unsigned NumVecElemPerNeonVecReg = 4;
-// Number of VecElem per Vector Register, computed based on the vector  
length

-constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords;
-
-using VecElem = uint32_t;
-using VecReg = ::VecRegT;
-using ConstVecReg = ::VecRegT;
-using VecRegContainer = VecReg::Container;
-
-using VecPredReg = ::VecPredRegT;
-using ConstVecPredReg = ::VecPredRegT;
-using VecPredRegContainer = VecPredReg::Container;
-
-// Vec, PredVec
-// NumFloatV7ArchRegs: This in theory should be 32.
-// However in A32 gem5 is splitting double register accesses in two
-// subsequent single register ones. This means we would use a index
-// bigger than 31 when accessing D16-D31.
-const int NumFloatV7ArchRegs = 64; // S0-S31, D0-D31
-const int NumVecV7ArchRegs  = 16; // Q0-Q15
-const int NumVecV8ArchRegs  = 32; // V0-V31
-const int NumVecSpecialRegs = 8;
-const int NumVecIntrlvRegs = 4;
-const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs +  
NumVecIntrlvRegs;

-const int NumVecPredRegs = 18;  // P0-P15, FFR, UREG0
-
-// Semantically meaningful register indices
-const int ReturnValueReg = 0;
-const int ReturnValueReg1 = 1;
-const int ReturnValueReg2 = 2;
-const int NumArgumentRegs = 4;
-const int NumArgumentRegs64 = 8;
-const int ArgumentReg0 = 0;
-const int ArgumentReg1 = 1;
-const int ArgumentReg2 = 2;
-const int ArgumentReg3 = 3;
-const int FramePointerReg = 11;
-const int StackPointerReg = INTREG_SP;
-const int ReturnAddressReg = INTREG_LR;
-const int PCReg = INTREG_PC;
-
 const int ZeroReg = INTREG_ZERO;

-// Vec, PredVec indices
-const int VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg;
-const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs;
-const int INTRLVREG1 = INTRLVREG0 + 1;
-const int INTRLVREG2 = INTRLVREG0 + 2;
-const int INTRLVREG3 = INTRLVREG0 + 3;
-const int VECREG_UREG0 = 32;
-const int PREDREG_FFR = 16;
-const int PREDREG_UREG0 = 17;
-
-const int SyscallNumReg = ReturnValueReg;
-const int SyscallPseudoReturnReg = ReturnValueReg;
-const int SyscallSuccessReg = ReturnValueReg;
-
 } // namespace ArmISA

 #endif
diff --git a/src/arch/arm/regs/int.hh b/src/arch/arm/regs/int.hh
index 9f3b5fd..af11993 100644
--- a/src/arch/arm/regs/int.hh
+++ b/src/arch/arm/regs/int.hh
@@ -517,6 +517,25 @@
 return reg == INTREG_SPX;
 }

+// Semantically meaningful register indices
+const int ReturnValueReg = 0;
+const int ReturnValueReg1 = 1;
+const int ReturnValueReg2 = 2;
+const int NumArgumentRegs = 4;
+const int NumArgumentRegs64 = 8;
+const int ArgumentReg0 = 0;
+const int ArgumentReg1 = 1;
+const int ArgumentReg2 = 2;
+const int ArgumentReg3 = 3;
+const int FramePointerReg = 11;
+const int StackPointerReg = INTREG_SP;
+const int ReturnAddressReg = INTREG_LR;
+const int PCReg = INTREG_PC;
+
+const int SyscallNumReg = ReturnValueReg;
+const int SyscallPseudoReturnReg = ReturnValueReg;
+const int SyscallSuccessReg = ReturnValueReg;
+
 }

 #endif
diff --git a/src/arch/arm/regs/vec.hh b/src/arch/arm/regs/vec.hh
new file mode 100644
index 000..f00b2db
--- /dev/null
+++ b/src/arch/arm/regs/vec.hh
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2010-2011, 2014, 2016-2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Clean up new FP code in arch/registers.hh.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41735 )



Change subject: arch-riscv: Clean up new FP code in arch/registers.hh.
..

arch-riscv: Clean up new FP code in arch/registers.hh.

Delete unused macros, turn macros into inline functions, simplify them,
comment them, replace custom sign extension with the bitfield.hh
version.

Change-Id: I5962c1f0ac62245385052082e5897e14e4b5adf1
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/registers.hh
2 files changed, 60 insertions(+), 70 deletions(-)



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index b4cda8f..90ea03d 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -909,7 +909,8 @@
 freg_t fd;
 fd = freg(f32_mulAdd(f32(freg(Fs1_bits)),
 f32(freg(Fs2_bits)),
-f32(f32(freg(Fs3_bits)).v ^  
F32_SIGN)));

+f32(f32(freg(Fs3_bits)).v ^
+mask(31, 31;
 Fd_bits = fd.v;
 }}, FloatMultAccOp);
 0x1: fmsub_d({{
@@ -917,7 +918,8 @@
 freg_t fd;
 fd = freg(f64_mulAdd(f64(freg(Fs1_bits)),
 f64(freg(Fs2_bits)),
-f64(f64(freg(Fs3_bits)).v ^  
F64_SIGN)));

+f64(f64(freg(Fs3_bits)).v ^
+mask(63, 63;
 Fd_bits = fd.v;
 }}, FloatMultAccOp);
 }
@@ -925,7 +927,8 @@
 0x0: fnmsub_s({{
 RM_REQUIRED;
 freg_t fd;
-fd = freg(f32_mulAdd(f32(f32(freg(Fs1_bits)).v ^  
F32_SIGN),

+fd = freg(f32_mulAdd(f32(f32(freg(Fs1_bits)).v ^
+ mask(31, 31)),
  f32(freg(Fs2_bits)),
  f32(freg(Fs3_bits;
 Fd_bits = fd.v;
@@ -933,7 +936,8 @@
 0x1: fnmsub_d({{
 RM_REQUIRED;
 freg_t fd;
-fd = freg(f64_mulAdd(f64(f64(freg(Fs1_bits)).v ^  
F64_SIGN),

+fd = freg(f64_mulAdd(f64(f64(freg(Fs1_bits)).v ^
+ mask(63, 63)),
  f64(freg(Fs2_bits)),
  f64(freg(Fs3_bits;
 Fd_bits = fd.v;
@@ -943,17 +947,21 @@
 0x0: fnmadd_s({{
 RM_REQUIRED;
 freg_t fd;
-fd = freg(f32_mulAdd(f32(f32(freg(Fs1_bits)).v ^  
F32_SIGN),

+fd = freg(f32_mulAdd(f32(f32(freg(Fs1_bits)).v ^
+ mask(31, 31)),
 f32(freg(Fs2_bits)),
-f32(f32(freg(Fs3_bits)).v ^  
F32_SIGN)));

+f32(f32(freg(Fs3_bits)).v ^
+mask(31, 31;
 Fd_bits = fd.v;
 }}, FloatMultAccOp);
 0x1: fnmadd_d({{
 RM_REQUIRED;
 freg_t fd;
-fd = freg(f64_mulAdd(f64(f64(freg(Fs1_bits)).v ^  
F64_SIGN),

+fd = freg(f64_mulAdd(f64(f64(freg(Fs1_bits)).v ^
+ mask(63, 63)),
 f64(freg(Fs2_bits)),
-f64(f64(freg(Fs3_bits)).v ^  
F64_SIGN)));

+f64(f64(freg(Fs3_bits)).v ^
+mask(63, 63;
 Fd_bits = fd.v;
 }}, FloatMultAccOp);
 }
@@ -1016,42 +1024,26 @@
 }}, FloatDivOp);
 0x10: decode ROUND_MODE {
 0x0: fsgnj_s({{
-freg_t fd;
-fd = freg(fsgnj32(freg(Fs1_bits), freg(Fs2_bits),
-  false, false));
-Fd_bits = fd.v;
+Fd_bits = insertBits(Fs1_bits, 31, Fs2_bits);
 }}, FloatMiscOp);
 0x1: fsgnjn_s({{
-freg_t fd;
-fd = freg(fsgnj32(freg(Fs1_bits), freg(Fs2_bits),
-  true, false));
-Fd_bits = fd.v;
+Fd_bits = insertBits(Fs1_bits, 31, ~Fs2_bits);
 }}, FloatMiscOp);
 0x2: fsgnjx_s

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Move (most) non-public values out of registers.hh.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41742 )



Change subject: arch-x86: Move (most) non-public values out of registers.hh.
..

arch-x86: Move (most) non-public values out of registers.hh.

The unnecessary DependenceTags is already being removed by another
pending change, and so is left in place for that to remove. Once that's
happened, the regs/*.hh includes can be removed, and there may be other
include related tangles to sort out.

Change-Id: I1c02aa8fd2f2045017609b70523b3519c2a92b03
---
M src/arch/x86/linux/linux.hh
M src/arch/x86/process.cc
M src/arch/x86/registers.hh
M src/arch/x86/regs/float.hh
M src/arch/x86/regs/int.hh
M src/arch/x86/utility.cc
6 files changed, 20 insertions(+), 19 deletions(-)



diff --git a/src/arch/x86/linux/linux.hh b/src/arch/x86/linux/linux.hh
index 697892c..5b46aa1 100644
--- a/src/arch/x86/linux/linux.hh
+++ b/src/arch/x86/linux/linux.hh
@@ -62,7 +62,7 @@
 }

 if (stack)
-ctc->setIntReg(X86ISA::StackPointerReg, stack);
+ctc->setIntReg(X86ISA::INTREG_RSP, stack);
 }

 class SyscallABI {};
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 925c836..cb69af9 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -978,7 +978,7 @@

 ThreadContext *tc = system->threads[contextIds[0]];
 // Set the stack pointer register
-tc->setIntReg(StackPointerReg, stack_min);
+tc->setIntReg(INTREG_RSP, stack_min);

 // There doesn't need to be any segment base added in since we're  
dealing

 // with the flat segmentation model.
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 572fa3d..e7c1d9f 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -41,23 +41,14 @@

 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/x86/regs/int.hh"
 #include "arch/x86/regs/ccr.hh"
+#include "arch/x86/regs/float.hh"
+#include "arch/x86/regs/int.hh"
 #include "arch/x86/regs/misc.hh"
-#include "arch/x86/x86_traits.hh"

 namespace X86ISA
 {

-const int NumIntArchRegs = NUM_INTREGS;
-const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs +  
NumImplicitIntRegs;

-const int NumCCRegs = NUM_CCREGS;
-
-// Each 128 bit xmm register is broken into two effective 64 bit registers.
-// Add 8 for the indices that are mapped over the fp stack
-const int NumFloatRegs =
-NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
-
 // These enumerate all the registers for dependence tracking.
 enum DependenceTags {
 // FP_Reg_Base must be large enough to be bigger than any integer
@@ -65,14 +56,12 @@
 // we just start at (1 << 7) == 128.
 FP_Reg_Base = 128,
 CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
-Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
+Misc_Reg_Base = CC_Reg_Base + NUM_CCREGS,
 Max_Reg_Index = Misc_Reg_Base + NUM_MISCREGS
 };

-// semantically meaningful register indices
-//There is no such register in X86
+// There is no such register in X86.
 const int ZeroReg = NUM_INTREGS;
-const int StackPointerReg = INTREG_RSP;

 // Not applicable to x86
 using VecElem = ::DummyVecElem;
diff --git a/src/arch/x86/regs/float.hh b/src/arch/x86/regs/float.hh
index 6cba603..963c111 100644
--- a/src/arch/x86/regs/float.hh
+++ b/src/arch/x86/regs/float.hh
@@ -148,6 +148,11 @@
 {
 return FLOATREG_FPR((top + index + 8) % 8);
 }
+
+// Each 128 bit xmm register is broken into two effective 64 bit  
registers.

+// Add 8 for the indices that are mapped over the fp stack
+const int NumFloatRegs =
+NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
 }

 #endif // __ARCH_X86_FLOATREGS_HH__
diff --git a/src/arch/x86/regs/int.hh b/src/arch/x86/regs/int.hh
index aa26224..87b3190 100644
--- a/src/arch/x86/regs/int.hh
+++ b/src/arch/x86/regs/int.hh
@@ -169,6 +169,10 @@
 index = (index - 4) | foldBit;
 return (IntRegIndex)index;
 }
+
+const int NumIntArchRegs = NUM_INTREGS;
+const int NumIntRegs =
+NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
 }

 #endif // __ARCH_X86_INTREGS_HH__
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index c664620..2872557 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -40,7 +40,10 @@

 #include "arch/x86/interrupts.hh"
 #include "arch/x86/mmu.hh"
-#include "arch/x86/registers.hh"
+#include "arch/x86/regs/ccr.hh"
+#include "arch/x86/regs/float.hh"
+#include "arch/x86/regs/int.hh"
+#include "arch/x86/regs/misc.hh"
 #include "arch/x86/x86_traits.hh"
 #include "cpu/base.hh"
 #include "fputils/fp80.h"
@@ -79,7 +82,7 @@
 for (int i = 0; i < NumFlo

[gem5-dev] Change in gem5/gem5[develop]: arch-mips: Pull non-public values out of registers.hh.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41739 )



Change subject: arch-mips: Pull non-public values out of registers.hh.
..

arch-mips: Pull non-public values out of registers.hh.

Change-Id: Ia15c75547e74bf2f784fac5b3063159e0c79a00c
---
M src/arch/mips/faults.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/mips/isa/includes.isa
M src/arch/mips/locked_mem.hh
M src/arch/mips/mt.hh
M src/arch/mips/process.cc
M src/arch/mips/registers.hh
A src/arch/mips/regs/float.hh
A src/arch/mips/regs/int.hh
A src/arch/mips/regs/misc.hh
M src/arch/mips/remote_gdb.cc
M src/arch/mips/remote_gdb.hh
M src/arch/mips/se_workload.hh
M src/arch/mips/utility.cc
M src/arch/mips/utility.hh
16 files changed, 364 insertions(+), 230 deletions(-)



diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 68ba6b6..8df1c5d 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -31,6 +31,7 @@
 #define __MIPS_FAULTS_HH__

 #include "arch/mips/pra_constants.hh"
+#include "arch/mips/regs/misc.hh"
 #include "cpu/thread_context.hh"
 #include "debug/MipsPRA.hh"
 #include "sim/faults.hh"
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 98dab66..3e4bb1e 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -31,6 +31,9 @@
 #include "arch/mips/mt.hh"
 #include "arch/mips/mt_constants.hh"
 #include "arch/mips/pra_constants.hh"
+#include "arch/mips/regs/float.hh"
+#include "arch/mips/regs/int.hh"
+#include "arch/mips/regs/misc.hh"
 #include "base/bitfield.hh"
 #include "cpu/base.hh"
 #include "cpu/reg_class.hh"
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index e2468ce..7805ea7 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -34,15 +34,15 @@
 #include 

 #include "arch/generic/isa.hh"
-#include "arch/mips/registers.hh"
+#include "arch/mips/regs/misc.hh"
 #include "arch/mips/types.hh"
+#include "base/types.hh"
 #include "cpu/reg_class.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"

 class BaseCPU;
 class Checkpoint;
-class EventManager;
 struct MipsISAParams;
 class ThreadContext;

diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index d17bcf6..dd0a1e9 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -55,6 +55,9 @@
 #include "arch/mips/mt_constants.hh"
 #include "arch/mips/pagetable.hh"
 #include "arch/mips/pra_constants.hh"
+#include "arch/mips/regs/float.hh"
+#include "arch/mips/regs/int.hh"
+#include "arch/mips/regs/misc.hh"
 #include "arch/mips/tlb.hh"
 #include "arch/mips/utility.hh"
 #include "base/cprintf.hh"
@@ -79,6 +82,9 @@
 #include "arch/mips/mt_constants.hh"
 #include "arch/mips/pagetable.hh"
 #include "arch/mips/pra_constants.hh"
+#include "arch/mips/regs/float.hh"
+#include "arch/mips/regs/int.hh"
+#include "arch/mips/regs/misc.hh"
 #include "arch/mips/tlb.hh"
 #include "arch/mips/utility.hh"
 #include "base/condcodes.hh"
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 73180af..42a4ed2 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -47,7 +47,7 @@
  * ISA-specific helper functions for locked memory accesses.
  */

-#include "arch/mips/registers.hh"
+#include "arch/mips/regs/misc.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index 9ab3290..56099da 100644
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -41,7 +41,7 @@
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/mt_constants.hh"
 #include "arch/mips/pra_constants.hh"
-#include "arch/mips/registers.hh"
+#include "arch/mips/regs/misc.hh"
 #include "base/bitfield.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index e2f2bb9..ec1270a 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -29,6 +29,7 @@
 #include "arch/mips/process.hh"

 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/regs/int.hh"
 #include "base/loader/elf_object.hh"
 #include "base/loader/object_file.hh"
 #include "base/logging.hh"
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 67691c9..1f49262 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Consolidate register related files into a directory.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41737 )



Change subject: arch-arm: Consolidate register related files into a  
directory.

..

arch-arm: Consolidate register related files into a directory.

Create a directory called "regs" which holds files, primarily headers,
related to registers, with the exception of registers.hh. Hopefully
registers.hh will go away in the not too distant future, removing this
exception.

Change-Id: I631423c2b09bbcd14b20001380270718aeca619e
---
M src/arch/arm/SConscript
M src/arch/arm/aapcs32.hh
M src/arch/arm/aapcs64.hh
M src/arch/arm/decoder.hh
M src/arch/arm/fastmodel/iris/interrupts.cc
M src/arch/arm/fastmodel/iris/isa.cc
M src/arch/arm/faults.hh
M src/arch/arm/freebsd/se_workload.hh
M src/arch/arm/htm.cc
M src/arch/arm/htm.hh
M src/arch/arm/insts/fplib.hh
M src/arch/arm/insts/vfp.hh
M src/arch/arm/interrupts.hh
M src/arch/arm/isa.hh
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa_device.cc
M src/arch/arm/isa_device.hh
M src/arch/arm/kvm/armv8_cpu.hh
M src/arch/arm/locked_mem.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/pmu.hh
M src/arch/arm/process.cc
M src/arch/arm/process.hh
M src/arch/arm/registers.hh
R src/arch/arm/regs/cc.hh
R src/arch/arm/regs/int.hh
R src/arch/arm/regs/misc.cc
R src/arch/arm/regs/misc.hh
R src/arch/arm/regs/misc_types.hh
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/semihosting.hh
M src/arch/arm/table_walker.hh
M src/arch/arm/tracers/tarmac_base.cc
M src/arch/arm/tracers/tarmac_record.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
37 files changed, 58 insertions(+), 56 deletions(-)



diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 1d6799e..a51d794 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -81,7 +81,7 @@
 Source('freebsd/fs_workload.cc')
 Source('freebsd/se_workload.cc')
 Source('fs_workload.cc')
-Source('miscregs.cc')
+Source('regs/misc.cc')
 Source('mmu.cc')
 Source('nativetrace.cc')
 Source('pauth_helpers.cc')
diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index a1345bd..151ff95 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -33,7 +33,7 @@
 #include 
 #include 

-#include "arch/arm/intregs.hh"
+#include "arch/arm/regs/int.hh"
 #include "arch/arm/utility.hh"
 #include "base/intmath.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index fb7b8f8..4d4ae92 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -33,7 +33,7 @@
 #include 
 #include 

-#include "arch/arm/intregs.hh"
+#include "arch/arm/regs/int.hh"
 #include "arch/arm/utility.hh"
 #include "base/intmath.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 1f14328..1e7f80e 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -43,7 +43,7 @@

 #include 

-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/types.hh"
 #include "arch/generic/decode_cache.hh"
 #include "arch/generic/decoder.hh"
diff --git a/src/arch/arm/fastmodel/iris/interrupts.cc  
b/src/arch/arm/fastmodel/iris/interrupts.cc

index a3c777d..914f81e 100644
--- a/src/arch/arm/fastmodel/iris/interrupts.cc
+++ b/src/arch/arm/fastmodel/iris/interrupts.cc
@@ -29,8 +29,8 @@

 #include "arch/arm/fastmodel/iris/thread_context.hh"
 #include "arch/arm/interrupts.hh"
-#include "arch/arm/miscregs.hh"
-#include "arch/arm/miscregs_types.hh"
+#include "arch/arm/regs/misc.hh"
+#include "arch/arm/regs/misc_types.hh"
 #include "arch/arm/types.hh"
 #include "params/IrisInterrupts.hh"

diff --git a/src/arch/arm/fastmodel/iris/isa.cc  
b/src/arch/arm/fastmodel/iris/isa.cc

index 1470434..4aac71f 100644
--- a/src/arch/arm/fastmodel/iris/isa.cc
+++ b/src/arch/arm/fastmodel/iris/isa.cc
@@ -27,7 +27,7 @@

 #include "arch/arm/fastmodel/iris/isa.hh"

-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
 #include "cpu/thread_context.hh"
 #include "params/IrisISA.hh"
 #include "sim/serialize.hh"
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index b911136..463af12 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -42,8 +42,8 @@
 #ifndef __ARM_FAULTS_HH__
 #define __ARM_FAULTS_HH__

-#include "arch/arm/miscregs.hh"
 #include "arch/arm/pagetable.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/types.hh"
 #include "base/logging.hh"
 #include "sim/faults.hh"
diff --git a/src/arch/arm/freebsd

[gem5-dev] Change in gem5/gem5[develop]: arch-power: Pull non-public information out of registers.hh.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41740 )



Change subject: arch-power: Pull non-public information out of registers.hh.
..

arch-power: Pull non-public information out of registers.hh.

Also create a regs/ directory for register related headers.

Change-Id: Id376597b7b6254b26c05aa94e0141abacd807c79
---
M src/arch/power/isa.cc
M src/arch/power/isa.hh
M src/arch/power/isa/includes.isa
M src/arch/power/registers.hh
A src/arch/power/regs/float.hh
A src/arch/power/regs/int.hh
R src/arch/power/regs/misc.hh
M src/arch/power/remote_gdb.hh
M src/arch/power/se_workload.hh
M src/arch/power/utility.cc
10 files changed, 113 insertions(+), 34 deletions(-)



diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc
index 0aa480c..8908645 100644
--- a/src/arch/power/isa.cc
+++ b/src/arch/power/isa.cc
@@ -37,8 +37,9 @@

 #include "arch/power/isa.hh"

-#include "arch/power/miscregs.hh"
-#include "arch/power/registers.hh"
+#include "arch/power/regs/float.hh"
+#include "arch/power/regs/int.hh"
+#include "arch/power/regs/misc.hh"
 #include "params/PowerISA.hh"

 namespace PowerISA
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 7ec9ac7..cc5aceb 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -31,8 +31,7 @@
 #define __ARCH_POWER_ISA_HH__

 #include "arch/generic/isa.hh"
-#include "arch/power/miscregs.hh"
-#include "arch/power/registers.hh"
+#include "arch/power/regs/misc.hh"
 #include "arch/power/types.hh"
 #include "base/logging.hh"
 #include "cpu/reg_class.hh"
diff --git a/src/arch/power/isa/includes.isa  
b/src/arch/power/isa/includes.isa

index c219d97..4aa9ff5 100644
--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -70,7 +70,7 @@
 #include "arch/generic/memhelpers.hh"
 #include "arch/power/faults.hh"
 #include "arch/power/isa_traits.hh"
-#include "arch/power/miscregs.hh"
+#include "arch/power/regs/misc.hh"
 #include "arch/power/utility.hh"
 #include "base/condcodes.hh"
 #include "cpu/base.hh"
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index b31f5f3..5bdc058 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -33,6 +33,7 @@

 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
+#include "arch/power/regs/int.hh"

 namespace PowerISA
 {
@@ -52,35 +53,9 @@
 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
 constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;

-// Constants Related to the number of registers
-const int NumIntArchRegs = 32;
-
-// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
-// and zero register, which doesn't actually exist but needs a number
-const int NumIntSpecialRegs = 9;
-const int NumFloatArchRegs = 32;
-
-const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
-const int NumFloatRegs = NumFloatArchRegs;
-
-// Semantically meaningful register indices
-const int ReturnValueReg = 3;
-const int StackPointerReg = 1;
-
 // There isn't one in Power, but we need to define one somewhere
 const int ZeroReg = NumIntRegs - 1;

-enum MiscIntRegNums {
-INTREG_CR = NumIntArchRegs,
-INTREG_XER,
-INTREG_LR,
-INTREG_CTR,
-INTREG_FPSCR,
-INTREG_RSV,
-INTREG_RSV_LEN,
-INTREG_RSV_ADDR
-};
-
 } // namespace PowerISA

 #endif // __ARCH_POWER_REGISTERS_HH__
diff --git a/src/arch/power/regs/float.hh b/src/arch/power/regs/float.hh
new file mode 100644
index 000..c6e872d
--- /dev/null
+++ b/src/arch/power/regs/float.hh
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRI

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Move the inUserMode function to the ISA object.

2021-02-21 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39323 )


Change subject: arch,cpu: Move the inUserMode function to the ISA object.
..

arch,cpu: Move the inUserMode function to the ISA object.

This function is used when tracing execution with --debug-flags=Exec.
The data used by the function (now method) is stored in the ISA object,
and so that's a logical place to move it.

Change-Id: I624f9365124679343e988cabfb4e1929225b439a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39323
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/iris/isa.hh
M src/arch/arm/isa.hh
M src/arch/arm/utility.hh
M src/arch/generic/isa.hh
M src/arch/mips/isa.hh
M src/arch/mips/utility.hh
M src/arch/power/isa.hh
M src/arch/power/utility.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/utility.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/utility.hh
M src/arch/x86/isa.hh
M src/arch/x86/utility.hh
M src/cpu/exetrace.cc
15 files changed, 66 insertions(+), 65 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/fastmodel/iris/isa.hh  
b/src/arch/arm/fastmodel/iris/isa.hh

index d9646df..a7ae7b5 100644
--- a/src/arch/arm/fastmodel/iris/isa.hh
+++ b/src/arch/arm/fastmodel/iris/isa.hh
@@ -28,6 +28,7 @@
 #ifndef __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
 #define __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__

+#include "arch/arm/utility.hh"
 #include "arch/generic/isa.hh"

 namespace Iris
@@ -39,6 +40,13 @@
 ISA(const Params ) : BaseISA(p) {}

 void serialize(CheckpointOut ) const;
+
+bool
+inUserMode() const override
+{
+CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
+return ::inUserMode(cpsr);
+}
 };

 } // namespace Iris
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index dd4dc6e..7888229 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -48,6 +48,7 @@
 #include "arch/arm/system.hh"
 #include "arch/arm/tlb.hh"
 #include "arch/arm/types.hh"
+#include "arch/arm/utility.hh"
 #include "arch/generic/isa.hh"
 #include "arch/generic/traits.hh"
 #include "debug/Checkpoint.hh"
@@ -891,6 +892,13 @@
 {
 return readMiscRegNoEffect(MISCREG_CONTEXTIDR);
 }
+
+bool
+inUserMode() const override
+{
+CPSR cpsr = miscRegs[MISCREG_CPSR];
+return ArmISA::inUserMode(cpsr);
+}
 };
 }

diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index e255b1c..bd043df 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -111,23 +111,11 @@
 }

 static inline bool
-inUserMode(ThreadContext *tc)
-{
-return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
-}
-
-static inline bool
 inPrivilegedMode(CPSR cpsr)
 {
 return !inUserMode(cpsr);
 }

-static inline bool
-inPrivilegedMode(ThreadContext *tc)
-{
-return !inUserMode(tc);
-}
-
 bool isSecure(ThreadContext *tc);

 bool inAArch64(ThreadContext *tc);
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 7d5daa8..4c717c7 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -56,6 +56,7 @@
 virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }

 virtual uint64_t getExecutingAsid() const { return 0; }
+virtual bool inUserMode() const = 0;
 };

 #endif // __ARCH_GENERIC_ISA_HH__
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 1e94a98..cc05781 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -140,6 +140,26 @@
 // dummy
 int flattenCCIndex(int reg) const { return reg; }
 int flattenMiscIndex(int reg) const { return reg; }
+
+bool
+inUserMode() const override
+{
+RegVal Stat = readMiscRegNoEffect(MISCREG_STATUS);
+RegVal Dbg = readMiscRegNoEffect(MISCREG_DEBUG);
+
+if (// EXL, ERL or CU0 set, CP0 accessible
+(Stat & 0x1006) == 0 &&
+// DM bit set, CP0 accessible
+(Dbg & 0x4000) == 0 &&
+// KSU = 0, kernel mode is base mode
+(Stat & 0x0018) != 0) {
+// Unable to use Status_CU0, etc directly,
+// using bitfields & masks.
+return true;
+} else {
+return false;
+}
+}
 };
 }

diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 0cb9349..6fb211d 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -65,22 +65,6 @@
 bool isQnan(void *val_ptr, int size);
 bool isSnan(void *val_ptr, int size);

-static inline bool
-inUserMode(ThreadContext *tc)
-{
-RegVal Stat = tc->readMiscRe

[gem5-dev] Change in gem5/gem5[develop]: arch: Eliminate the getArgument function.

2021-02-19 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39321 )


Change subject: arch: Eliminate the getArgument function.
..

arch: Eliminate the getArgument function.

This ISA switched function is no longer used. Eliminate it, and reduce
the number of functions used in the switched utility.hh header by one.

Change-Id: Ic6020c5fa6d976d9dbf1e9f517809acf9b0b7cd8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39321
Reviewed-by: Giacomo Travaglini 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/mips/utility.cc
M src/arch/mips/utility.hh
M src/arch/power/utility.cc
M src/arch/power/utility.hh
M src/arch/riscv/utility.hh
M src/arch/sparc/utility.cc
M src/arch/sparc/utility.hh
M src/arch/x86/utility.cc
M src/arch/x86/utility.hh
11 files changed, 2 insertions(+), 141 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 93e0a78..31408f6 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -53,64 +53,6 @@
 namespace ArmISA
 {

-uint64_t
-getArgument(ThreadContext *tc, int , uint16_t size, bool fp)
-{
-panic_if(!FullSystem,
-"getArgument() only implemented for full system mode.");
-
-panic_if(fp, "getArgument(): Floating point arguments not  
implemented");

-
-if (inAArch64(tc)) {
-if (size == (uint16_t)(-1))
-size = sizeof(uint64_t);
-
-if (number < 8 /*NumArgumentRegs64*/) {
-   return tc->readIntReg(number);
-} else {
-panic("getArgument(): No support reading stack args for  
AArch64\n");

-}
-} else {
-if (size == (uint16_t)(-1))
-size = sizeof(uint32_t);
-
-if (number < NumArgumentRegs) {
-// If the argument is 64 bits, it must be in an even regiser
-// number. Increment the number here if it isn't even.
-if (size == sizeof(uint64_t)) {
-if ((number % 2) != 0)
-number++;
-// Read the two halves of the data. Number is inc here to
-// get the second half of the 64 bit reg.
-uint64_t tmp;
-tmp = tc->readIntReg(number++);
-tmp |= tc->readIntReg(number) << 32;
-return tmp;
-} else {
-   return tc->readIntReg(number);
-}
-} else {
-Addr sp = tc->readIntReg(StackPointerReg);
-PortProxy  = tc->getVirtProxy();
-uint64_t arg;
-if (size == sizeof(uint64_t)) {
-// If the argument is even it must be aligned
-if ((number % 2) != 0)
-number++;
-arg = vp.read(sp +
-(number-NumArgumentRegs) * sizeof(uint32_t));
-// since two 32 bit args == 1 64 bit arg, increment number
-number++;
-} else {
-arg = vp.read(sp +
-   (number-NumArgumentRegs) *  
sizeof(uint32_t));

-}
-return arg;
-}
-}
-panic("getArgument() should always return\n");
-}
-
 static void
 copyVecRegs(ThreadContext *src, ThreadContext *dest)
 {
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 453e461..e255b1c 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -400,8 +400,6 @@

 bool SPAlignmentCheckEnabled(ThreadContext* tc);

-uint64_t getArgument(ThreadContext *tc, int , uint16_t size, bool  
fp);

-
 inline void
 advancePC(PCState , const StaticInstPtr )
 {
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index db4e110..78fa3e2 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -43,12 +43,6 @@
 namespace MipsISA {

 uint64_t
-getArgument(ThreadContext *tc, int , uint16_t size, bool fp)
-{
-panic("getArgument() not implemented\n");
-}
-
-uint64_t
 fpConvert(ConvertType cvt_type, double fp_val)
 {

diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 23d92c1..0cb9349 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -49,8 +49,6 @@
 return ret;
 }

-uint64_t getArgument(ThreadContext *tc, int , uint16_t size, bool  
fp);

-
 
 //
 // Floating Point Utility Functions
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index da4748d..bed0be9 100644
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -55,11 +55,4 @@
 dest->pcState(src->pcState());
 }

-uint64_t
-getArgument(ThreadContext *tc,

[gem5-dev] Change in gem5/gem5[develop]: arm,kern: Stop using the getArgument function for kernel events.

2021-02-19 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39320 )


Change subject: arm,kern: Stop using the getArgument function for kernel  
events.

..

arm,kern: Stop using the getArgument function for kernel events.

This change plumbs through an ABI to use with the GuestABI mechanism so
that the ISA switched getArgument function is no longer used.

Change-Id: I0d394dcfd7ad6fa745b6ef2aa62973167108f0c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39320
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/freebsd/fs_workload.cc
M src/arch/arm/fs_workload.hh
M src/arch/arm/linux/fs_workload.cc
M src/kern/freebsd/events.cc
M src/kern/freebsd/events.hh
M src/kern/linux/events.cc
M src/kern/linux/events.hh
7 files changed, 64 insertions(+), 37 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  Bobby R. Bruce: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/arch/arm/freebsd/fs_workload.cc  
b/src/arch/arm/freebsd/fs_workload.cc

index cc0151b..7cd7a03 100644
--- a/src/arch/arm/freebsd/fs_workload.cc
+++ b/src/arch/arm/freebsd/fs_workload.cc
@@ -68,8 +68,7 @@
 "oops_exit", "Kernel oops in guest");
 }

-skipUDelay = addKernelFuncEvent>(
-"DELAY", "DELAY", 1000, 0);
+skipUDelay = addSkipFunc("DELAY", "DELAY", 1000, 0);
 }

 void
diff --git a/src/arch/arm/fs_workload.hh b/src/arch/arm/fs_workload.hh
index 4461670..d7f1738 100644
--- a/src/arch/arm/fs_workload.hh
+++ b/src/arch/arm/fs_workload.hh
@@ -44,6 +44,8 @@
 #include 
 #include 

+#include "arch/arm/aapcs32.hh"
+#include "arch/arm/aapcs64.hh"
 #include "kern/linux/events.hh"
 #include "params/ArmFsWorkload.hh"
 #include "sim/kernel_workload.hh"
@@ -86,6 +88,34 @@
  */
 Loader::ObjectFile *getBootLoader(Loader::ObjectFile *const obj);

+template  class FuncEvent,
+ typename... Args>
+PCEvent *
+addSkipFunc(Args... args)
+{
+if (getArch() == Loader::Arm64) {
+return addKernelFuncEvent>(
+std::forward(args)...);
+} else {
+return addKernelFuncEvent>(
+std::forward(args)...);
+}
+}
+
+template  class FuncEvent,
+ typename... Args>
+PCEvent *
+addSkipFuncOrPanic(Args... args)
+{
+if (getArch() == Loader::Arm64) {
+return addKernelFuncEventOrPanic>(
+std::forward(args)...);
+} else {
+return addKernelFuncEventOrPanic>(
+std::forward(args)...);
+}
+}
+
   public:
 typedef ArmFsWorkloadParams Params;
 const Params &
diff --git a/src/arch/arm/linux/fs_workload.cc  
b/src/arch/arm/linux/fs_workload.cc

index b296b68..3c29298 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -230,28 +230,23 @@

 // With ARM udelay() is #defined to __udelay
 // newer kernels use __loop_udelay and __loop_const_udelay symbols
-skipUDelay = addKernelFuncEvent>(
+skipUDelay = addSkipFunc(
 "__loop_udelay", "__udelay", 1000, 0);
-if (!skipUDelay)
-skipUDelay = addKernelFuncEventOrPanic>(
- "__udelay", "__udelay", 1000, 0);
+if (!skipUDelay) {
+skipUDelay = addSkipFuncOrPanic(
+"__udelay", "__udelay", 1000, 0);
+}

 // constant arguments to udelay() have some precomputation done ahead  
of

 // time. Constant comes from code.
-skipConstUDelay = addKernelFuncEvent>(
+skipConstUDelay = addSkipFunc(
 "__loop_const_udelay", "__const_udelay", 1000, 107374);
 if (!skipConstUDelay) {
-skipConstUDelay = addKernelFuncEventOrPanic>(
+skipConstUDelay = addSkipFuncOrPanic(
 "__const_udelay", "__const_udelay", 1000, 107374);
 }

-if (getArch() == Loader::Arm64) {
-debugPrintk = addKernelFuncEvent<
-DebugPrintk>("dprintk");
-} else {
-debugPrintk = addKernelFuncEvent<
-DebugPrintk>("dprintk");
-}
+debugPrintk = addSkipFunc("dprintk");
 }

 void
diff --git a/src/kern/freebsd/events.cc b/src/kern/freebsd/events.cc
index 0c4c613..e6b66fa 100644
--- a/src/kern/freebsd/events.cc
+++ b/src/kern/freebsd/events.cc
@@ -45,13 +45,8 @@
 {

 void
-onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul)
+onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t time)
 {
-int arg_num = 0;
-
-// Get the

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Move getExecutingAsid to the ISA class.

2021-02-19 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39322 )


Change subject: arch,cpu: Move getExecutingAsid to the ISA class.
..

arch,cpu: Move getExecutingAsid to the ISA class.

This function was switched based on the ISA, and returned 0 on
everything except SPARC and ARM. It was used only when tracing
instruction execution with --debug-flags=Exec.

Change-Id: I70c274cb76fb229d0e2bc606ba41f458ed18ab81
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39322
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Gabe Black 
---
M src/arch/arm/isa.hh
M src/arch/arm/utility.hh
M src/arch/generic/isa.hh
M src/arch/mips/utility.hh
M src/arch/power/utility.hh
M src/arch/riscv/utility.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/utility.hh
M src/arch/x86/utility.hh
M src/cpu/exetrace.cc
10 files changed, 17 insertions(+), 39 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 133c824..a97b1a5 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -887,6 +887,12 @@
 const Params () const;

 ISA(const Params );
+
+uint64_t
+getExecutingAsid() const override
+{
+return readMiscRegNoEffect(MISCREG_CONTEXTIDR);
+}
 };
 }

diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 6ec6403..453e461 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -411,12 +411,6 @@
 Addr truncPage(Addr addr);
 Addr roundPage(Addr addr);

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-return tc->readMiscReg(MISCREG_CONTEXTIDR);
-}
-
 // Decodes the register index to access based on the fields used in a MSR
 // or MRS instruction
 bool
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index c1b8734..7d5daa8 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -54,6 +54,8 @@
   public:
 virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext  
*old_tc) {}

 virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
+
+virtual uint64_t getExecutingAsid() const { return 0; }
 };

 #endif // __ARCH_GENERIC_ISA_HH__
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index c156c82..23d92c1 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -108,12 +108,6 @@
 pc.advance();
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-return 0;
-}
-
 };


diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index ba28f07..3a4b16c 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -66,12 +66,6 @@
 return 0;
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-return 0;
-}
-
 } // namespace PowerISA


diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index d4cf221..816d36c 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -176,12 +176,6 @@
 return true;
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-return 0;
-}
-
 } // namespace RiscvISA

 #endif // __ARCH_RISCV_UTILITY_HH__
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 2881384..21143dd 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -215,6 +215,11 @@
 int flattenCCIndex(int reg) const { return reg; }
 int flattenMiscIndex(int reg) const { return reg; }

+uint64_t
+getExecutingAsid() const override
+{
+return readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
+}

 typedef SparcISAParams Params;
 const Params () const;
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 4738eb4..3f36f03 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -70,12 +70,6 @@
 inst->advancePC(pc);
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-return tc->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
-}
-
 } // namespace SparcISA

 #endif
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 39a142c..50f65ef 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -77,13 +77,6 @@
 inst->advancePC(pc);
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-return 0;
-}
-
-
 /**
  * Reconstruct the rflags register from the internal gem5 register
  * state.
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 7bf60e7..e144743 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -66,8 +66,10 @@
 if (!in_user_mode && !Debug::ExecKernel) return;
 }

-if (Debug::ExecAsid)
-outs << "A" << std::dec << TheISA::getExecutingAsid(thread) << " ";
+if (Debug::ExecAsid) {
+outs << "A" << std::dec 

[gem5-dev] Change in gem5/gem5[develop]: scons: Enable the clang++ and clang tools.

2021-02-19 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41673 )



Change subject: scons: Enable the clang++ and clang tools.
..

scons: Enable the clang++ and clang tools.

If these tools aren't enabled and CXX isn't set, scons will look for
generically named compiler aliases like cc and c++. These will generally
work, but if scons knows that the compiler is specifically clang, it
will set the CXXCONFIG variable we can use to do compiler version
checking.

Change-Id: Ie6bebb8eab531989575c878bee07189541756d2c
---
M SConstruct
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/SConstruct b/SConstruct
index cc3af90..150e068 100755
--- a/SConstruct
+++ b/SConstruct
@@ -135,7 +135,7 @@
 #
 

-main = Environment(tools=['default', 'git', TempFileSpawn])
+main = Environment(tools=['default', 'git',  
TempFileSpawn, 'clang', 'clang++'])


 from gem5_scons.util import get_termcap
 termcap = get_termcap()

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie6bebb8eab531989575c878bee07189541756d2c
Gerrit-Change-Number: 41673
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Re: weird issue using gcr.io/gem5-test/clang-version-9 docker image?

2021-02-19 Thread Gabe Black via gem5-dev
Sorry I hadn't gotten back to you about this. Your explanation made sense
(stale docker), but I wanted to try it out before replying to make sure
that was it. I have now, and that command (less the http:// prefix which it
didn't like) said it downloaded an update. After that, "which
python3-config" had output. Thanks!

Gabe

On Sun, Feb 14, 2021 at 12:53 AM Bobby Bruce  wrote:

> I can't recreate the "clang-version-9 docker image without python3-config"
> bug on my end . I also had a little check of Kokoro and found the image
> there to be fine:
> https://gem5-review.googlesource.com/c/public/gem5/+/41373.
> python3-config appears to exist on the image inside Kokoro.
>
> I _think_ what you have is an out-of-date image on whatever system you're
> running on. I don't know under what circumstances docker will pull the
> latest version of an image, but you can do so manually with `docker pull
> http://gcr.io/gem5-test/clang-version-9`
> <http://gcr.io/gem5-test/clang-version-9>. Can you do that and try again?
> I think this will solve your problem.
>
> --
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Fri, Feb 12, 2021 at 5:35 PM Gabe Black  wrote:
>
>> Hi Bobby, that's not the docker I'm using. The one I'm using is
>> gcr.io/gem5-test/clang-version-9 which is the one run as part of the
>> presubmit tests (see original email). There may have been drift between
>> that and the compiler tests? When I run that docker interactively
>> (otherwise the same command as in the presubmit script) I get the following:
>>
>> $ docker run -i -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) --rm "
>> gcr.io/gem5-test/clang-version-9"
>> which python3-config
>> python3-config
>> /bin/bash: line 2: python3-config: command not found
>>
>> There's no command prompt so what is the output of what may not be clear.
>> I typed the "which" line which produced no output (nothing found). Then I
>> typed python3-config which returned the error message on the last line.
>>
>> The "leak" I'm referring to would be if the original build of gem5 (for
>> the regressions) figured out, for instance, where to get the python library
>> from, etc. scons will cache these values between builds to speed up build
>> time, and may not attempt to redetermine those values which it would no
>> longer be able to do once python3-config goes away in the second run. I
>> think it does try to figure out when those values are stale and rerun
>> config checks, but in my experience it's not 100% accurate and may not
>> retry when it really should. That could be hiding the error in this case.
>>
>> Gabe
>>
>> On Fri, Feb 12, 2021 at 10:37 AM Bobby Bruce  wrote:
>>
>>> Hey Gabe,
>>>
>>> So, the docker image appears to have python3-config:
>>>
>>> ```
>>> docker run --rm gcr.io/gem5-test/clang-version-9 python3-config
>>> ```
>>>
>>> Returns:
>>>
>>> ```
>>> Usage: /usr/bin/python3-config
>>> --prefix|--exec-prefix|--includes|--libs|--cflags|--ldflags|--extension-suffix|--help|--abiflags|--configdir
>>> ```
>>>
>>> So it's in there.
>>>
>>> As far as I can tell it's been this way for a while. The Dockerfile used
>>> to build the image is
>>> `util/dockerfiles/ubuntu-18.04_clang-version/Dockerfile`. I'm confused by
>>> this, I don't think anything should "leak" into the image in this way.
>>> Could you link me to an example of this issue happening?
>>>
>>> --
>>> Dr. Bobby R. Bruce
>>> Room 2235,
>>> Kemper Hall, UC Davis
>>> Davis,
>>> CA, 95616
>>>
>>> web: https://www.bobbybruce.net
>>>
>>>
>>> On Wed, Feb 10, 2021 at 10:21 PM Gabe Black 
>>> wrote:
>>>
>>>> Hi folks. I was trying to debug a problem in one of my scons cleanups
>>>> which was failing on kokoro when trying to build under clang. I think I
>>>> fixed it, but after doing so it started to fail because it didn't like the
>>>> version of python it was finding, and sure enough that image has
>>>> python-config and python2.7-config installed on it, but no python3-config
>>>> even though it has python 3.
>>>>
>>>> Does anybody know what's going on here? My best guess is that values
>>>> from a previous build using a docker image that does have python3-config
>>>> are leaking through and making the subsequent build with this image work,
>>>> even though it doesn't work when done first.
>>>>
>>>> Where should I/we look to fix this image so it has python3-config on it?
>>>>
>>>> Gabe
>>>>
>>>
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[gem5-dev] Change in gem5/gem5[develop]: misc: Fix mismatched struct/class "tags" and reenable that warning.

2021-02-19 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40953 )


Change subject: misc: Fix mismatched struct/class "tags" and reenable that  
warning.

..

misc: Fix mismatched struct/class "tags" and reenable that warning.

The mismatches were from places where Params structs had been declared
as classes instead of structs, and ruby's MachineID struct.

A comment describing why the warning had been disabled said that it was
because of libstdc++ version 4.8. As far as I can tell, that version is
old enough to be outside the window we support, and so that should no
longer be a problem. It looks like the oldest version of gcc we
support, 5.0, corresponds with approximately libstdc++ version 6.0.21.

https://gcc.gnu.org/onlinedocs/libstdc++/manual/abi.html#abi.versioning

Change-Id: I75ad92f3723a1883bd47e3919c5572a353344047
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40953
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M SConstruct
M src/arch/arm/pmu.hh
M src/dev/arm/css/mhu.hh
M src/dev/arm/display.hh
M src/dev/arm/fvp_base_pwr_ctrl.hh
M src/dev/arm/generic_timer.hh
M src/dev/arm/gpu_nomali.hh
M src/dev/arm/watchdog_generic.hh
M src/dev/arm/watchdog_sp805.hh
M src/gpu-compute/scheduler.hh
M src/mem/qos/mem_sink.hh
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/VIPERCoalescer.hh
M src/sim/mem_state.hh
M src/sim/probe/probe.hh
M src/sim/ticked_object.hh
16 files changed, 24 insertions(+), 30 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index e1814c3..cc3af90 100755
--- a/SConstruct
+++ b/SConstruct
@@ -387,13 +387,7 @@
 # parantheses are allowed due to Ruby's printing of the AST,
 # finally self assignments are allowed as the generated CPU code
 # is relying on this
-main.Append(CCFLAGS=['-Wno-parentheses',
- '-Wno-self-assign',
- # Some versions of libstdc++ (4.8?) seem to
- # use struct hash and class hash
- # interchangeably.
- '-Wno-mismatched-tags',
- ])
+main.Append(CCFLAGS=['-Wno-parentheses', '-Wno-self-assign'])
 conf.CheckCxxFlag('-Wno-c99-designator')
 conf.CheckCxxFlag('-Wno-defaulted-function-deleted')

diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh
index 3cdcf1c..e8c63bf 100644
--- a/src/arch/arm/pmu.hh
+++ b/src/arch/arm/pmu.hh
@@ -52,7 +52,7 @@
 #include "sim/sim_object.hh"
 #include "sim/system.hh"

-class ArmPMUParams;
+struct ArmPMUParams;
 class Platform;
 class ThreadContext;
 class ArmInterruptPin;
diff --git a/src/dev/arm/css/mhu.hh b/src/dev/arm/css/mhu.hh
index 17704e8..4e13605 100644
--- a/src/dev/arm/css/mhu.hh
+++ b/src/dev/arm/css/mhu.hh
@@ -41,12 +41,12 @@
 #include "dev/arm/doorbell.hh"
 #include "dev/io_device.hh"

-class Ap2ScpDoorbellParams;
+struct Ap2ScpDoorbellParams;
 class ArmInterruptPin;
 class MHU;
-class MHUParams;
+struct MHUParams;
 class Scp;
-class Scp2ApDoorbellParams;
+struct Scp2ApDoorbellParams;

 class MhuDoorbell : public Doorbell
 {
diff --git a/src/dev/arm/display.hh b/src/dev/arm/display.hh
index 1359487..91819ff 100644
--- a/src/dev/arm/display.hh
+++ b/src/dev/arm/display.hh
@@ -40,7 +40,7 @@

 #include "sim/sim_object.hh"

-class DisplayParams;
+struct DisplayParams;

 class Display : public SimObject
 {
diff --git a/src/dev/arm/fvp_base_pwr_ctrl.hh  
b/src/dev/arm/fvp_base_pwr_ctrl.hh

index 4b1bc4c..948ad30 100644
--- a/src/dev/arm/fvp_base_pwr_ctrl.hh
+++ b/src/dev/arm/fvp_base_pwr_ctrl.hh
@@ -44,7 +44,7 @@
 #include "dev/io_device.hh"

 class ArmSystem;
-class FVPBasePwrCtrlParams;
+struct FVPBasePwrCtrlParams;
 class ThreadContext;

 /**
diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh
index 9a6663c..66048cc 100644
--- a/src/dev/arm/generic_timer.hh
+++ b/src/dev/arm/generic_timer.hh
@@ -64,10 +64,10 @@
 /// I2 - System Level Implementation of the Generic Timer

 class Checkpoint;
-class SystemCounterParams;
-class GenericTimerParams;
-class GenericTimerFrameParams;
-class GenericTimerMemParams;
+struct SystemCounterParams;
+struct GenericTimerParams;
+struct GenericTimerFrameParams;
+struct GenericTimerMemParams;

 /// Abstract class for elements whose events depend on the counting speed
 /// of the System Counter
diff --git a/src/dev/arm/gpu_nomali.hh b/src/dev/arm/gpu_nomali.hh
index a096edb..e30f3ed 100644
--- a/src/dev/arm/gpu_nomali.hh
+++ b/src/dev/arm/gpu_nomali.hh
@@ -43,8 +43,8 @@
 #include "dev/io_device.hh"
 #include "libnomali/nomali.h"

-class NoMaliGpuParams;
-class CustomNoMaliGpuParams;
+struct NoMaliGpuParams;
+struct CustomNoMaliGpuParams;
 class

[gem5-dev] Change in gem5/gem5[develop]: cpu,mem: Add or remove parenthesis to make the compiler happy.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40956 )


Change subject: cpu,mem: Add or remove parenthesis to make the compiler  
happy.

..

cpu,mem: Add or remove parenthesis to make the compiler happy.

Remove extraneous parenthesis in an if condition, and add some
parenthesis where an assignment was being used as a condition in a while
loop.

Change-Id: Ie12c74ac681ef042138e3b41f257ea1bb2ce4267
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40956
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/pred/tage_base.cc
2 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 8472597..0f8716b 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -773,12 +773,12 @@
 IssueStruct *i2e_info = issueToExecuteQueue->access(0);

 DynInstPtr mem_inst;
-while (mem_inst = std::move(getDeferredMemInstToExecute())) {
+while ((mem_inst = std::move(getDeferredMemInstToExecute( {
 addReadyMemInst(mem_inst);
 }

 // See if any cache blocked instructions are able to be executed
-while (mem_inst = std::move(getBlockedMemInstToExecute())) {
+while ((mem_inst = std::move(getBlockedMemInstToExecute( {
 addReadyMemInst(mem_inst);
 }

diff --git a/src/cpu/pred/tage_base.cc b/src/cpu/pred/tage_base.cc
index 108f6a2..791f5d4 100644
--- a/src/cpu/pred/tage_base.cc
+++ b/src/cpu/pred/tage_base.cc
@@ -467,7 +467,7 @@
 //Allocate entries
 unsigned numAllocated = 0;
 for (int i = X; i <= nHistoryTables; i++) {
-if ((gtable[i][bi->tableIndices[i]].u == 0)) {
+if (gtable[i][bi->tableIndices[i]].u == 0) {
 gtable[i][bi->tableIndices[i]].tag = bi->tableTags[i];
 gtable[i][bi->tableIndices[i]].ctr = (taken) ? 0 : -1;
 ++numAllocated;



7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie12c74ac681ef042138e3b41f257ea1bb2ce4267
Gerrit-Change-Number: 40956
Gerrit-PatchSet: 10
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Introduce a version of reverseBits for 8 bit types.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41593 )


Change subject: base: Introduce a version of reverseBits for 8 bit types.
..

base: Introduce a version of reverseBits for 8 bit types.

These types shouldn't be shifted by 8, since shifting a type by its
width is technically undefined behavior. We never actually use the
result from this shift, but it still upsets certain versions of clang.

Change-Id: I425431473fa44a6e0de2edf780c265ff4e3f440e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41593
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/base/bitfield.hh
1 file changed, 9 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 1ec684f..470941a 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -209,7 +209,7 @@
  * @ingroup api_bitfield
  */
 template 
-std::enable_if_t::value, T>
+std::enable_if_t::value && sizeof(T) != 1, T>
 reverseBits(T val, size_t size=sizeof(T))
 {
 assert(size <= sizeof(T));
@@ -223,6 +223,14 @@
 return output;
 }

+template 
+std::enable_if_t::value && sizeof(T) == 1, T>
+reverseBits(T val, size_t size=sizeof(T))
+{
+assert(size == 1);
+return reverseBitsLookUpTable[val];
+}
+
 /**
  * Returns the bit position of the MSB that is set in the input
  *

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I425431473fa44a6e0de2edf780c265ff4e3f440e
Gerrit-Change-Number: 41593
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Move imports below version checks in site_init.py.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40966 )


Change subject: scons: Move imports below version checks in site_init.py.
..

scons: Move imports below version checks in site_init.py.

Without knowing for sure we're using python 3, it's dangerous to start
pulling in code which may make that assumption.

Change-Id: Ic13af74a686ee0fb8f36bb672beadea4334b431c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40966
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
---
M site_scons/site_init.py
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/site_scons/site_init.py b/site_scons/site_init.py
index 2f7cbf1..3507373 100644
--- a/site_scons/site_init.py
+++ b/site_scons/site_init.py
@@ -39,7 +39,6 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from __future__ import print_function
-from gem5_python_paths import extra_python_paths

 # Check for recent-enough Python and SCons versions.
 try:
@@ -85,4 +84,6 @@
 """)
 raise

+from gem5_python_paths import extra_python_paths
+
 sys.path[1:1] = extra_python_paths



7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Change-Number: 40966
Gerrit-PatchSet: 9
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Use std::abs() in traffic_gen.cc.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41597 )


Change subject: cpu: Use std::abs() in traffic_gen.cc.
..

cpu: Use std::abs() in traffic_gen.cc.

When building with clang with the --without-tcmalloc flag set, the
-fno-builtin flag is not used, and clang can then detect that the
integer version of abs(), apparently the C version, is being used on a
floating point value in traffic_gen.cc.

This change takes clang's suggestion to use std::abs instead, and also
includes a header file which will provide it.

Change-Id: Ic28ed7454b2ac00c89328d9d0314aed74e946643
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41597
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/cpu/testers/traffic_gen/traffic_gen.cc
1 file changed, 3 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/testers/traffic_gen/traffic_gen.cc  
b/src/cpu/testers/traffic_gen/traffic_gen.cc

index 1ea4d5e..6e1a00a 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.cc
+++ b/src/cpu/testers/traffic_gen/traffic_gen.cc
@@ -39,6 +39,7 @@
 #include 
 #include 

+#include 
 #include 
 #include 

@@ -331,9 +332,10 @@
 }

 // avoid comparing floating point numbers
-if (abs(sum - 1.0) > 0.001)
+if (std::fabs(sum - 1.0) > 0.001) {
 fatal("%s has transition probability != 1 for state %d\n",
   name(), i);
+}
 }

 // close input file

--
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Gerrit-Change-Number: 41597
Gerrit-PatchSet: 4
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Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: scons,systemc: Drop the check for gcc version when building systemc.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41595 )


Change subject: scons,systemc: Drop the check for gcc version when building  
systemc.

..

scons,systemc: Drop the check for gcc version when building systemc.

The minimum version of gcc is 5, and the check would only fail if gcc
was older than that.

Change-Id: I20f4f42661baf415b7cbe80ec0ace4e427666348
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41595
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
---
M src/systemc/SConsopts
1 file changed, 1 insertion(+), 8 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/systemc/SConsopts b/src/systemc/SConsopts
index bd9f1da..26a15dd 100644
--- a/src/systemc/SConsopts
+++ b/src/systemc/SConsopts
@@ -25,17 +25,10 @@

 Import('*')

-from m5.util import compareVersions
-
 from gem5_scons import warning

 def use_systemc_check(env, warn=False):
-if ('GCC_VERSION' in env and
-compareVersions(env['GCC_VERSION'], '5.0') < 0):
-if warn:
-warning('Systemc may not work on gcc versions less than 5.0.')
-return False
-elif env['PLATFORM'] == 'darwin':
+if env['PLATFORM'] == 'darwin':
 if warn:
 warning('Warning: Systemc may not work on Mac OS.')
 return False



2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Change-Id: I20f4f42661baf415b7cbe80ec0ace4e427666348
Gerrit-Change-Number: 41595
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: sim: Simplify some code in the guest ABI mechanism.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41600 )



Change subject: sim: Simplify some code in the guest ABI mechanism.
..

sim: Simplify some code in the guest ABI mechanism.

Instead of using recursively applied templates to accumulate a series of
wrapper lambdas which dispatch to a call, use pure parameter pack
expansion. This has two benefits. One, it makes the code simpler(ish) and
easier to understand. The parameter pack machinery is still intrinsically
fairly tricky, but there's less of it and it's a fairly straightforward
application of that mechanism.

Also, a nice side benefit is that the template for simcall dispatch will
expand to a small fixed number of functions which do all their work
locally, instead of having a new function for each layer of the onion,
one per parameter, and no calls through lambdas. That should hopefully
make debugging easier, and produce less bookkeeping overhead as far as
really long names, lots of functions, etc.

This code, specifically the code in dispatch.hh, can be simplified even
further in the future once we start using c++17 which is if constexpr,
and std::apply which explodes a tuple and uses its components as
arguments to a function, something I'm doing manually here.

Change-Id: If7c9234cc1014101211474c2ec20362702cf78c2
---
M src/sim/guest_abi.hh
M src/sim/guest_abi/dispatch.hh
M src/sim/guest_abi/layout.hh
3 files changed, 51 insertions(+), 112 deletions(-)



diff --git a/src/sim/guest_abi.hh b/src/sim/guest_abi.hh
index ea3325f..75c4e00 100644
--- a/src/sim/guest_abi.hh
+++ b/src/sim/guest_abi.hh
@@ -51,7 +51,7 @@
 // types will be zero initialized.
 auto state = GuestABI::initializeState(tc);
 GuestABI::prepareForFunction(tc, state);
-return GuestABI::callFrom(tc, state,  
target);
+return GuestABI::callFrom(tc, state,  
target);

 }

 template 
@@ -86,7 +86,7 @@
 // types will be zero initialized.
 auto state = GuestABI::initializeState(tc);
 GuestABI::prepareForArguments(tc, state);
-GuestABI::callFrom(tc, state, target);
+GuestABI::callFrom(tc, state, target);
 }

 template 
@@ -113,7 +113,7 @@

 GuestABI::prepareForFunction(tc, state);
 ss << name;
-GuestABI::dumpArgsFrom(0, ss, tc, state);
+GuestABI::dumpArgsFrom(ss, tc, state);
 return ss.str();
 }

diff --git a/src/sim/guest_abi/dispatch.hh b/src/sim/guest_abi/dispatch.hh
index bc365b9..93480db 100644
--- a/src/sim/guest_abi/dispatch.hh
+++ b/src/sim/guest_abi/dispatch.hh
@@ -30,8 +30,11 @@

 #include 
 #include 
+#include 
 #include 
+#include 

+#include "base/compiler.hh"
 #include "sim/guest_abi/definition.hh"
 #include "sim/guest_abi/layout.hh"

@@ -50,114 +53,63 @@
  * still possible to support by redefining these functions..
  */

-// With no arguments to gather, call the target function and store the
-// result.
-template 
-static typename std::enable_if_t::value && store_ret,  
Ret>

-callFrom(ThreadContext *tc, typename ABI::State ,
-std::function target)
+template 
+static inline typename std::enable_if_t
+callFromHelper(Target , ThreadContext *tc, State , Args  
&,

+std::index_sequence)
 {
-Ret ret = target(tc);
+return target(tc, std::get(args)...);
+}
+
+template 
+static inline typename std::enable_if_t
+callFromHelper(Target , ThreadContext *tc, State , Args  
&,

+std::index_sequence)
+{
+Ret ret = target(tc, std::get(args)...);
 storeResult(tc, ret, state);
 return ret;
 }

-template 
-static typename std::enable_if_t::value && !store_ret,  
Ret>

+template 
+static inline Ret
 callFrom(ThreadContext *tc, typename ABI::State ,
-std::function target)
+std::function target)
 {
-return target(tc);
+// Extract all the arguments from the thread context. Braced  
initializers

+// are evaluated from left to right.
+auto args = std::tuple{getArgument(tc, state)...};
+
+// Call the wrapper which will call target.
+return callFromHelper(
+target, tc, state, std::move(args),
+std::make_index_sequence{});
 }

-// With no arguments to gather and nothing to return, call the target  
function.

-template 
-static void
-callFrom(ThreadContext *tc, typename ABI::State ,
-std::function target)
-{
-target(tc);
-}
-
-// Recursively gather arguments for target from tc until we get to the base
-// case above.
-template 
-static typename std::enable_if_t::value, Ret>
-callFrom(ThreadContext *tc, typename ABI::State ,
-std::function target)
-{
-// Extract the next argument from the thread context.
-NextArg next = getArgument(tc, state);
-
-// Build a partial function which adds the next argument to the call.
-std::function partial =
-[target,next](ThreadContext *_tc, Args... args) {
-   

[gem5-dev] Change in gem5/gem5[develop]: python,scons: Move readCommand and compareVersions into site_scons.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41599 )



Change subject: python,scons: Move readCommand and compareVersions into  
site_scons.

..

python,scons: Move readCommand and compareVersions into site_scons.

These functions are only used by scons, so it makes sense to move them
to site_scons/gem5_scons/util.py.

Change-Id: If2b3995f208cb71adf3c59aac4eabe378c47f94f
---
M SConstruct
M ext/libelf/SConscript
M site_scons/gem5_scons/util.py
M site_scons/site_tools/git.py
M src/SConscript
M src/proto/SConsopts
M src/python/m5/util/__init__.py
M src/systemc/dt/int/SConscript
8 files changed, 64 insertions(+), 68 deletions(-)



diff --git a/SConstruct b/SConstruct
index adb7f0c..4308b72 100755
--- a/SConstruct
+++ b/SConstruct
@@ -90,8 +90,6 @@
 import SCons.Node
 import SCons.Node.FS

-from m5.util import compareVersions, readCommand
-

 
 #
@@ -131,6 +129,7 @@
 from gem5_scons import TempFileSpawn, EnvDefaults, MakeAction,  
MakeActionTool

 import gem5_scons
 from gem5_scons.builders import ConfigFile, AddLocalRPATH, SwitchingHeaders
+from gem5_scons.util import compareVersions, readCommand

 Export('MakeAction')

diff --git a/ext/libelf/SConscript b/ext/libelf/SConscript
index e2cc847..f3dbe6a 100644
--- a/ext/libelf/SConscript
+++ b/ext/libelf/SConscript
@@ -32,8 +32,6 @@

 Import('main')

-from m5.util import compareVersions
-
 elf_files = []
 def ElfFile(filename):
 elf_files.append(File(filename))
diff --git a/site_scons/gem5_scons/util.py b/site_scons/gem5_scons/util.py
index 1a196c2..b62cc01 100644
--- a/site_scons/gem5_scons/util.py
+++ b/site_scons/gem5_scons/util.py
@@ -38,6 +38,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+import itertools
+import re
 import sys

 import SCons.Script
@@ -50,3 +52,60 @@

 def get_termcap():
 return  
m5.util.terminal.get_termcap(SCons.Script.GetOption('use_colors'))

+
+def readCommand(cmd, **kwargs):
+"""
+run the command cmd, read the results and return them
+this is sorta like `cmd` in shell
+
+:param cmd: command to run with Popen
+:type cmd: string, list
+:returns: command stdout
+:rtype: string
+"""
+from subprocess import Popen, PIPE, STDOUT
+
+if isinstance(cmd, str):
+cmd = cmd.split()
+
+no_exception = 'exception' in kwargs
+exception = kwargs.pop('exception', None)
+
+kwargs.setdefault('shell', False)
+kwargs.setdefault('stdout', PIPE)
+kwargs.setdefault('stderr', STDOUT)
+kwargs.setdefault('close_fds', True)
+try:
+subp = Popen(cmd, **kwargs)
+except Exception as e:
+if no_exception:
+return -1, exception
+raise
+
+output = subp.communicate()[0].decode('utf-8')
+return output
+
+def compareVersions(v1, v2):
+"""helper function: compare arrays or strings of version numbers.
+E.g., compare_version((1,3,25), (1,4,1)')
+returns -1, 0, 1 if v1 is <, ==, > v2
+"""
+def make_version_list(v):
+if isinstance(v, (list,tuple)):
+return v
+elif isinstance(v, str):
+return list(map(lambda x: int(re.match('\d+', x).group()),
+v.split('.')))
+else:
+raise TypeError()
+
+v1 = make_version_list(v1)
+v2 = make_version_list(v2)
+
+# Compare corresponding elements of lists
+# The shorter list is filled with 0 till the lists have the same length
+for n1,n2 in itertools.zip_longest(v1, v2, fillvalue=0):
+if n1 < n2: return -1
+if n1 > n2: return  1
+
+return 0
diff --git a/site_scons/site_tools/git.py b/site_scons/site_tools/git.py
index a77cffb..3a71c9f 100644
--- a/site_scons/site_tools/git.py
+++ b/site_scons/site_tools/git.py
@@ -42,7 +42,6 @@
 import sys

 import gem5_scons.util
-from m5.util import readCommand

 git_style_message = """
 You're missing the gem5 style or commit message hook. These hooks help
@@ -52,7 +51,7 @@

 def install_style_hooks(env):
 try:
-gitdir = env.Dir(readCommand(
+gitdir = env.Dir(gem5_scons.util.readCommand(
 ["git", "rev-parse", "--git-dir"]).strip("\n"))
 except Exception as e:
 print("Warning: Failed to find git repo directory: %s" % e)
diff --git a/src/SConscript b/src/SConscript
index 5fe0ab2..dc07279 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -63,7 +63,7 @@

 build_env = [(opt, env[opt]) for opt in export_vars]

-from m5.util import code_formatter, compareVersions, readCommand
+from m5.util import code_formatter

 #

[gem5-dev] Change in gem5/gem5[develop]: python: Collapse away the now unused readCommandWithReturn function.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41598 )



Change subject: python: Collapse away the now unused readCommandWithReturn  
function.

..

python: Collapse away the now unused readCommandWithReturn function.

This had been used when detecting python versions, but can now be
absorbed into readCommand.

Change-Id: I4385357c3ce33a0f1b58e741067aa7ae3a7daa3b
---
M src/python/m5/util/__init__.py
1 file changed, 4 insertions(+), 16 deletions(-)



diff --git a/src/python/m5/util/__init__.py b/src/python/m5/util/__init__.py
index 74c0ec0..a0fe63d 100644
--- a/src/python/m5/util/__init__.py
+++ b/src/python/m5/util/__init__.py
@@ -173,15 +173,15 @@
 line += item
 print(line)

-def readCommandWithReturn(cmd, **kwargs):
+def readCommand(cmd, **kwargs):
 """
 run the command cmd, read the results and return them
 this is sorta like `cmd` in shell

 :param cmd: command to run with Popen
 :type cmd: string, list
-:returns: pair consisting on Popen retcode and the command stdout
-:rtype: (int, string)
+:returns: command stdout
+:rtype: string
 """
 from subprocess import Popen, PIPE, STDOUT

@@ -203,19 +203,7 @@
 raise

 output = subp.communicate()[0].decode('utf-8')
-return subp.returncode, output
-
-def readCommand(cmd, **kwargs):
-"""
-run the command cmd, read the results and return them
-this is sorta like `cmd` in shell
-
-:param cmd: command to run with Popen
-:type cmd: string, list
-:returns: command stdout
-:rtype: string
-"""
-return readCommandWithReturn(cmd, **kwargs)[1]
+return output

 def makeDir(path):
 """Make a directory if it doesn't exist.  If the path does exist,

--
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Gerrit-Branch: develop
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Use std::abs() in traffic_gen.cc.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41597 )



Change subject: cpu: Use std::abs() in traffic_gen.cc.
..

cpu: Use std::abs() in traffic_gen.cc.

When building with clang with the --without-tcmalloc flag set, the
-fno-builtin flag is not used, and clang can then detect that the
integer version of abs(), apparently the C version, is being used on a
floating point value in traffic_gen.cc.

This change takes clang's suggestion to use std::abs instead, and also
includes a header file which will provide it.

Change-Id: Ic28ed7454b2ac00c89328d9d0314aed74e946643
---
M src/cpu/testers/traffic_gen/traffic_gen.cc
1 file changed, 3 insertions(+), 1 deletion(-)



diff --git a/src/cpu/testers/traffic_gen/traffic_gen.cc  
b/src/cpu/testers/traffic_gen/traffic_gen.cc

index 1ea4d5e..97b6e65 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.cc
+++ b/src/cpu/testers/traffic_gen/traffic_gen.cc
@@ -39,6 +39,7 @@
 #include 
 #include 

+#include 
 #include 
 #include 

@@ -331,9 +332,10 @@
 }

 // avoid comparing floating point numbers
-if (abs(sum - 1.0) > 0.001)
+if (std::abs(sum - 1.0) > 0.001) {
 fatal("%s has transition probability != 1 for state %d\n",
   name(), i);
+}
 }

 // close input file

--
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[gem5-dev] Change in gem5/gem5[develop]: scons,systemc: Drop the check for gcc version when building systemc.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41595 )



Change subject: scons,systemc: Drop the check for gcc version when building  
systemc.

..

scons,systemc: Drop the check for gcc version when building systemc.

The minimum version of gcc is 5, and the check would only fail if gcc
was older than that.

Change-Id: I20f4f42661baf415b7cbe80ec0ace4e427666348
---
M src/systemc/SConsopts
1 file changed, 1 insertion(+), 6 deletions(-)



diff --git a/src/systemc/SConsopts b/src/systemc/SConsopts
index 13636cd..4864944 100644
--- a/src/systemc/SConsopts
+++ b/src/systemc/SConsopts
@@ -30,12 +30,7 @@
 from gem5_scons import warning

 def use_systemc_check(env, warn=False):
-if ('GCC_VERSION' in env and
-compareVersions(env['GCC_VERSION'], '5.0') < 0):
-if warn:
-warning('Systemc may not work on gcc versions less than 5.0.')
-return False
-elif env['PLATFORM'] == 'darwin':
+if env['PLATFORM'] == 'darwin':
 if warn:
 warning('Warning: Systemc may not work on Mac OS.')
 return False

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I20f4f42661baf415b7cbe80ec0ace4e427666348
Gerrit-Change-Number: 41595
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: Use SCons' built in CXXVERSION instead of detecting our own.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41596 )



Change subject: scons: Use SCons' built in CXXVERSION instead of detecting  
our own.

..

scons: Use SCons' built in CXXVERSION instead of detecting our own.

It's not guaranteed that every compiler will set CXXVERSION, but both
gcc and clang do, and for any check of CXXVERSION to be meaningful, we
have to first check which compiler we're talking about.

Change-Id: Icd15e12832920fec6fa8634bc0fde16cc48e3f41
---
M SConstruct
M src/systemc/dt/int/SConscript
2 files changed, 5 insertions(+), 9 deletions(-)



diff --git a/SConstruct b/SConstruct
index 4752d9e..f2fbafb 100755
--- a/SConstruct
+++ b/SConstruct
@@ -345,12 +345,9 @@
   "src/SConscript to support that compiler.")))

 if main['GCC']:
-gcc_version = readCommand([main['CXX'], '-dumpversion'],  
exception=False)

-if compareVersions(gcc_version, "5") < 0:
+if compareVersions(main['CXXVERSION'], "5") < 0:
 error('gcc version 5 or newer required.\n'
-  'Installed version:', gcc_version)
-
-main['GCC_VERSION'] = gcc_version
+  'Installed version:', main['CXXVERSION'])

 # If not disabled, set the Link-Time Optimization (LTO) flags.
 if not GetOption('no_lto'):
@@ -362,10 +359,9 @@
   '-fno-builtin-realloc', '-fno-builtin-free'])

 elif main['CLANG']:
-clang_version = readCommand([main['CXX'], '-dumpversion'],  
exception=False)

-if compareVersions(clang_version, "3.9") < 0:
+if compareVersions(main['CXXVERSION'], "3.9") < 0:
 error('clang version 3.9 or newer required.\n'
-  'Installed version:', clang_version)
+  'Installed version:', main['CXXVERSION'])

 # If not disabled, set the Link-Time Optimization (LTO) flags.
 if not GetOption('no_lto'):
diff --git a/src/systemc/dt/int/SConscript b/src/systemc/dt/int/SConscript
index 92c0f07..b052f04 100644
--- a/src/systemc/dt/int/SConscript
+++ b/src/systemc/dt/int/SConscript
@@ -28,7 +28,7 @@
 from m5.util import compareVersions

 if env['USE_SYSTEMC']:
-if main['GCC'] and compareVersions(main['GCC_VERSION'], '10.0') >= 0:
+if main['GCC'] and compareVersions(main['CXXVERSION'], '10.0') >= 0:
 disable_false_positives = {
 "CCFLAGS": [ "-Wno-array-bounds",
  "-Wno-stringop-overflow" ]

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icd15e12832920fec6fa8634bc0fde16cc48e3f41
Gerrit-Change-Number: 41596
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: Introduce a version of reverseBits for 8 bit types.

2021-02-17 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41593 )



Change subject: scons: Introduce a version of reverseBits for 8 bit types.
..

scons: Introduce a version of reverseBits for 8 bit types.

These types shouldn't be shifted by 8, since shifting a type by its
width is technically undefined behavior. We never actually use the
result from this shift, but it still upsets certain versions of clang.

Change-Id: I425431473fa44a6e0de2edf780c265ff4e3f440e
---
M src/base/bitfield.hh
1 file changed, 9 insertions(+), 1 deletion(-)



diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 1ec684f..470941a 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -209,7 +209,7 @@
  * @ingroup api_bitfield
  */
 template 
-std::enable_if_t::value, T>
+std::enable_if_t::value && sizeof(T) != 1, T>
 reverseBits(T val, size_t size=sizeof(T))
 {
 assert(size <= sizeof(T));
@@ -223,6 +223,14 @@
 return output;
 }

+template 
+std::enable_if_t::value && sizeof(T) == 1, T>
+reverseBits(T val, size_t size=sizeof(T))
+{
+assert(size == 1);
+return reverseBitsLookUpTable[val];
+}
+
 /**
  * Returns the bit position of the MSB that is set in the input
  *

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I425431473fa44a6e0de2edf780c265ff4e3f440e
Gerrit-Change-Number: 41593
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] minor bug in bitfield.hh

2021-02-17 Thread Gabe Black via gem5-dev
Hey folks. I just found out that certain versions of clang get upset with
the new version of reverseBits I just checked in when reversing the bits in
an 8 bit data type. It doesn't like shifting an 8 bit value by 8, since
that's technically undefined behavior, even though we'll never use the
resulting value. I have a fix which I'll upload shortly, but if anybody
runs into that, a fix is on the way.

Gabe
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