Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/67211?usp=email )

 (

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: arch-riscv: Correct interrupt order
......................................................................

arch-riscv: Correct interrupt order

In Section 3.1.14 of Volume II Riscv Spec., the interrupt order
should be MEI, MSI, MTI, SEI, SSI, STI and so on.

issues:
https://gem5.atlassian.net/browse/GEM5-889

Change-Id: I357c86eecd74e9e65bbfd3d4d31e68bc276f8760
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67211
Maintainer: Jason Lowe-Power <power...@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsi...@google.com>
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Jui-min Lee <f...@google.com>
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
---
M src/arch/riscv/interrupts.hh
1 file changed, 24 insertions(+), 3 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jui-min Lee: Looks good to me, but someone else must approve
  Yu-hsin Wang: Looks good to me, approved
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved




diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index f10c5f3..a1ee396 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -125,9 +125,9 @@
             return std::make_shared<NonMaskableInterruptFault>();
         std::bitset<NumInterruptTypes> mask = globalMask();
         const std::vector<int> interrupt_order {
-            INT_EXT_MACHINE, INT_TIMER_MACHINE, INT_SOFTWARE_MACHINE,
-            INT_EXT_SUPER, INT_TIMER_SUPER, INT_SOFTWARE_SUPER,
-            INT_EXT_USER, INT_TIMER_USER, INT_SOFTWARE_USER
+            INT_EXT_MACHINE, INT_SOFTWARE_MACHINE, INT_TIMER_MACHINE,
+            INT_EXT_SUPER, INT_SOFTWARE_SUPER, INT_TIMER_SUPER,
+            INT_EXT_USER, INT_SOFTWARE_USER, INT_TIMER_USER
         };
         for (const int &id : interrupt_order)
             if (checkInterrupt(id) && mask[id])

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I357c86eecd74e9e65bbfd3d4d31e68bc276f8760
Gerrit-Change-Number: 67211
Gerrit-PatchSet: 5
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
Gerrit-Reviewer: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Jui-min Lee <f...@google.com>
Gerrit-Reviewer: Peter Yuen <ppeetteer...@gmail.com>
Gerrit-Reviewer: Roger Chang <rogerycch...@google.com>
Gerrit-Reviewer: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Earl Ou <shunhsin...@google.com>
Gerrit-MessageType: merged
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