Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34055 )
Change subject: arch-arm: XPACD, XPACI, XPACLRI do not trap
......................................................................
arch-arm: XPACD, XPACI, XPACLRI do not trap
The HCR_EL2.API and SCR_EL3.API bits do not control the trapping of
those stripping instructions.
Change-Id: I84349937f8c50d63b5b52146743b035d1058fd8d
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa/insts/pauth.isa
M src/arch/arm/pauth_helpers.cc
M src/arch/arm/pauth_helpers.hh
3 files changed, 11 insertions(+), 53 deletions(-)
diff --git a/src/arch/arm/isa/insts/pauth.isa
b/src/arch/arm/isa/insts/pauth.isa
index 4806e6a..699d86b 100644
--- a/src/arch/arm/isa/insts/pauth.isa
+++ b/src/arch/arm/isa/insts/pauth.isa
@@ -89,7 +89,7 @@
code = pacEnabledCode(hint) + """
uint64_t res;
- fault = stripPAC(xc->tcBase(), XDest, data, &res);
+ stripPAC(xc->tcBase(), XDest, data, &res);
XDest = res;
"""
regoptype = 'RegOp'
diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index 7424eb3..d38e745 100644
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -1,5 +1,6 @@
// -*- mode:c++ -*-
+// Copyright (c) 2020 ARM Limited
// Copyright (c) 2020 Metempsy Technology Consulting
// All rights reserved
//
@@ -857,13 +858,9 @@
-Fault
-ArmISA::stripPAC(ThreadContext* tc, uint64_t A, bool data, uint64_t* out){
- bool trapEL2 = false;
- bool trapEL3 = false;
-
- uint64_t ptr;
-
+void
+ArmISA::stripPAC(ThreadContext* tc, uint64_t A, bool data, uint64_t* out)
+{
ExceptionLevel el = currEL(tc);
bool tbi = calculateTBI(tc, el, A, data);
@@ -871,51 +868,14 @@
int bottom_PAC_bit = calculateBottomPACBit(tc, el, selbit);
int top_bit = tbi ? 55 : 63;
- uint32_t nbits = (top_bit+1) - bottom_PAC_bit;
+ uint32_t nbits = (top_bit + 1) - bottom_PAC_bit;
uint64_t pacbits = ((uint64_t)0x1 << nbits) -1; // 2^n -1;
uint64_t mask = pacbits << bottom_PAC_bit; // creates mask
-
if (selbit) {
- ptr = A | mask;
+ *out = A | mask;
} else {
- ptr = A & ~mask;
+ *out = A & ~mask;
}
-
- SCR scr3 = tc->readMiscReg(MISCREG_SCR_EL3);
- HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
- bool have_el3 = ArmSystem::haveEL(tc, EL3);
-
- switch (el)
- {
- case EL0:
- trapEL2 = (EL2Enabled(tc) && hcr.api == 0 &&
- (hcr.tge == 0 || hcr.e2h == 0));
- trapEL3 = have_el3 && scr3.api == 0;
- break;
- case EL1:
- trapEL2 = EL2Enabled(tc) && hcr.api == 0;
- trapEL3 = have_el3 && scr3.api == 0;
- break;
- case EL2:
- trapEL2 = false;
- trapEL3 = have_el3 && scr3.api == 0;
- break;
- case EL3:
- trapEL2 = false;
- trapEL3 = false;
- break;
- default:
- // Unnaccessible
- break;
- }
- if (trapEL2)
- return trapPACUse(tc, EL2);
- else if (trapEL3)
- return trapPACUse(tc, EL3);
- else
- *out = ptr;
-
- return NoFault;
}
diff --git a/src/arch/arm/pauth_helpers.hh b/src/arch/arm/pauth_helpers.hh
index 24e745c..66b2c7e 100644
--- a/src/arch/arm/pauth_helpers.hh
+++ b/src/arch/arm/pauth_helpers.hh
@@ -1,5 +1,6 @@
// -*- mode:c++ -*-
+// Copyright (c) 2020 ARM Limited
// Copyright (c) 2020 Metempsy Technology Consulting
// All rights reserved
//
@@ -110,15 +111,12 @@
Fault
addPACIB(ThreadContext* tc, uint64_t X, uint64_t Y, uint64_t* out);
- // Strip()
- // =======
- // Strip() returns a 64-bit value containing A, but replacing the
+ // stripPAC returns a 64-bit value containing A, but replacing the
// pointer authentication code field bits with the extension of the
// address bits. This can apply to either instructions or data, where,
// as the use of tagged pointers is distinct, it might be
// handled differently.
-
- Fault
+ void
stripPAC(ThreadContext* tc, uint64_t A, bool data, uint64_t* out);
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I84349937f8c50d63b5b52146743b035d1058fd8d
Gerrit-Change-Number: 34055
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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