Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35836 )
Change subject: mem: Add support to tag tlb entries with PCID
......................................................................
mem: Add support to tag tlb entries with PCID
This change adds support to tag tlb entries with PCID to
avoid the conflict between different processes with same
virtual addresses sharing a tlb. This eventually is required
to enable smt support for x86.
Change-Id: Ia91dc371482793962e3fc83afe7a3fd2cdb60eab
---
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
3 files changed, 49 insertions(+), 8 deletions(-)
diff --git a/src/arch/x86/pagetable_walker.cc
b/src/arch/x86/pagetable_walker.cc
index fd9d043..07d20b4 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -510,8 +510,22 @@
}
if (doEndWalk) {
if (doTLBInsert)
- if (!functional)
- walker->tlb->insert(entry.vaddr, entry);
+ if (!functional) {
+
+ // Check if PCIDE is set in CR4
+ CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
+ if (cr4.pcide){
+ CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
+ walker->tlb->insert(entry.vaddr, entry, cr3.pcid);
+ }
+ else{
+ // The current PCID is always 000H if PCIDE
+ // is not set [sec 4.10.1 of Intel's Software
+ // Developer Manual]
+ walker->tlb->insert(entry.vaddr, entry, 0x000);
+ }
+ }
+
endWalk();
} else {
PacketPtr oldRead = read;
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 11ce660..0eebdcf 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -94,8 +94,14 @@
}
TlbEntry *
-TLB::insert(Addr vpn, const TlbEntry &entry)
+TLB::insert(Addr vpn, const TlbEntry &entry, uint64_t pcid)
{
+ //Adding pcid to the page address so
+ //that multiple processes using the same
+ //tlb do not conflict when using the same
+ //virtual addresses
+ vpn = concAddrPcid(vpn, pcid);
+
// If somebody beat us to it, just use that existing entry.
TlbEntry *newEntry = trie.lookup(vpn);
if (newEntry) {
@@ -113,7 +119,7 @@
newEntry->lruSeq = nextSeq();
newEntry->vaddr = vpn;
newEntry->trieHandle =
- trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
+ trie.insert(vpn, TlbEntryTrie::MaxBits, newEntry);
return newEntry;
}
@@ -371,7 +377,22 @@
if (m5Reg.paging) {
DPRINTF(TLB, "Paging enabled.\n");
// The vaddr already has the segment base applied.
- TlbEntry *entry = lookup(vaddr);
+
+ //Appending the pcid (last 12 bits of CR3) to the
+ //page aligned vaddr if pcide is set
+ CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
+ Addr pageAlignedVaddr = vaddr & mask(X86ISA::PageShift);
+ CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
+ uint64_t pcid;
+
+ if (cr4.pcide)
+ pcid = cr3.pcid;
+ else
+ pcid = 0x000;
+
+ pageAlignedVaddr = concAddrPcid(pageAlignedVaddr, pcid);
+ TlbEntry *entry = lookup(pageAlignedVaddr);
+
if (mode == Read) {
stats.rdAccesses++;
} else {
@@ -393,7 +414,7 @@
delayedResponse = true;
return fault;
}
- entry = lookup(vaddr);
+ entry = lookup(pageAlignedVaddr);
assert(entry);
} else {
Process *p = tc->getProcessPtr();
@@ -409,7 +430,8 @@
entry = insert(alignedVaddr, TlbEntry(
p->pTable->pid(), alignedVaddr, pte->paddr,
pte->flags &
EmulationPageTable::Uncacheable,
- pte->flags &
EmulationPageTable::ReadOnly));
+ pte->flags & EmulationPageTable::ReadOnly),
+ pcid);
}
DPRINTF(TLB, "Miss was serviced.\n");
}
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 671b165..c5fe3a6 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -73,6 +73,11 @@
TlbEntry *lookup(Addr va, bool update_lru = true);
void setConfigAddress(uint32_t addr);
+ //concatenate Page Addr and pcid
+ inline Addr concAddrPcid(Addr vpn, uint64_t pcid)
+ {
+ return (vpn | pcid);
+ }
protected:
@@ -150,7 +155,7 @@
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc,
Mode mode) const override;
- TlbEntry *insert(Addr vpn, const TlbEntry &entry);
+ TlbEntry *insert(Addr vpn, const TlbEntry &entry, uint64_t pcid);
// Checkpointing
void serialize(CheckpointOut &cp) const override;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35836
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia91dc371482793962e3fc83afe7a3fd2cdb60eab
Gerrit-Change-Number: 35836
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram <yazak...@ucdavis.edu>
Gerrit-MessageType: newchange
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