Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39915 )
Change subject: system: Fix PCI Mem range for VExpress_GEM5_VX DTS
......................................................................
system: Fix PCI Mem range for VExpress_GEM5_VX DTS
This is addressing an issue raised in the mailing list [1]
where setting up a PCI mem bar for an ethernet device
resulted into an overlap of memory ranges:
fatal: system.iobus has two ports responding within range
[0x80000000:0x80020000]:
system.realview.ethernet.pio
system.iobridge.cpu_side_port
The reason for this is the following:
The PCI mem range in the DTB is using 0x40000000 (3rd word) as a
starting address in the PCI domain, which is linked to 0x40000000 in the
host domain.
<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
However the current mapping scheme works with simple fixed translation
So address 0x40000000 in the PCI domain will be mapped to 0x40000000 +
0x40000000 = 0x80000000, which is where DRAM starts
This is aligning with DTB autogeneration, which is setting up a
PCI mem range starting at PCI address = 0 [2]
[1]: https://www.mail-archive.com/gem5-users@gem5.org/msg18941.html
[2]:
https://github.com/gem5/gem5/blob/v20.1.0.0/src/dev/arm/RealView.py#L161
Change-Id: I4538511453cfd5143fb4613a080780dc86b2244c
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
M system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
b/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
index a84e8e3..2a56150 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
@@ -66,8 +66,8 @@
reg = <0x0 0x30000000 0x0 0x10000000>;
- ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0
0x00010000>,
- <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0
0x40000000>;
+ ranges = <0x01000000 0x0 0x0 0x0 0x2f000000 0x0 0x00010000>,
+ <0x02000000 0x0 0x0 0x0 0x40000000 0x0 0x40000000>;
interrupt-map = <0x000000 0x0 0x0 0 &gic 0 68 1>,
<0x000800 0x0 0x0 0 &gic 0 69 1>,
diff --git a/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
b/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
index 2ea94ac..6dbaa2c 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
@@ -76,8 +76,8 @@
reg = <0x0 0x30000000 0x0 0x10000000>;
- ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0
0x00010000>,
- <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0
0x40000000>;
+ ranges = <0x01000000 0x0 0x0 0x0 0x2f000000 0x0 0x00010000>,
+ <0x02000000 0x0 0x0 0x0 0x40000000 0x0 0x40000000>;
/*
child unit address, #cells = #address-cells
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4538511453cfd5143fb4613a080780dc86b2244c
Gerrit-Change-Number: 39915
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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