Hi all (and specifically our AMD colleagues), Does anyone know how real hardware assigns APIC IDs in x86? We need to do something more than just use the CPU number if we want to support multiple hardware threads.
We have a proposal here: https://gem5-review.googlesource.com/c/public/gem5/+/35837. However, Gabe correctly points out that "we should do what real hardware does", but the problem is we don't know what it does. Feedback from others would be appreciated! Note that this is a long standing jira issue ( https://gem5.atlassian.net/browse/GEM5-332) and many of our users have been asking for us to enable multi-thread support for x86 (there was another question on this today!). It would be really nice to get this done for the next gem5 release. If no one knows what real hardware does, is there anyone against just using the hw thread number in the lower bits? Thanks, Jason
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