changeset 0b969a35781f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0b969a35781f
description:
mem: Add parameter to reserve MSHR entries for demand access
Adds a new parameter that reserves some number of MSHR entries for
demand
accesses. This helps prevent prefetchers from taking all MSHRs,
forcing demand
requests from the CPU to stall.
diffstat:
src/mem/cache/BaseCache.py | 1 +
src/mem/cache/base.cc | 4 ++--
src/mem/cache/cache_impl.hh | 2 +-
src/mem/cache/mshr_queue.cc | 8 +++++---
src/mem/cache/mshr_queue.hh | 19 ++++++++++++++++++-
5 files changed, 27 insertions(+), 7 deletions(-)
diffs (101 lines):
diff -r b7bc5b1084a4 -r 0b969a35781f src/mem/cache/BaseCache.py
--- a/src/mem/cache/BaseCache.py Tue Dec 23 09:31:18 2014 -0500
+++ b/src/mem/cache/BaseCache.py Tue Dec 23 09:31:18 2014 -0500
@@ -54,6 +54,7 @@
max_miss_count = Param.Counter(0,
"number of misses to handle before calling exit")
mshrs = Param.Int("number of MSHRs (max outstanding requests)")
+ demand_mshr_reserve = Param.Int(1, "mshrs to reserve for demand access")
size = Param.MemorySize("capacity in bytes")
forward_snoops = Param.Bool(True,
"forward snoops from mem side to cpu side")
diff -r b7bc5b1084a4 -r 0b969a35781f src/mem/cache/base.cc
--- a/src/mem/cache/base.cc Tue Dec 23 09:31:18 2014 -0500
+++ b/src/mem/cache/base.cc Tue Dec 23 09:31:18 2014 -0500
@@ -68,8 +68,8 @@
BaseCache::BaseCache(const Params *p)
: MemObject(p),
cpuSidePort(nullptr), memSidePort(nullptr),
- mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs),
- writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,
+ mshrQueue("MSHRs", p->mshrs, 4, p->demand_mshr_reserve, MSHRQueue_MSHRs),
+ writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 0,
MSHRQueue_WriteBuffer),
blkSize(p->system->cacheLineSize()),
hitLatency(p->hit_latency),
diff -r b7bc5b1084a4 -r 0b969a35781f src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Tue Dec 23 09:31:18 2014 -0500
+++ b/src/mem/cache/cache_impl.hh Tue Dec 23 09:31:18 2014 -0500
@@ -1841,7 +1841,7 @@
// fall through... no pending requests. Try a prefetch.
assert(!miss_mshr && !write_mshr);
- if (prefetcher && !mshrQueue.isFull()) {
+ if (prefetcher && mshrQueue.canPrefetch()) {
// If we have a miss queue slot, we can try a prefetch
PacketPtr pkt = prefetcher->getPacket();
if (pkt) {
diff -r b7bc5b1084a4 -r 0b969a35781f src/mem/cache/mshr_queue.cc
--- a/src/mem/cache/mshr_queue.cc Tue Dec 23 09:31:18 2014 -0500
+++ b/src/mem/cache/mshr_queue.cc Tue Dec 23 09:31:18 2014 -0500
@@ -52,10 +52,12 @@
using namespace std;
MSHRQueue::MSHRQueue(const std::string &_label,
- int num_entries, int reserve, int _index)
+ int num_entries, int reserve, int demand_reserve,
+ int _index)
: label(_label), numEntries(num_entries + reserve - 1),
- numReserve(reserve), registers(numEntries),
- drainManager(NULL), allocated(0), inServiceEntries(0), index(_index)
+ numReserve(reserve), demandReserve(demand_reserve),
+ registers(numEntries), drainManager(NULL), allocated(0),
+ inServiceEntries(0), index(_index)
{
for (int i = 0; i < numEntries; ++i) {
registers[i].queue = this;
diff -r b7bc5b1084a4 -r 0b969a35781f src/mem/cache/mshr_queue.hh
--- a/src/mem/cache/mshr_queue.hh Tue Dec 23 09:31:18 2014 -0500
+++ b/src/mem/cache/mshr_queue.hh Tue Dec 23 09:31:18 2014 -0500
@@ -77,6 +77,12 @@
*/
const int numReserve;
+ /**
+ * The number of entries to reserve for future demand accesses.
+ * Prevent prefetcher from taking all mshr entries
+ */
+ const int demandReserve;
+
/** MSHR storage. */
std::vector<MSHR> registers;
/** Holds pointers to all allocated entries. */
@@ -106,9 +112,11 @@
* @param num_entrys The number of entries in this queue.
* @param reserve The minimum number of entries needed to satisfy
* any access.
+ * @param demand_reserve The minimum number of entries needed to satisfy
+ * demand accesses.
*/
MSHRQueue(const std::string &_label, int num_entries, int reserve,
- int index);
+ int demand_reserve, int index);
/**
* Find the first MSHR that matches the provided address.
@@ -218,6 +226,15 @@
}
/**
+ * Returns true if sufficient mshrs for prefetch.
+ * @return True if sufficient mshrs for prefetch.
+ */
+ bool canPrefetch() const
+ {
+ return (allocated < numEntries - (numReserve + demandReserve));
+ }
+
+ /**
* Returns the MSHR at the head of the readyList.
* @return The next request to service.
*/
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
