Yea, it seems like it could start translating, get to commit cause a
fault that refetchs or replays that instruction...
Ali
On Jan 16, 2009, at 11:08 PM, Korey Sewell wrote:
> Isn't "before it commits" the same as "before/while it's executing"?
>
> On Sat, Jan 17, 2009 at 1:35 AM, Gabe Black
Isn't "before it commits" the same as "before/while it's executing"?
On Sat, Jan 17, 2009 at 1:35 AM, Gabe Black wrote:
> I don't think that'll work because the fix up needs to happen
> before/while the instruction executes, not on the side before it commits.
>
> Korey Sewell wrote:
> > OK, I'm
Kevin Lim wrote:
> Hey Gabe,
>
> My suggestion would be to allow translation to be put off until it has
> completed or generated a different fault. It would be a bit of a pain
> to include, but given that the infrastructure is already there in
> terms of delaying when cache misses occur, it should
I don't think that'll work because the fix up needs to happen
before/while the instruction executes, not on the side before it commits.
Korey Sewell wrote:
> OK, I'm not sure why you cant just let the instruction go on as
> regular, have some object does does your special x86 stuff, then when
> th
Hey Gabe,
My suggestion would be to allow translation to be put off until it has
completed or generated a different fault. It would be a bit of a pain
to include, but given that the infrastructure is already there in terms
of delaying when cache misses occur, it should be feasible.
Regarding
OK, I'm not sure why you cant just let the instruction go on as regular,
have some object does does your special x86 stuff, then when that finishes
signals something to the CPU to acknowledge the fix up.
Basically, I'm not sure you cant just manipulate the signals that are sent
between stages and
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Sure. Also the current process is not inaccurate, or at least mostly accurate if
you want to be picky, for all the ISAs except x86.
Currently, translation works like this as I'm sure you know:
1. Instruction generates request.
2. CPU asks TLB to translate request possibly generating a fault.
3. If
Gabe,
Can you step-by-step explain what's inaccurate about the current TLB
process?
On Wed, Jan 14, 2009 at 6:31 PM, wrote:
> Has anyone had a chance to give this some thought? Could Kevin/Korey
> comment on
> how hard they think it would be and/or how much overhead there would be to
> make
> tr
* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing passed.
* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-ti
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