These patches first cleanup/restructure the ARM ISA description to make
working on it easier, and to extend it slightly. Later patches eliminate ISA
defined register files in favor of ISA defined register policies/semantics and
CPU implemented register files. The MiscRegFile was subsumed by a new
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247027877 25200
# Node ID 25e9fe47c844a1e59f9705fcd0844da1312ae0d0
# Parent b42cea5e16251b2f556271f17edb2f24a8998260
ARM: Add operands for the load/store double instructions.
diff --git a/src/arch/arm/isa/operands.isa
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247028089 25200
# Node ID 6e5c26fe17ea449302c4e6357ee5ade8a0b2fc37
# Parent 25e9fe47c844a1e59f9705fcd0844da1312ae0d0
ARM: Add load/store double instructions.
diff --git a/src/arch/arm/isa/decoder.isa
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247028751 25200
# Node ID e4e0a9c21038f603f01f8ae76c530bd85e9ea88c
# Parent f51525f758ad52dad2be9872bd7ae9c3ed04ab60
ARM: Don't always update CPSR.
diff --git a/src/arch/arm/isa/formats/mem.isa
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247029036 25200
# Node ID 16c1879694a187e9124819e196c8ce0181ee83f2
# Parent e4e0a9c21038f603f01f8ae76c530bd85e9ea88c
ARM: Add an AddrMode2 format for memory instructions that use address mode 2.
diff --git
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247029159 25200
# Node ID ba161dcdbde4ce9fc6f5e7424095a1121897e18b
# Parent 16c1879694a187e9124819e196c8ce0181ee83f2
ARM: Get rid of end_addr in the ArmMacroStore constructor.
diff --git a/src/arch/arm/isa/formats/macromem.isa
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030011 25200
# Node ID f7fff997a90c73c0039a4df21765af1e7472d009
# Parent 390b00170a5874e09107d0b16f33ce59e1e7111d
ARM: Tune up predicated instruction decoding.
diff --git a/src/arch/arm/insts/pred_inst.cc
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030039 25200
# Node ID e654a7b1863b13b020abe6716eb71a4348177271
# Parent f7fff997a90c73c0039a4df21765af1e7472d009
ARM: Improve memory instruction disassembly.
diff --git a/src/arch/arm/insts/mem.cc
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030415 25200
# Node ID 35afb9c03f93765def29418dda102a4fe0783796
# Parent d243b53a4a035947d7519c72b1f6cb6dc9c11c71
ARM: Move the memory microops out of the decoder and into the ISA desc.
diff --git
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030259 25200
# Node ID d243b53a4a035947d7519c72b1f6cb6dc9c11c71
# Parent e654a7b1863b13b020abe6716eb71a4348177271
ARM: Move the integer microops out of the decoder and into the ISA desc.
diff --git
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030577 25200
# Node ID fb76c90f067563a312f12d012f77787d2093a79b
# Parent 35afb9c03f93765def29418dda102a4fe0783796
ARM: Move the remaining microops out of the decoder and into the ISA desc.
diff --git
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030684 25200
# Node ID b754546a7d335695138e0cb5fb422e6273861fb9
# Parent fb76c90f067563a312f12d012f77787d2093a79b
ISA parser: Allow alternative read/write code for operands.
diff --git a/src/arch/isa_parser.py
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030974 25200
# Node ID 558ae700b4c884985894057001b428581cad8a87
# Parent b754546a7d335695138e0cb5fb422e6273861fb9
ARM: Use custom read/write code to alias R15 with the PC.
diff --git a/src/arch/arm/isa/operands.isa
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247031835 25200
# Node ID 95d483300be325e2f201ce2cd111a6f6a53c0b3c
# Parent 2a32835617508ef7ffb24324446a6091f0874b5f
Registers: Eliminate the ISA defined floating point register file.
diff --git a/src/arch/alpha/SConscript
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247031915 25200
# Node ID 1e69e4af6b8326bc39832eb283932765ca6028e8
# Parent 95d483300be325e2f201ce2cd111a6f6a53c0b3c
Registers: Eliminate the ISA defined integer register file.
diff --git a/src/arch/alpha/intregfile.cc
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032287 25200
# Node ID 6f4db071b6a035d228e232e30bdec6fe53c294ef
# Parent 1e69e4af6b8326bc39832eb283932765ca6028e8
ARM: Flush out the ARM's int_regfile.hh.
diff --git a/src/arch/arm/regfile/int_regfile.hh
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032307 25200
# Node ID 3258ed877cdf1c2d5652459a4e47bb07fe940096
# Parent 6f4db071b6a035d228e232e30bdec6fe53c294ef
MIPS: Phase out MIPS's int_regfile.hh.
diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc
---
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032325 25200
# Node ID aae0868864317ce2a75fcc983824d70bca57c389
# Parent 3258ed877cdf1c2d5652459a4e47bb07fe940096
X86: Phase out x86's intregfile.hh.
diff --git a/src/arch/x86/intregfile.hh b/src/arch/x86/intregfile.hh
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032343 25200
# Node ID 6ef0fe52b0f8c1c6515f87557733c37123cca123
# Parent aae0868864317ce2a75fcc983824d70bca57c389
SPARC: Phase out SPARC's intregfile.hh.
diff --git a/src/arch/sparc/interrupts.hh
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032355 25200
# Node ID d8a15ef0b98a97ffc001da822a1e181c15f4e51d
# Parent 6ef0fe52b0f8c1c6515f87557733c37123cca123
Alpha: Phase out Alpha's intregfile.hh and intregfile.cc.
diff --git a/src/arch/alpha/SConscript
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032533 25200
# Node ID 84d1f065dc0ada2b1999d1db2dd21ce063853bc2
# Parent d8a15ef0b98a97ffc001da822a1e181c15f4e51d
MIPS: Get rid of an orphaned MIPS .cc file.
diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032618 25200
# Node ID 69fc4de727cc87f848066ec5adc4575dfd138c49
# Parent 84d1f065dc0ada2b1999d1db2dd21ce063853bc2
ARM, Simple CPU: Fix an index and add assert checks.
diff --git a/src/arch/arm/isa_traits.hh
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032718 25200
# Node ID 0c71cf640a766877f362fd8fd7606d0c778079ad
# Parent 2ae12bc9cb4e6c170e8c2cd363667063b406ac2a
Alpha: Get rid of function prototypes with no implementations.
diff --git a/src/arch/alpha/utility.hh
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032696 25200
# Node ID 2ae12bc9cb4e6c170e8c2cd363667063b406ac2a
# Parent 69fc4de727cc87f848066ec5adc4575dfd138c49
Registers: Move the PCs out of the ISAs and into the CPUs.
diff --git a/src/arch/alpha/regfile.cc
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032814 25200
# Node ID 1914f4971a5c8c5dc043b41ec0956392b31c0bd2
# Parent 0c71cf640a766877f362fd8fd7606d0c778079ad
Registers: Eliminate the ISA defined RegFile class.
diff --git a/src/arch/alpha/miscregfile.hh
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247033042 25200
# Node ID 963e51dbd618daf84e1e95a2861891b38311bb35
# Parent 1914f4971a5c8c5dc043b41ec0956392b31c0bd2
Alpha: Move reg_redir into its own files, and move some constants into
regfile.hh.
diff --git
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247033125 25200
# Node ID 9edc4e717d8933b93fa9a8c04c663e46df6f6594
# Parent 963e51dbd618daf84e1e95a2861891b38311bb35
Registers: Collapse ARM and MIPS regfile directories.
diff --git a/src/arch/arm/SConscript
Some of these may end up being filtered, or at least they did for me, so
look for gaps in the numbering and in your spam folder.
Gabe
gbl...@eecs.umich.edu wrote:
These patches first cleanup/restructure the ARM ISA description to make
working on it easier, and to extend it slightly. Later
* build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic passed.
* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing passed.
* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
passed.
*
changeset 57650468aff1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=57650468aff1
description:
slicc: fixed MI_example bug. The directory wasn't deallocating the
TBE, leading to a leak. Also increased the default max TBE size to 256 to allow
memtest to pass the
Derek,
I'd like to request that you insert newlines such that your comments
wrap at 80 columns.
Thanks,
Nate
On Wed, Jul 8, 2009 at 7:23 AM, Derek Howerd...@cs.wisc.edu wrote:
changeset 57650468aff1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=57650468aff1
* build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
FAILED!
I'm guessing that this changed because of the tweaks Derek has made to
the MI_example protocol.
Nate
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m5-dev@m5sim.org
Sure, I'll try to get emacs to do it.
On Wed, Jul 8, 2009 at 9:34 AM, nathan binkert n...@binkert.org wrote:
Derek,
I'd like to request that you insert newlines such that your comments
wrap at 80 columns.
Thanks,
Nate
On Wed, Jul 8, 2009 at 7:23 AM, Derek Howerd...@cs.wisc.edu wrote:
That's correct. The last changeset fixes it.
On Wed, Jul 8, 2009 at 9:35 AM, nathan binkert n...@binkert.org wrote:
* build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
FAILED!
I'm guessing that this changed because of the tweaks Derek has made to
the MI_example
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