* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed.
*
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Ship it!
- Nilay
On 2011-01-06 15:55:34, Brad Beckmann wrote:
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There's one minor glitch, but otherwise it looks fine.
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I think there are two problems with this patch. First, if at all possible
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There are a few problems with this. First, this is an indirect way to get
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I think you forgot some files so this I suppose this is only a partial
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I don't know all the ins and outs of checkpointing, but it looks ok to
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Ship it!
Looks ok to me.
- Gabe
On 2011-01-06 16:12:04, Brad Beckmann
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The code seems ok, but why do we need to have multiple outstanding page
On 2011-01-07 05:51:30, Gabe Black wrote:
The code seems ok, but why do we need to have multiple outstanding page
walks in timing mode again?
Actually, I wrote the above before I'd read it carefully. My question still
stands, but there are some areas that need to be fixed up. Also, since
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src/dev/x86/i82094aa.hh
http://reviews.m5sim.org/r/397/#comment884
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What are these new pseudo instructions and script options for? I don't
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Ship it!
- Nilay
On 2011-01-06 16:19:23, Brad Beckmann wrote:
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src/mem/ruby/libruby.cc
http://reviews.m5sim.org/r/391/#comment892
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If these are adapted from Rick's patches, what was the license on those
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src/mem/ruby/system/Sequencer.cc
Hi Nilay,
Unfortunately I can't provide you an example of a protocol where getCacheEntry
behaves in a different manner, but they do exist. I reviewed your most recent
patch updates and I don't think what we're asking for is much different than
what you have on reviewboard right now.
Brad, my comments are inline.
On Fri, 7 Jan 2011, Beckmann, Brad wrote:
Hi Nilay,
Unfortunately I can't provide you an example of a protocol where
getCacheEntry behaves in a different manner, but they do exist. I
reviewed your most recent patch updates and I don't think what we're
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src/dev/x86/intdev.hh
http://reviews.m5sim.org/r/384/#comment898
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
On 2011-01-07 12:01:01, Nathan Binkert wrote:
src/dev/x86/intdev.hh, line 62
http://reviews.m5sim.org/r/384/diff/1/?file=9053#file9053line62
Can you fix the style since you're editing? The colon should be on the
line below the one it's on.
That's not actually in the style guide
Oops, I mean to send this to m5-dev.
Gabe
Original Message
Subject:Re: Review Request: x86: set IsCondControl flag for the
appropriate microops
Date: Fri, 07 Jan 2011 12:04:38 -0800
From: Gabe Black gbl...@eecs.umich.edu
To: Brad Beckmann
On 2011-01-07 04:21:05, Gabe Black wrote:
I think there are two problems with this patch. First, if at all possible
we should avoid the code duplication we'd now have for the recvTiming
function. Second, while this probably does fix the legitimate problem of
deleting packets twice, I
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src/dev/x86/intdev.hh
http://reviews.m5sim.org/r/384/#comment900
On 2011-01-07 12:16:31, Nathan Binkert wrote:
src/dev/x86/intdev.hh, line 62
http://reviews.m5sim.org/r/384/diff/1/?file=9053#file9053line62
Just because something is not in the style guide doesn't mean it's not
part of the style. I'd guess that 95% of m5 follows the convention.
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
On 2011-01-07 04:45:16, Gabe Black wrote:
I think you forgot some files so this I suppose this is only a partial
review. It looks like this could be cleanly split into three different
changes, and the fact that you have sub-commit messages for those
independent parts suggests that
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Ship it!
Though I'm with Nate on code cleanliness to just use the hash
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Ship it!
- Lisa
On 2011-01-06 16:10:36, Brad Beckmann wrote:
On 2011-01-07 04:34:28, Gabe Black wrote:
See review of the earlier IntDev patch. Basically this is displacing the
latency value from the base class that uses it into the subclass that gets
it from the config. I don't think it's necessary as described previously,
but also that
Ok, yeah, looking at it again I think you probably have something. I
keep mixing up the port and the containing device in my head when I
think about this. A revised version of my suggestion would be to move
the latency into IntDev and use it there. Sorry if I propagated any of
my own
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I don't know about the interrupt device, the but TLB code is good -
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Suggest using %#x instead of %x, otherwise, good.
- Lisa
On 2011-01-06
On 2011-01-07 06:13:30, Gabe Black wrote:
What are these new pseudo instructions and script options for? I don't
remember these being mentioned before. You should NOT check in the
m5.disableAllListeners() line.
This patch tracks work items for those benchmarks that have had their work
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
On 2011-01-07 04:21:05, Gabe Black wrote:
I think there are two problems with this patch. First, if at all possible
we should avoid the code duplication we'd now have for the recvTiming
function. Second, while this probably does fix the legitimate problem of
deleting packets twice, I
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
Please update existing review requests instead of creating new ones.
Gabe
Quoting Brad Beckmann brad.beckm...@amd.com:
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On 2011-01-07 04:45:16, Gabe Black wrote:
src/arch/x86/vtophys.cc, line 58
http://reviews.m5sim.org/r/385/diff/1/?file=9054#file9054line58
Better wording might be Need access to page tables.
I like that change
On 2011-01-07 04:45:16, Gabe Black wrote:
src/arch/x86/vtophys.cc,
I'll have to look at this again and see if I can figure out what's
going on. For now I wanted to mention that Valgrind isn't necessarily
going to be useful in determining if there's a memory leak here
because these messages are sent infrequently and only leak a little
bit each time. In the
On 2011-01-07 05:51:30, Gabe Black wrote:
The code seems ok, but why do we need to have multiple outstanding page
walks in timing mode again?
Gabe Black wrote:
Actually, I wrote the above before I'd read it carefully. My question
still stands, but there are some areas that need
changeset b5003ac75977 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b5003ac75977
description:
scons: show sources and targets when building, and colorize output.
I like the brevity of Ali's recent change, but the ambiguity of
sometimes showing the
changeset 94fdc8111d7b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=94fdc8111d7b
description:
inorder: get rid of references to mainEventQueue.
Events need to be scheduled on the queue assigned
to the SimObject, not on the global queue (which
changeset afe8476ee9e9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=afe8476ee9e9
description:
pseudoinst: get rid of mainEventQueue references.
Avoid direct references to mainEventQueue in pseudo-insts
by indirecting through associated CPU object.
changeset 4ee66d8c1dd8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4ee66d8c1dd8
description:
sim: delete unused CheckSwapEvent code.
There's no way to even create one of these anymore.
diffstat:
src/sim/sim_events.cc | 33 -
changeset f1d298b7416c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f1d298b7416c
description:
sim: clean up CountedDrainEvent slightly.
There's no reason for it to derive from SimLoopExitEvent.
This whole drain thing needs to be redone eventually,
changeset fc475ac7d2a4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=fc475ac7d2a4
description:
stats: rename StatEvent() function to schedStatEvent().
This follows the style rules and is more descriptive.
diffstat:
src/python/m5/stats.py | 2 +-
changeset dac01f14f20f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=dac01f14f20f
description:
Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with
Hi,
I am trying to build m5 with a non-root account and the operation system
is redhat 2.6.28.
The system does not have recent python (the original one is 2.3.4 which
does not fulfill m5's requirement), and I installed python 2.6.4 in my own
directory.
However, when I compile m5, the system
Hi. You should ask this on m5-users. Most or maybe all of the people on
this list are on that list as well, along with a lot of other people.
Gabe
zhanglunkai wrote:
Hi,
I am trying to build m5 with a non-root account and the operation system
is redhat 2.6.28.
The system does not have
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