[m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-01-24 Thread Cron Daemon
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed. *

Re: [m5-dev] Profile Results for Mesh Network

2011-01-24 Thread Steve Reinhardt
On Sun, Jan 23, 2011 at 4:08 PM, Nilay Vaish ni...@cs.wisc.edu wrote: On Sun, 23 Jan 2011, Korey Sewell wrote: In sendFetch(), it calls sendTiming() which would then call the recvTiming on the cache port since those two should be binded as peers. I'm a little unsure of how the RubyPort,

Re: [m5-dev] Profile Results for Mesh Network

2011-01-24 Thread Nilay Vaish
On Mon, 24 Jan 2011, Steve Reinhardt wrote: On Sun, Jan 23, 2011 at 4:08 PM, Nilay Vaish ni...@cs.wisc.edu wrote: On Sun, 23 Jan 2011, Korey Sewell wrote: In sendFetch(), it calls sendTiming() which would then call the recvTiming on the cache port since those two should be binded as peers.

Re: [m5-dev] Profile Results for Mesh Network

2011-01-24 Thread Korey Sewell
Steve, we can try caching MRU cache block. We can also try replacing hash table with a two dimensional array indexed using cache set and cache way. This should at least show some decent speedup (depending on SMC code). The O3 caches the MRU and ironically, I had just patched the InOrder model

Re: [m5-dev] Review Request: Remove CacheMsg class from SLICC

2011-01-24 Thread Derek Hower
On 2011-01-20 15:49:13, Brad Beckmann wrote: I've only had a chance to briefly review this, but I do have a couple comments: - The hammer cache changes didn't seem to upload cleanly. Can you try to post them again? - I just want to confirm that the libruby interface is still useful to

Re: [m5-dev] Profile Results for Mesh Network

2011-01-24 Thread Gabriel Michael Black
Quoting Steve Reinhardt ste...@gmail.com: Gabe, how many bytes at a time does the x86 predecoder fetch? If it doesn't currently grab a cache line at a time, could it be made to do so, and do you know if that would cause any issues with SMC? All of the predecoders expect to receive one

[m5-dev] PerfectSwitch

2011-01-24 Thread Nilay Vaish
On Tue, 18 Jan 2011, Beckmann, Brad wrote: Hi Nilay, My plan is to tackle the functional access support as soon as I check in our current group of outstanding patches. I'm hoping to at least check in the majority of them in the next couple of days. Now that you've completed the

[m5-dev] Review Request: refcnt: Update doxygen comments

2011-01-24 Thread Nathan Binkert
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/437/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

Re: [m5-dev] Review Request: Remove CacheMsg class from SLICC

2011-01-24 Thread Nilay Vaish
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/327/ --- (Updated 2011-01-24 20:26:28.555420) Review request for Default. Summary

[m5-dev] Review Request: Ruby: Remove isTagPresent() calls from Sequencer.cc

2011-01-24 Thread Nilay Vaish
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/329/ --- Review request for Default. Summary --- Ruby: Remove isTagPresent() calls

Re: [m5-dev] Review Request: Remove CacheMsg class from SLICC

2011-01-24 Thread nathan binkert
To be honest, I think that libruby removal should really be a separate diff. Nate With this update, all the protocols have been changed. Also, libruby.hh and libruby.cc have been removed. Only problem is that there are still a couple of files DeterministicDriver.cc, RaceyPseudoThread.hh,