[m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-02-25 Thread Cron Daemon
* build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory passed. *

[m5-dev] Review Request: O3: Fix corner case squashing into the microcode ROM.

2011-02-25 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/501/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[m5-dev] Review Request: O3: Implement memory mapped IPRs for O3.

2011-02-25 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/502/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

Re: [m5-dev] Review Request: O3: Implement memory mapped IPRs for O3.

2011-02-25 Thread Gabe Black
I think there's a better than normal chance I introduced some bug with this code, so I'd appreciate it if people could check it out. Gabe On 02/25/11 05:46, Gabe Black wrote: This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/502/ Review request for

[m5-dev] changeset in m5: O3CPU: Fix iqCount and lsqCount SMT fetch polic...

2011-02-25 Thread Timothy M. Jones
changeset 4a59661d3fd1 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=4a59661d3fd1 description: O3CPU: Fix iqCount and lsqCount SMT fetch policies. Fixes two of the SMT fetch policies in O3CPU that were returning the count of instructions in the IQ or

[m5-dev] Review Request: Ruby: Change DataBlock.hh

2011-02-25 Thread Nilay Vaish
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/503/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[m5-dev] Review Request: Ruby: Change Address.hh

2011-02-25 Thread Nilay Vaish
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/504/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[m5-dev] Review Request: Ruby: Remove libruby_internal.hh

2011-02-25 Thread Nilay Vaish
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/506/ --- Review request for Default. Summary --- Ruby: Remove libruby_internal.hh This

Re: [m5-dev] Review Request: Ruby: Remove libruby

2011-02-25 Thread Nilay Vaish
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/439/ --- (Updated 2011-02-25 08:32:18.235107) Review request for Default. Summary

[m5-dev] Review Request: Ruby: Remove store buffer

2011-02-25 Thread Nilay Vaish
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/507/ --- Review request for Default. Summary --- Ruby: Remove store buffer This patch

Re: [m5-dev] Review Request: Ruby: Change DataBlock.hh

2011-02-25 Thread Nilay Vaish
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/503/ --- (Updated 2011-02-25 08:34:04.928259) Review request for Default. Summary ---

Re: [m5-dev] Store Buffer

2011-02-25 Thread Arkaprava Basu
In sum, I think we all agree that Ruby is going to handle *only non-speculative stores*. M5 CPU model(s) handles all of speculative and non-speculative stores that are *yet to be revealed to the memory sub-system*. To make it clearer, as I understand, we now have following: 1. All store

Re: [m5-dev] Review Request: Ruby: Change Address.hh

2011-02-25 Thread Nathan Binkert
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/504/#review896 --- The summary line is a pretty non-descriptive summary - Nathan On

Re: [m5-dev] Review Request: Ruby: Remove libruby_internal.hh

2011-02-25 Thread Nathan Binkert
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/506/#review897 --- It seems that this diff should just be folded into the remove libruby

Re: [m5-dev] Review Request: Ruby: Change DataBlock.hh

2011-02-25 Thread Nathan Binkert
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/503/#review898 --- Please make the summary more descriptive. For example: ruby: Make

Re: [m5-dev] Store Buffer

2011-02-25 Thread Steve Reinhardt
This sounds right. Ruby does need to forward invalidations to the CPU since some models (including O3) will need to do internal invalidations/flushes to maintain consistency. Others can choose to do it other ways (e.g., by querying the L1 at commit as you suggest), but they have the option of

Re: [m5-dev] Review Request: Ruby: Make Address.hh independent of RubySystem

2011-02-25 Thread Nilay Vaish
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/504/ --- (Updated 2011-02-25 10:51:09.206696) Review request for Default, Ali Saidi, Gabe

Re: [m5-dev] Review Request: Ruby: Make DataBlock.hh independent of RubySystem

2011-02-25 Thread Nilay Vaish
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/503/ --- (Updated 2011-02-25 10:51:51.189669) Review request for Default. Summary

Re: [m5-dev] Review Request: Ruby: Remove libruby_internal.hh

2011-02-25 Thread Nilay Vaish
On 2011-02-25 09:43:34, Nathan Binkert wrote: It seems that this diff should just be folded into the remove libruby diff. I will do that before committing these to repository. - Nilay --- This is an automatically generated e-mail.

[m5-dev] Functional Access support in Ruby

2011-02-25 Thread Nilay Vaish
Brad, Here is my understanding of the current state of functional accesses in gem5. As of now, all functional accesses are forwarded to the PhysicalMemory's MemoryPort. Instead, we would like to add recvFunctional() function to M5Port of the RubyPort, and attach this port as peer instead of

Re: [m5-dev] Review Request: Ruby: Remove store buffer

2011-02-25 Thread Brad Beckmann
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/507/#review900 --- Ship it! - Brad On 2011-02-25 08:33:43, Nilay Vaish wrote:

Re: [m5-dev] Review Request: Ruby: Remove libruby

2011-02-25 Thread Brad Beckmann
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/439/#review901 --- Ship it! - Brad On 2011-02-25 08:32:18, Nilay Vaish wrote:

Re: [m5-dev] Review Request: Ruby: Make Address.hh independent of RubySystem

2011-02-25 Thread Brad Beckmann
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/504/#review902 --- Ship it! - Brad On 2011-02-25 10:51:09, Nilay Vaish wrote:

Re: [m5-dev] Review Request: Ruby: Make DataBlock.hh independent of RubySystem

2011-02-25 Thread Brad Beckmann
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/503/#review903 --- Ship it! - Brad On 2011-02-25 10:51:51, Nilay Vaish wrote:

Re: [m5-dev] Functional Access support in Ruby

2011-02-25 Thread Beckmann, Brad
Yes, that is correct. The RubyPort::M5Port::recvFunctional() function is where we need to add the new support. Brad -Original Message- From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On Behalf Of Nilay Vaish Sent: Friday, February 25, 2011 12:20 PM To:

Re: [m5-dev] Store Buffer

2011-02-25 Thread Beckmann, Brad
It sounds like we are in agreement here, but I just want to make sure we clarify one item. I don't believe simply checking the coherence permissions at commit time can sufficiently support stronger consistency models like SC/TSO. Instead you need to really need to know whether you've ever

[m5-dev] changeset in m5: Ruby: Make Address.hh independent of RubySystem

2011-02-25 Thread Nilay Vaish
changeset 04078b1214dd in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=04078b1214dd description: Ruby: Make Address.hh independent of RubySystem This patch changes Address.hh so that it is not dependent on RubySystem. This dependence seems unecessary. All

[m5-dev] changeset in m5: Ruby: Remove libruby

2011-02-25 Thread Nilay Vaish
changeset 6782b51ae8a8 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=6782b51ae8a8 description: Ruby: Remove libruby This patch removes libruby_internal.hh, libruby.hh and libruby.cc. It moves the contents to libruby.hh to RubyRequest.hh and

[m5-dev] changeset in m5: Ruby: Remove store buffer

2011-02-25 Thread Nilay Vaish
changeset 05a2f6ac1f8e in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=05a2f6ac1f8e description: Ruby: Remove store buffer This patch removes the store buffer from Ruby. It is not in use currently. Since libruby is being and store buffer makes calls to

[m5-dev] Review Request: O3: Fix unaligned stores when cache blocked

2011-02-25 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/508/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[m5-dev] Review Request: Mem: Fix issue with dirty block being losted when entire block transfered to non-cache.

2011-02-25 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/509/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[m5-dev] Review Request: O3: Cleanup the commitInfo comm struct.

2011-02-25 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/510/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[m5-dev] Review Request: O3: Send instruction back to fetch on squash to seed predecoder correctly.

2011-02-25 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/511/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[m5-dev] Review Request: ARM: Detect and skip udelay() functions in linux kernel.

2011-02-25 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/512/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

Re: [m5-dev] Review Request: Mem: Fix issue with dirty block being losted when entire block transfered to non-cache.

2011-02-25 Thread Steve Reinhardt
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/509/#review904 --- Ship it! Looks good to me, other than the minor non-substantive change