But I need to find the point to log order of completion of loads and stores
in the LSQ (between LSQ and L1 cache), to check the effect of that change.
I was observing inside LSQUnitImpl::completeDataAccess(PacketPtr pkt).
But the order observed doesn't look like the expected.
Looks like you
Korey,
That idea of creating a fault was probably leading to a dead lock, as you
stated. Then, trying to stall the access as suggested, I added constraints
between stores in the Instruction Queue (actually inside MemDepUnit), where
only membar constraints were handled before. The simulator
Are your changes:
1) Causing the simulator to assert/panic/not function correctly.
or
2) Allowing the simulator to work but giving you unexpected results (bad
stats, etc.?)
If #2, it's a bigger picture issue and you'll need to add some debug
statements in the code to make sure that stores are
Steve, what about adding dependencies between stores in the Memory
Dependency Unit, should it do the trick or needs other modifications?
I've added the restrictions but the result wasn't the expected. Maybe I need
to make more changes in other places?
As I'm using SPARC, I'd need the processor to
Any ideas?
On Fri, Jan 21, 2011 at 5:00 PM, Eberle rambo.u...@gmail.com wrote:
Hi,
How can I enforce the reordering restriction between stores in the O3 (W-W
restriction)? To make an store to be executed only after all stores issued
before it were executed.
I tried adding this condition
Apparently not...
When you say it didn't work, what do you mean? Maybe if you ask some more
specific questions it will be easier for us to provide some clues.
Steve
On Tue, Jan 25, 2011 at 5:36 AM, Eberle rambo.u...@gmail.com wrote:
Any ideas?
On Fri, Jan 21, 2011 at 5:00 PM, Eberle
Right, what I need is to prevent the reordering of stores. The stores should
be executed in program order, the oldest store must be executed before a
younger store is allowed to execute.
Using O3 cpu and SPARC_SE.
When the following code is put before 'store_inst-initiateAcc();'
in
Hi,
How can I enforce the reordering restriction between stores in the O3 (W-W
restriction)? To make an store to be executed only after all stores issued
before it were executed.
I tried adding this condition in the executeStore method in
lsq_unit_impl.hh, but it didn't work:
if (store_idx !=
