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I still don't understand how the CPU ends up in a bad state. Could you
completeIFetch()
- initiateAcc() -- translation hits in TLB, page marked read only so fault
returned immediately
- finishTranslation() is called by the DTLB and a fault has been
generated
- translationFault()
- advanceInst()
-
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Ship it!
src/cpu/simple/timing.hh
On 2011-01-19 07:02:40, Steve Reinhardt wrote:
src/cpu/simple/timing.hh, line 114
http://reviews.m5sim.org/r/431/diff/1/?file=9738#file9738line114
It's interesting that we already had an ITBWaitResponse state defined
but had never used it before. Does it make sense to add an
Ah, ok, yes, that makes sense. It's another example of more happening
inside of a function than you expect, similar to the problem where a
trace data structure was being freed and then later used way back on the
stack. Things run farther and farther along until a delay is hit which
may be quite a
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- Gabe
On 2011-01-18 14:34:11, Ali Saidi wrote:
On 2011-01-19 16:22:22, Gabe Black wrote:
Review board lost the text of my review apparently. Your change looks good to
me.
- Gabe
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
