[m5-dev] MWAHAHAHAHAHAHAHAHAHA
A little over dramatic perhaps, and it's not quite right, but tada! Again! It even echoed when I typed! Freeing unused kernel memory: 232k freed INIT: version 2.86 booting /bin/bash: /sbin/rccùü¢+: No such file or directory /bin/baahh: /sbinnrr: No such file or directory INIT: Entering runlevel: 3 /bin/bash: /sbin/rccyðLý*: No such file or directory This is (none).unknown_domain (Linux x86_64 2.6.22.9) 00:00:05 (none) login: ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MWAHAHAHAHAHAHAHAHAHA
As someone who has had no part in this, I would like to say: Huzzah! Also, I need better support for /sbin/rccùü¢+ ;) Regards, Dan On Wed, Feb 4, 2009 at 3:08 AM, Gabe Black gbl...@eecs.umich.edu wrote: A little over dramatic perhaps, and it's not quite right, but tada! Again! It even echoed when I typed! Freeing unused kernel memory: 232k freed INIT: version 2.86 booting /bin/bash: /sbin/rccùü¢+: No such file or directory /bin/baahh: /sbinnrr: No such file or directory INIT: Entering runlevel: 3 /bin/bash: /sbin/rccyðLý*: No such file or directory This is (none).unknown_domain (Linux x86_64 2.6.22.9) 00:00:05 (none) login: ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- http://www.cs.wisc.edu/~gibson [esc]:wq! ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MWAHAHAHAHAHAHAHAHAHA
Awesome, Gabe! Congratulations again! Steve On Wed, Feb 4, 2009 at 1:08 AM, Gabe Black gbl...@eecs.umich.edu wrote: A little over dramatic perhaps, and it's not quite right, but tada! Again! It even echoed when I typed! Freeing unused kernel memory: 232k freed INIT: version 2.86 booting /bin/bash: /sbin/rccùü¢+: No such file or directory /bin/baahh: /sbinnrr: No such file or directory INIT: Entering runlevel: 3 /bin/bash: /sbin/rccyðLý*: No such file or directory This is (none).unknown_domain (Linux x86_64 2.6.22.9) 00:00:05 (none) login: ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MWAHAHAHAHAHAHAHAHAHA
Woo! Super awesome! We generally don't run init and do our own thing, so it should be even easier to move forward. What's next? Nate On Wed, Feb 4, 2009 at 1:08 AM, Gabe Black gbl...@eecs.umich.edu wrote: A little over dramatic perhaps, and it's not quite right, but tada! Again! It even echoed when I typed! Freeing unused kernel memory: 232k freed INIT: version 2.86 booting /bin/bash: /sbin/rccùü¢+: No such file or directory /bin/baahh: /sbinnrr: No such file or directory INIT: Entering runlevel: 3 /bin/bash: /sbin/rccyðLý*: No such file or directory This is (none).unknown_domain (Linux x86_64 2.6.22.9) 00:00:05 (none) login: ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MWAHAHAHAHAHAHAHAHAHA
I haven't looked into that yet, but I think it's probably from the file names getting garbled somehow before a call to exec. I'm not expecting that to be too hard to figure out (knock on wood). Quoting Ali Saidi sa...@umich.edu: Congrats!! What is with the file or directory not found errors? You should probably remove /sbin/login and replace it with a symlink to /bin/bash. Ali On Feb 4, 2009, at 10:04 AM, Lisa Hsu wrote: wooot! you are l33t!! :) Nice job Gabe. On Wed, Feb 4, 2009 at 4:08 AM, Gabe Black gbl...@eecs.umich.edu wrote: A little over dramatic perhaps, and it's not quite right, but tada! Again! It even echoed when I typed! Freeing unused kernel memory: 232k freed INIT: version 2.86 booting /bin/bash: /sbin/rccùü¢+: No such file or directory /bin/baahh: /sbinnrr: No such file or directory INIT: Entering runlevel: 3 /bin/bash: /sbin/rccyðLý*: No such file or directory This is (none).unknown_domain (Linux x86_64 2.6.22.9) 00:00:05 (none) login: ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MWAHAHAHAHAHAHAHAHAHA
Even if people wouldn't normally run init (the scripts, not /sbin/init I'm assuming), there's an error here that I'd like to fix. I'm expecting it's just that a string got mangled while being copied around so I shouldn't even have to dreg kernel innards to fix it. There are few things that are next. The first thing I'd like to do, after fixing the apparent issues with the output below, is to go back and fix up the two hacks I'm aware of that I have in my tree. The first is handling TLB misses more cleanly. The second is that my syscall tracer is still just stuck to the side of the exec tracer, but that should be mostly mechanical to correct. After that, I'd like to take care of the unimplemented instructions which are being skipped/warned about, support checkpointing, set up a golden model to compare execution against somehow, start working on 32 bit support in SE, and work on propagating my new message based interrupt scheme into the other ISAs. I'd also like to try other kernel versions/compiles with other config options to see what errors those expose. Beyond that, in no particular order, I'd like to work on some sort of BIOS/boot loader set up so I can boot all the way from power on to power off, add minimal ACPI support, fill out my SMBios table, add a simple graphics device of some sort, and try to tighten up performance. Performance might actually be something to work on earlier since it would make all the other work a little more palatable. There are stretch marks on the simple CPU specifically from the microcode stuff but also unaligned memory accesses which I'd like to address at some point. Gabe Quoting nathan binkert n...@binkert.org: Woo! Super awesome! We generally don't run init and do our own thing, so it should be even easier to move forward. What's next? Nate On Wed, Feb 4, 2009 at 1:08 AM, Gabe Black gbl...@eecs.umich.edu wrote: A little over dramatic perhaps, and it's not quite right, but tada! Again! It even echoed when I typed! Freeing unused kernel memory: 232k freed INIT: version 2.86 booting /bin/bash: /sbin/rccùü¢+: No such file or directory /bin/baahh: /sbinnrr: No such file or directory INIT: Entering runlevel: 3 /bin/bash: /sbin/rccyðLý*: No such file or directory This is (none).unknown_domain (Linux x86_64 2.6.22.9) 00:00:05 (none) login: ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MWAHAHAHAHAHAHAHAHAHA
Hi Gabe, I just wanted to chime in and say good work! I'm sure lots of people will benefit from your x86 efforts so you should feel very good about yourself! On Wed, Feb 4, 2009 at 3:07 PM, gbl...@eecs.umich.edu wrote: Even if people wouldn't normally run init (the scripts, not /sbin/init I'm assuming), there's an error here that I'd like to fix. I'm expecting it's just that a string got mangled while being copied around so I shouldn't even have to dreg kernel innards to fix it. There are few things that are next. The first thing I'd like to do, after fixing the apparent issues with the output below, is to go back and fix up the two hacks I'm aware of that I have in my tree. The first is handling TLB misses more cleanly. The second is that my syscall tracer is still just stuck to the side of the exec tracer, but that should be mostly mechanical to correct. After that, I'd like to take care of the unimplemented instructions which are being skipped/warned about, support checkpointing, set up a golden model to compare execution against somehow, start working on 32 bit support in SE, and work on propagating my new message based interrupt scheme into the other ISAs. I'd also like to try other kernel versions/compiles with other config options to see what errors those expose. Beyond that, in no particular order, I'd like to work on some sort of BIOS/boot loader set up so I can boot all the way from power on to power off, add minimal ACPI support, fill out my SMBios table, add a simple graphics device of some sort, and try to tighten up performance. Performance might actually be something to work on earlier since it would make all the other work a little more palatable. There are stretch marks on the simple CPU specifically from the microcode stuff but also unaligned memory accesses which I'd like to address at some point. Gabe Quoting nathan binkert n...@binkert.org: Woo! Super awesome! We generally don't run init and do our own thing, so it should be even easier to move forward. What's next? Nate On Wed, Feb 4, 2009 at 1:08 AM, Gabe Black gbl...@eecs.umich.edu wrote: A little over dramatic perhaps, and it's not quite right, but tada! Again! It even echoed when I typed! Freeing unused kernel memory: 232k freed INIT: version 2.86 booting /bin/bash: /sbin/rccùü¢+: No such file or directory /bin/baahh: /sbinnrr: No such file or directory INIT: Entering runlevel: 3 /bin/bash: /sbin/rccyðLý*: No such file or directory This is (none).unknown_domain (Linux x86_64 2.6.22.9) 00:00:05 (none) login: ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Ali: webnew suffering from 404 and Out-Of-Order packets and TCP retransmission
Rick, 1) Just to follow up, did you figure out a good speed for the checkpoint producing run? 2) Did you ever find why everything was 404'ed? Lisa On Wed, Jan 28, 2009 at 9:44 PM, Lisa Hsu h...@eecs.umich.edu wrote: I couldn't say exactly, so much in M5 has changed since that paper to give an exact number, but I'd imagine whatever instructions/second you're getting in the detailed, if you make the checkpoint run the appropriate speed considering its 1 IPC, you'd probably be in the right range. Lisa On Wed, Jan 28, 2009 at 8:26 PM, Rick Strong rstr...@cs.ucsd.edu wrote: The clock rate on the server is only set to 1GHz on the checkpoint run (as opposed to 3GHz for the detailed simulation). How slow should it be set? Are we talking nearer to 250MHz? Thanks, -Rick Ali Saidi wrote: That's almost certainly what is happening. Different packets are trying to be sent, both originating from the kernel. This isn't a device bug. It's exactly what that paper described. The delay observed by the server has changed dramatically, that a retransmit is occurring because since the ack didn't arrive in twice the round trip latency. You should add some latency to the ethernet link, and drive the server with a slower CPU during the checkpoint run. That will normally fix the problem. Ali On Jan 28, 2009, at 5:59 PM, Rick Strong wrote: This is an interesting. Thanks for the link. -Rick Lisa Hsu wrote: Your description that it only occurs when you switch to a timing sim makes me think of this (not to toot my own horn or anything): http://www.eecs.umich.edu/~hsul/pubs/mobs05.pdfhttp://www.eecs.umich.edu/%7Ehsul/pubs/mobs05.pdf http://www.eecs.umich.edu/%7Ehsul/pubs/mobs05.pdf Just throwing that out as a possibility. You might want to slow down your checkpoint dropping run so that it's not so disruptive when you switch over to timing. Lisa On Wed, Jan 28, 2009 at 5:32 PM, Rick Strong rstr...@cs.ucsd.edu mailto:rstr...@cs.ucsd.edu wrote: I have posted tar.gz files that include EthernetAll output (in ethernet_all.trace) @ http://rickshin.ucsd.edu. Once you have a chance, if you could take a look at the trace and figure what is wrong that is great. I ended restoring from the checkpoint for two runs. One run stays in atomic mode while the other switches to timing and detailed. The run that stays in atomic mode works fine. This leads me to believe that the checkpoint restore mechanism is fine. The fault likely lies in the switching to timing or detailed mdoe. The differences between the runs: (1) m5out-atomic-run-aftercheckpoint.tar.gz is a run that stays in atomic mode (no switching to timing mode) (2) m5out-timing-run-aftercheckpoint.tar.gz is a run that switches to timing and then to detailed mode. Thanks and good luck, -Rick Ali Saidi wrote: Looking at the trace, it appears as though you just restored from a checkpoint. Is this the case? If so, what does the checkpoint dropping run do after that checkpoint is created? It's so early in the trace that I would guess it's a serialization bug, particularly in the TSO code. However, I looked quickly at the code and and nothing seemed to jump out at me. If you can provide me with an EthernetAll trace from the checkpoint run and from the restored run I can work on figuring out what the problem is. Ali On Jan 28, 2009, at 2:53 AM, Rick Strong wrote: There are three possibilities here: a) A kernel bug b) a device model/driver bug c) a checkpointing bug (as it relates to (b)) What kernel version are you using? Could you put the ethernet trace somewhere so I could look at it? Ali I am using the kernel 2.6.18 with M5 patches. I have put the ethernet traces up at http://rickshin.ucsd.edu. It is the only link. If you take a look, let me know what you think. Best, -Rick ___ m5-dev mailing list m5-dev@m5sim.org mailto:m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org mailto:m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org mailto:m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in inorder-patches: ignore some stuff
changeset 040d328ce5de in /z/repo/inorder-patches details: inorder-patches?cmd=changeset;node=040d328ce5de description: ignore some stuff diffstat: 1 file changed, 4 insertions(+) .hgignore |4 diffs (8 lines): diff -r cd969187e2d3 -r 040d328ce5de .hgignore --- /dev/null Thu Jan 01 00:00:00 1970 + +++ b/.hgignore Wed Feb 04 16:32:10 2009 -0800 @@ -0,0 +1,4 @@ +syntax: glob +guards +status +*~ ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in inorder-patches: Fix some copyrights
changeset cd969187e2d3 in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=cd969187e2d3
description:
Fix some copyrights
diffstat:
1 file changed, 566 insertions(+), 646 deletions(-)
import_mixie | 1212 +++---
diffs (truncated from 1772 to 300 lines):
diff -r 0b6421ada742 -r cd969187e2d3 import_mixie
--- a/import_mixie Wed Feb 04 14:00:21 2009 -0800
+++ b/import_mixie Wed Feb 04 16:31:44 2009 -0800
@@ -1,63 +1,7 @@
-diff -r db1653549204 src/arch/mips/locked_mem.hh
a/src/arch/mips/locked_mem.hh Thu Nov 20 19:08:46 2008 -0800
-+++ b/src/arch/mips/locked_mem.hh Mon Nov 24 18:03:46 2008 -0500
-@@ -1,31 +1,31 @@
- /*
-- * Copyright (c) 2006-2007 The Regents of The University of Michigan
-- * All rights reserved.
-+ * Copyright (c) 2006, 2007
-+ * The Regents of The University of Michigan
-+ * All Rights Reserved
- *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are
-- * met: redistributions of source code must retain the above copyright
-- * notice, this list of conditions and the following disclaimer;
-- * redistributions in binary form must reproduce the above copyright
-- * notice, this list of conditions and the following disclaimer in the
-- * documentation and/or other materials provided with the distribution;
-- * neither the name of the copyright holders nor the names of its
-- * contributors may be used to endorse or promote products derived from
-- * this software without specific prior written permission.
-+ * This code is part of the M5 simulator.
- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ * Permission is granted to use, copy, create derivative works and
-+ * redistribute this software and such derivative works for any
-+ * purpose, so long as the copyright notice above, this grant of
-+ * permission, and the disclaimer below appear in all copies made; and
-+ * so long as the name of The University of Michigan is not used in
-+ * any advertising or publicity pertaining to the use or distribution
-+ * of this software without specific, written prior authorization.
- *
-- * Authors: Steve Reinhardt
-+ * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
-+ * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
-+ * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
-+ * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
-+ * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
-+ * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
-+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
-+ * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGES.
-+ *
-+ * Authors: Steven K. Reinhardt
- */
-
- #ifndef __ARCH_MIPS_LOCKED_MEM_HH__
-@@ -49,10 +49,11 @@ inline void
+diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
+--- a/src/arch/mips/locked_mem.hh
b/src/arch/mips/locked_mem.hh
+@@ -49,10 +49,11 @@
inline void
handleLockedRead(XC *xc, Request *req)
{
@@ -72,7 +16,7 @@
}
-@@ -60,20 +61,22 @@ inline bool
+@@ -60,20 +61,22 @@
inline bool
handleLockedWrite(XC *xc, Request *req)
{
@@ -98,7 +42,7 @@
// the rest of this code is not architectural;
// it's just a debugging aid to help detect
-@@ -82,22 +85,22 @@ handleLockedWrite(XC *xc, Request *req)
+@@ -82,22 +85,22 @@
int stCondFailures = xc-readStCondFailures();
stCondFailures++;
xc-setStCondFailures(stCondFailures);
@@ -127,10 +71,10 @@
}
// store conditional failed already, so don't issue it to mem
return false;
-diff -r db1653549204 src/cpu/SConscript
a/src/cpu/SConscript Thu Nov 20 19:08:46 2008 -0800
-+++ b/src/cpu/SConscript Mon Nov 24 18:03:46 2008 -0500
-@@ -54,6 +54,8 @@ virtual Fault completeAcc(Packet *pkt, %
+diff --git a/src/cpu/SConscript b/src/cpu/SConscript
+---
