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> I'm not sure I all the way understand why the register file shouldnt be
> defined in the ISA...
>
> I could see maybe there being one standard integer and floating point
> register file thats totally generic however, the system/miscellaneous
> registers are pretty ISA dependent so those register
> It's only a few instructions to push three registers on the stack, use
> the appropriate instruction, pop those three, and return. All together
> it's 11 bytes.
I don't think one can claim copyright on 11 bytes.
Nate
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I'm not sure I all the way understand why the register file shouldnt be
defined in the ISA...
I could see maybe there being one standard integer and floating point
register file thats totally generic however, the system/miscellaneous
registers are pretty ISA dependent so those register probably ne
nathan binkert wrote:
>> If #2 didnt exist, then that would make more sense to me. That would make an
>> instruction HAVE to use the threadContext interface to access any CPU
>> facilities. That would also remove the CPU pointer from the instruction
>> object as well.
>>
>> If that were the solutio
nathan binkert wrote:
>>In x86 there are at least three different ways to call a system
>> call, int $0x80, sysenter, and syscall. In 64 bit mode I think syscall
>> is pretty much guaranteed to be there so glibc uses it directly, or at
>> least that's been my experience. For 32 bit x86, though,
> If #2 didnt exist, then that would make more sense to me. That would make an
> instruction HAVE to use the threadContext interface to access any CPU
> facilities. That would also remove the CPU pointer from the instruction
> object as well.
>
> If that were the solution, I would be OK with it, be
>In x86 there are at least three different ways to call a system
> call, int $0x80, sysenter, and syscall. In 64 bit mode I think syscall
> is pretty much guaranteed to be there so glibc uses it directly, or at
> least that's been my experience. For 32 bit x86, though, sysenter, the
> preferred
> Also, could someone explain how the idleCycle count compares to the kernel
> stat "mode_ticks_idle"? Obviously, one is in cycles and the other one is in
> ticks, but they seem to be capturing two different behaviors.
mode_ticks_idle is idle as reported by the kernel. That is, the
cycles where
Also, could someone explain how the idleCycle count compares to the
kernel stat "mode_ticks_idle"? Obviously, one is in cycles and the
other one is in ticks, but they seem to be capturing two different
behaviors.
Thanks,
Brad
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5s
OK, the kernel stats fix is easy enough.
As far as idleCycles, I have another question: in O3, this appears to be
measuring the number of cycles the model is not ticked, regardless of
whether it's due to explicit idling (e.g., due to the quiesce instruction in
Alpha) or due to a general pipeline s
You're right, thanks Gabe. That's the first time (that I know of) that one
of my own emails ended up in my own spam box. Heh.
Lisa
On Mon, Feb 16, 2009 at 6:28 PM, Gabe Black wrote:
> I got one for your recent push unless there was more than one. Sometimes
> mine get caught in the spam filter
I got one for your recent push unless there was more than one. Sometimes
mine get caught in the spam filter so you might want to check in your
junk folder.
Gabe
Lisa Hsu wrote:
> hey guys,
>
> i just pushed something and haven't gotten an email notification - has
> anyone else?
>
> lisa
> ---
hey guys,
i just pushed something and haven't gotten an email notification - has
anyone else?
lisa
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changeset 9fe574944f31 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9fe574944f31
description:
sycalls: implement mremap() and add DATA flag for getrlimit(). mremap
has been tested on Alpha, compiles for the rest but not tested. I don't see why
it wouldn't work though
Just looking at the output seems to indicate that you've done
something funny with your mercurial setup. Do you have mq in both
your .hgrc file and in /etc/mercurial?
Nate
2009/2/16 Korey Sewell :
> Hey all,
> I am currently unable to build any CPU Model successfully after the scons
> update..
Hey all,
I am currently unable to build any CPU Model successfully after the scons
update...0
Other people seem to be doing just fine, so am I missing something?
My error message has something to do with generating a defines.py file:
makeDefinesPyFile(["build/ALPHA_SE/python/m5/defines.py"], [{'A
I agree that having both optimized and unoptimized binaries for at least
some workloads is useful for regressions, but I'm not convinced it's a huge
loss to require different names for them... you'd get some duplication in
the input files but that's about it. However, there are enough things that
This is the mail system at host daystrom.m5sim.org.
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changeset 7202be891bb4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7202be891bb4
description:
Update stats for new prefetching fixes.
Prefetching is not enabled in any of our regressions, so no significant
stat values have changed, but zero-valued prefe
changeset d82be3235ab4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d82be3235ab4
description:
Fixes to get prefetching working again.
Apparently we broke it with the cache rewrite and never noticed.
Thanks to Bao Yungang for a significant part
Regarding the kernel stats, I had assumed that in taking over for
another CPU, you'd still want to keep the same kernel statistics
because you're still running the same system. I didn't realize that
the stats would be registered to each CPU and thus create fairly
confusing output. Unless Nate
I have a 32 bit hello world working, and thinking about making it
part of the regressions reminded me of when I was doing something
similar for SPARC. Back then I didn't find a good way for 32 bit and 64
bit benchmarks/binaries to exist in the regression system at the same
time since they're al
* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic passed.
* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-ti
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