[m5-dev] changeset in m5: getopt: Remove GPL code.

[Nathan Binkert]

changeset baf4b5f6782e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=baf4b5f6782e
description:
getopt: Remove GPL code.
This code is unused and should never have been committed

diffstat:

 src/mem/ruby/tester/SConscript|1 -
 src/mem/ruby/tester/getopt.cc |  945 --
 src/mem/ruby/tester/getopt.hh |  129 
 src/mem/ruby/tester/test_framework.cc |1 -
 4 files changed, 0 insertions(+), 1076 deletions(-)

diffs (truncated from 1104 to 300 lines):

diff -r 05a2f6ac1f8e -r baf4b5f6782e src/mem/ruby/tester/SConscript
--- a/src/mem/ruby/tester/SConscriptFri Feb 25 17:55:20 2011 -0600
+++ b/src/mem/ruby/tester/SConscriptSat Feb 26 21:43:11 2011 -0800
@@ -34,7 +34,6 @@
 Return()
 
 #Source('SpecifiedGenerator.cc')
-#Source('getopt.cc')
 #Source('main.cc')
 #Source('test_framework.cc')
 #Source('RaceyDriver.cc')
diff -r 05a2f6ac1f8e -r baf4b5f6782e src/mem/ruby/tester/getopt.cc
--- a/src/mem/ruby/tester/getopt.cc Fri Feb 25 17:55:20 2011 -0600
+++ /dev/null   Thu Jan 01 00:00:00 1970 +
@@ -1,945 +0,0 @@
-/* Getopt for GNU.
-   NOTE: getopt is now part of the C library, so if you don't know what
-   "Keep this file name-space clean" means, talk to rol...@gnu.ai.mit.edu
-   before changing it!
-
-   Copyright (C) 1987, 88, 89, 90, 91, 92, 93, 94, 95
-Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify it
-   under the terms of the GNU General Public License as published by the
-   Free Software Foundation; either version 2, or (at your option) any
-   later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-/* This tells Alpha OSF/1 not to define a getopt prototype in .
-   Ditto for AIX 3.2 and .  */
-#ifndef _NO_PROTO
-#define _NO_PROTO
-#endif
-
-#ifdef HAVE_CONFIG_H
-#include 
-#endif
-
-#if !defined (__STDC__) || !__STDC__
-/* This is a separate conditional since some stdc systems
-   reject `defined (const)'.  */
-#ifndef const
-#define const
-#endif
-#endif
-
-#include 
-
-/* Comment out all this code if we are using the GNU C Library, and are not
-   actually compiling the library itself.  This code is part of the GNU C
-   Library, but also included in many other GNU distributions.  Compiling
-   and linking in this code is a waste when using the GNU C library
-   (especially if it is a shared library).  Rather than having every GNU
-   program understand `configure --with-gnu-libc' and omit the object files,
-   it is simpler to just do this in the source for each such file.  */
-
-#if defined (_LIBC) || !defined (__GNU_LIBRARY__)
-
-
-/* This needs to come after some library #include
-   to get __GNU_LIBRARY__ defined.  */
-#ifdef  __GNU_LIBRARY__
-/* Don't include stdlib.h for non-GNU C libraries because some of them
-   contain conflicting prototypes for getopt.  */
-#include 
-#endif  /* GNU C library.  */
-
-/* This is for other GNU distributions with internationalized messages.
-   The GNU C Library itself does not yet support such messages.  */
-#if HAVE_LIBINTL_H
-# include 
-#else
-# define gettext(msgid) (msgid)
-#endif
-
-/* This version of `getopt' appears to the caller like standard Unix `getopt'
-   but it behaves differently for the user, since it allows the user
-   to intersperse the options with the other arguments.
-
-   As `getopt' works, it permutes the elements of ARGV so that,
-   when it is done, all the options precede everything else.  Thus
-   all application programs are extended to handle flexible argument order.
-
-   Setting the environment variable POSIXLY_CORRECT disables permutation.
-   Then the behavior is completely standard.
-
-   GNU application programs can use a third alternative mode in which
-   they can distinguish the relative order of options and other arguments.  */
-
-#include "mem/ruby/tester/getopt.hh"
-
-/* For communication from `getopt' to the caller.
-   When `getopt' finds an option that takes an argument,
-   the argument value is returned here.
-   Also, when `ordering' is RETURN_IN_ORDER,
-   each non-option ARGV-element is returned here.  */
-
-char *optarg = NULL;
-
-/* Index in ARGV of the next element to be scanned.
-   This is used for communication to and from the caller
-   and for communication between successive calls to `getopt'.
-
-   On entry to `getopt', zero means this is the first call; initialize.
-
-   When `getopt' returns EOF, this is the index of the first of the
-   non-option elements that the caller should itself scan.
-
-   Otherwise, `optind' c

Re: [m5-dev] Review Request: Main: Create long talked about output-conference-paper option.

[Nathan Binkert]

> On 2011-02-26 17:09:28, Nathan Binkert wrote:
> > Perhaps we should make this the top of --help.  How about this as an 
> > alternate implementation for --output-conference-paper
> > 
> > import os
> > import urllib
> > import webbrowser
> > 
> > try:
> > import pwd
> > uname = os.getlogin()
> > pw = pwd.getpwnam(uname)
> > user = pw.pw_gecos.split(',')[0]
> > except:
> > user = "M5 User"
> > 
> > user = urllib.quote_plus(user)
> > 
> > print user
> > 
> > url = "http://apps.pdos.lcs.mit.edu/cgi-bin/scigen.cgi?author=%s";
> > webbrowser.open(url % user)
> >

oops.  Remove the "print user"


- Nathan


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---


On 2011-02-26 14:16:37, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/516/
> ---
> 
> (Updated 2011-02-26 14:16:37)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> Main: Create long talked about output-conference-paper option.
> 
> 
> Diffs
> -
> 
>   src/python/m5/main.py 05a2f6ac1f8e 
> 
> Diff: http://reviews.m5sim.org/r/516/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

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Re: [m5-dev] Review Request: Main: Create long talked about output-conference-paper option.

[Nathan Binkert]

---
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---

Ship it!


Perhaps we should make this the top of --help.  How about this as an alternate 
implementation for --output-conference-paper

import os
import urllib
import webbrowser

try:
import pwd
uname = os.getlogin()
pw = pwd.getpwnam(uname)
user = pw.pw_gecos.split(',')[0]
except:
user = "M5 User"

user = urllib.quote_plus(user)

print user

url = "http://apps.pdos.lcs.mit.edu/cgi-bin/scigen.cgi?author=%s";
webbrowser.open(url % user)


- Nathan


On 2011-02-26 14:16:37, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/516/
> ---
> 
> (Updated 2011-02-26 14:16:37)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> Main: Create long talked about output-conference-paper option.
> 
> 
> Diffs
> -
> 
>   src/python/m5/main.py 05a2f6ac1f8e 
> 
> Diff: http://reviews.m5sim.org/r/516/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

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Re: [m5-dev] Review Request: O3: Send instruction back to fetch on squash to seed predecoder correctly.

[Gabe Black]

---
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---


I see what you're doing here, I think. For the strategy your taking your 
implementation seems ok (other than some weird whitespace), but I'm not sure 
this is the way to go. The itstate should be part of the pc and then wouldn't 
depend on anything in the previous instruction. The way you've implemented this 
forced itstate stuff may be the real culprit. I don't remember all the details 
of our previous conversation about it, but I do remember suggesting a way to 
implement that that fit better with the rest of the pc state information and I 
expect would make this change unnecessary.


src/arch/arm/predecoder.hh


Why all the extra blank lines?


- Gabe


On 2011-02-25 21:05:49, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/511/
> ---
> 
> (Updated 2011-02-25 21:05:49)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> O3: Send instruction back to fetch on squash to seed predecoder correctly.
> 
> 
> Diffs
> -
> 
>   src/arch/alpha/predecoder.hh 9dc17725f795 
>   src/arch/arm/predecoder.hh 9dc17725f795 
>   src/arch/mips/predecoder.hh 9dc17725f795 
>   src/arch/power/predecoder.hh 9dc17725f795 
>   src/arch/sparc/predecoder.hh 9dc17725f795 
>   src/arch/x86/predecoder.hh 9dc17725f795 
>   src/cpu/o3/cpu.cc 9dc17725f795 
>   src/cpu/o3/fetch.hh 9dc17725f795 
>   src/cpu/o3/fetch_impl.hh 9dc17725f795 
> 
> Diff: http://reviews.m5sim.org/r/511/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

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Re: [m5-dev] Review Request: O3: Cleanup the commitInfo comm struct.

[Gabe Black]

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---


I don't see anything obviously wrong here, although I'm sure it wouldn't be 
hard to slip a bug into this code accidentally. Please be sure to run all the 
regressions just in case.


src/cpu/o3/comm.hh


You have two sentences mushed together here.


- Gabe


On 2011-02-25 21:04:59, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/510/
> ---
> 
> (Updated 2011-02-25 21:04:59)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> O3: Cleanup the commitInfo comm struct.
> 
> Get rid of unused members and use base types rather than derrived values
> where possible to limit amount of state. This cleans up a change to the
> fetch stage I promised Steve a month ago.
> 
> 
> Diffs
> -
> 
>   src/cpu/o3/comm.hh 9dc17725f795 
>   src/cpu/o3/commit.hh 9dc17725f795 
>   src/cpu/o3/commit_impl.hh 9dc17725f795 
>   src/cpu/o3/fetch_impl.hh 9dc17725f795 
>   src/cpu/o3/iew_impl.hh 9dc17725f795 
> 
> Diff: http://reviews.m5sim.org/r/510/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

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Re: [m5-dev] Functional Access support in Ruby

[Nilay Vaish]

Brad,

I don't recall if talked about the following situtation on Tuesday -- 
suppose we have a functional access for an address A. Further assume that 
the corresponding cache block is in base state in all the caches (if 
present). But there is timing access to this block which is currently in 
some message buffer, or the request has not been yet issued due to lack of 
resources.


Current implementation of functional accesses takes in to account the 
timing accesses that are inflight (refer to the function checkFunctional() 
in src/mem/packet.cc).


I think, if do add code to detect such cases, then we should return that 
the functional access failed. Consider the case when two timing accesses 
to same address (both are writes) are inflight and there is a functional 
read access to that address. In this case, we would not be able to decide 
which value to return for the read.


Nilay

On Fri, 25 Feb 2011, Beckmann, Brad wrote:


Yes, that is correct.  The RubyPort::M5Port::recvFunctional() function is where 
we need to add the new support.

Brad



-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
On Behalf Of Nilay Vaish
Sent: Friday, February 25, 2011 12:20 PM
To: m5-dev@m5sim.org
Subject: [m5-dev] Functional Access support in Ruby

Brad,

Here is my understanding of the current state of functional accesses in gem5.
As of now, all functional accesses are forwarded to the PhysicalMemory's
MemoryPort. Instead, we would like to add
recvFunctional() function to M5Port of the RubyPort, and attach this port as
peer instead of the PhysicalMemory.

--
Nilay
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Re: [m5-dev] Review Request: O3: Implement memory mapped IPRs for O3.

[Gabe Black]

While trying to fix another problem, I reworked the load part of this to
look more like a load satisfied by store to load forwarding than one
that came back from the memory system. It didn't turn out to be
necessary to fix what I was working on, but I like this version better
since it's simpler and probably performs a little better.

Gabe

On 02/26/11 16:31, Gabe Black wrote:
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/502/
>
>
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt,
> and Nathan Binkert.
> By Gabe Black.
>
> /Updated 2011-02-26 16:31:51.117900/
>
>
>   Description
>
> O3: Implement memory mapped IPRs for O3.
>
>
>   Diffs (updated)
>
> * src/cpu/o3/lsq_unit.hh (ac1bd3d1aa54)
> * src/cpu/o3/lsq_unit_impl.hh (ac1bd3d1aa54)
>
> View Diff 
>
>
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Re: [m5-dev] Review Request: O3: Implement memory mapped IPRs for O3.

[Gabe Black]

---
This is an automatically generated e-mail. To reply, visit:
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---

(Updated 2011-02-26 16:31:51.117900)


Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

O3: Implement memory mapped IPRs for O3.


Diffs (updated)
-

  src/cpu/o3/lsq_unit.hh ac1bd3d1aa54 
  src/cpu/o3/lsq_unit_impl.hh ac1bd3d1aa54 

Diff: http://reviews.m5sim.org/r/502/diff


Testing
---


Thanks,

Gabe

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Re: [m5-dev] Review Request: X86: Use regular read requests in the walker instead of read exclusive.

[Gabe Black]

> On 2011-02-26 08:36:58, Steve Reinhardt wrote:
> > I won't vouch for the surrounding code (I don't get the difference between 
> > the oldRead, read, and write packets, for starters), but this one specific 
> > line that's changed looks good to me :-)

oldRead is the read that just returned data, read and write are the packets 
that should go out to continue with the walk. The writes are to update accessed 
and dirty bits, and the new read is to access the next entry. I also missed an 
instance of ReadExReq which I just added to the patch.


- Gabe


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---


On 2011-02-26 16:21:29, Gabe Black wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/514/
> ---
> 
> (Updated 2011-02-26 16:21:29)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> X86: Use regular read requests in the walker instead of read exclusive.
> 
> 
> Diffs
> -
> 
>   src/arch/x86/pagetable_walker.cc ac1bd3d1aa54 
> 
> Diff: http://reviews.m5sim.org/r/514/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Gabe
> 
>

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Re: [m5-dev] Review Request: X86: Use regular read requests in the walker instead of read exclusive.

[Gabe Black]

---
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---

(Updated 2011-02-26 16:21:29.974813)


Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

X86: Use regular read requests in the walker instead of read exclusive.


Diffs (updated)
-

  src/arch/x86/pagetable_walker.cc ac1bd3d1aa54 

Diff: http://reviews.m5sim.org/r/514/diff


Testing
---


Thanks,

Gabe

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Re: [m5-dev] Functional Access support in Ruby

[Nilay Vaish]

I am talking about real silicon. Then, how does gdb makes changes to 
values of variables?


Nilay


On Sat, 26 Feb 2011, Beckmann, Brad wrote:


Hi Nilay,

What exactly are you referring to as the "underlying processor"?  Are you 
referring to real silicon?

Actual hardware doesn't support functional accesses.  Functional 
accesses are unique to gem5 and are completely fake when compared to 
actual hardware.  gem5 could support functional accesses by quiescing 
the system and then perform the read or write using the existing timing 
path.  That would probably be a suitable solution if gdb running on the 
simulated system was the only source of dynamic functional accesses. 
However, there are other sources of dynamic functional accesses and we 
don't want to always perturb the system when performing those accesses. 
Thus we need a backdoor that doesn't perturb the system.


Brad



-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On
Behalf Of Nilay Vaish
Sent: Saturday, February 26, 2011 9:06 AM
To: M5 Developer List
Subject: Re: [m5-dev] Functional Access support in Ruby

I was thinking about the behavior of functional accesses. Currently in
gdb
we can change the value of a program variable. Does that mean the
underlying processor supports functional accesses? If yes, then we
should
already have some knowledge about what is expected from functional
accesses.

Nilay


On Fri, 25 Feb 2011, Beckmann, Brad wrote:


Yes, that is correct.  The RubyPort::M5Port::recvFunctional()

function is where we need to add the new support.


Brad



-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
On Behalf Of Nilay Vaish
Sent: Friday, February 25, 2011 12:20 PM
To: m5-dev@m5sim.org
Subject: [m5-dev] Functional Access support in Ruby

Brad,

Here is my understanding of the current state of functional accesses

in gem5.

As of now, all functional accesses are forwarded to the

PhysicalMemory's

MemoryPort. Instead, we would like to add
recvFunctional() function to M5Port of the RubyPort, and attach this

port as

peer instead of the PhysicalMemory.

--
Nilay
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Re: [m5-dev] Review Request: Main: Create long talked about output-conference-paper option.

[Thomas Wenisch]

I was extremely excited about this new option till I discovered it only printed 
out help text...  Ali, why can't you implement it properly?  It doesn't even 
need to work in general, just for the configurations I care to run.

Sent from my iPhone

On Feb 26, 2011, at 4:25 PM, "Gabe Black"  wrote:

> This is an automatically generated e-mail. To reply, visit: 
> http://reviews.m5sim.org/r/516/
> 
> Yeah, lets not. I don't think those users will get or appreciate an inside 
> joke at their expense, and we risk insulting other users by insinuating we 
> expected to need to tell them that.
> 
> - Gabe
> 
> 
> On February 26th, 2011, 2:16 p.m., Ali Saidi wrote:
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> By Ali Saidi.
> Updated 2011-02-26 14:16:37
> 
> Description
> 
> Main: Create long talked about output-conference-paper option.
> Diffs
> 
> src/python/m5/main.py (05a2f6ac1f8e)
> View Diff
> 
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Re: [m5-dev] Functional Access support in Ruby

[Beckmann, Brad]

Hi Nilay,

What exactly are you referring to as the "underlying processor"?  Are you 
referring to real silicon?

Actual hardware doesn't support functional accesses.  Functional accesses are 
unique to gem5 and are completely fake when compared to actual hardware.  gem5 
could support functional accesses by quiescing the system and then perform the 
read or write using the existing timing path.  That would probably be a 
suitable solution if gdb running on the simulated system was the only source of 
dynamic functional accesses.  However, there are other sources of dynamic 
functional accesses and we don't want to always perturb the system when 
performing those accesses.  Thus we need a backdoor that doesn't perturb the 
system.

Brad


> -Original Message-
> From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On
> Behalf Of Nilay Vaish
> Sent: Saturday, February 26, 2011 9:06 AM
> To: M5 Developer List
> Subject: Re: [m5-dev] Functional Access support in Ruby
> 
> I was thinking about the behavior of functional accesses. Currently in
> gdb
> we can change the value of a program variable. Does that mean the
> underlying processor supports functional accesses? If yes, then we
> should
> already have some knowledge about what is expected from functional
> accesses.
> 
> Nilay
> 
> 
> On Fri, 25 Feb 2011, Beckmann, Brad wrote:
> 
> > Yes, that is correct.  The RubyPort::M5Port::recvFunctional()
> function is where we need to add the new support.
> >
> > Brad
> >
> >
> >> -Original Message-
> >> From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
> >> On Behalf Of Nilay Vaish
> >> Sent: Friday, February 25, 2011 12:20 PM
> >> To: m5-dev@m5sim.org
> >> Subject: [m5-dev] Functional Access support in Ruby
> >>
> >> Brad,
> >>
> >> Here is my understanding of the current state of functional accesses
> in gem5.
> >> As of now, all functional accesses are forwarded to the
> PhysicalMemory's
> >> MemoryPort. Instead, we would like to add
> >> recvFunctional() function to M5Port of the RubyPort, and attach this
> port as
> >> peer instead of the PhysicalMemory.
> >>
> >> --
> >> Nilay
> >> ___
> >> m5-dev mailing list
> >> m5-dev@m5sim.org
> >> http://m5sim.org/mailman/listinfo/m5-dev
> >
> >
> > ___
> > m5-dev mailing list
> > m5-dev@m5sim.org
> > http://m5sim.org/mailman/listinfo/m5-dev
> >
> ___
> m5-dev mailing list
> m5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/m5-dev


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Re: [m5-dev] Review Request: Main: Create long talked about output-conference-paper option.

[Gabe Black]

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---


Yeah, lets not. I don't think those users will get or appreciate an inside joke 
at their expense, and we risk insulting other users by insinuating we expected 
to need to tell them that.

- Gabe


On 2011-02-26 14:16:37, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/516/
> ---
> 
> (Updated 2011-02-26 14:16:37)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> Main: Create long talked about output-conference-paper option.
> 
> 
> Diffs
> -
> 
>   src/python/m5/main.py 05a2f6ac1f8e 
> 
> Diff: http://reviews.m5sim.org/r/516/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

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[m5-dev] Review Request: Main: Create long talked about output-conference-paper option.

[Ali Saidi]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/516/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

Main: Create long talked about output-conference-paper option.


Diffs
-

  src/python/m5/main.py 05a2f6ac1f8e 

Diff: http://reviews.m5sim.org/r/516/diff


Testing
---


Thanks,

Ali

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Re: [m5-dev] Functional Access support in Ruby

[Nilay Vaish]

I was thinking about the behavior of functional accesses. Currently in gdb 
we can change the value of a program variable. Does that mean the 
underlying processor supports functional accesses? If yes, then we should 
already have some knowledge about what is expected from functional 
accesses.


Nilay


On Fri, 25 Feb 2011, Beckmann, Brad wrote:


Yes, that is correct.  The RubyPort::M5Port::recvFunctional() function is where 
we need to add the new support.

Brad



-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
On Behalf Of Nilay Vaish
Sent: Friday, February 25, 2011 12:20 PM
To: m5-dev@m5sim.org
Subject: [m5-dev] Functional Access support in Ruby

Brad,

Here is my understanding of the current state of functional accesses in gem5.
As of now, all functional accesses are forwarded to the PhysicalMemory's
MemoryPort. Instead, we would like to add
recvFunctional() function to M5Port of the RubyPort, and attach this port as
peer instead of the PhysicalMemory.

--
Nilay
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Re: [m5-dev] Review Request: X86: Use regular read requests in the walker instead of read exclusive.

[Steve Reinhardt]

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http://reviews.m5sim.org/r/514/#review905
---

Ship it!


I won't vouch for the surrounding code (I don't get the difference between the 
oldRead, read, and write packets, for starters), but this one specific line 
that's changed looks good to me :-)

- Steve


On 2011-02-26 01:44:53, Gabe Black wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/514/
> ---
> 
> (Updated 2011-02-26 01:44:53)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> X86: Use regular read requests in the walker instead of read exclusive.
> 
> 
> Diffs
> -
> 
>   src/arch/x86/pagetable_walker.cc ac1bd3d1aa54 
> 
> Diff: http://reviews.m5sim.org/r/514/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Gabe
> 
>

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[m5-dev] Review Request: X86: If PCI config space is disabled, pass through to regular IO addresses.

[Gabe Black]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/515/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

X86: If PCI config space is disabled, pass through to regular IO addresses.


Diffs
-

  src/arch/x86/tlb.cc ac1bd3d1aa54 

Diff: http://reviews.m5sim.org/r/515/diff


Testing
---


Thanks,

Gabe

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[m5-dev] Review Request: X86: Use regular read requests in the walker instead of read exclusive.

[Gabe Black]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/514/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

X86: Use regular read requests in the walker instead of read exclusive.


Diffs
-

  src/arch/x86/pagetable_walker.cc ac1bd3d1aa54 

Diff: http://reviews.m5sim.org/r/514/diff


Testing
---


Thanks,

Gabe

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[m5-dev] Cron /z/m5/regression/do-regression quick

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