[m5-dev] Connecting to cache ports

Hi, We are trying to connect a dummy cpu model to caches. So we require to connect the icache and dcache ports of this dummy cpu model to that of M5 caches. Can anybody please tell us what is the best way to achieve this connection ? Arka Rathijit

Re: [m5-dev] Connecting to cache ports

14, 2010 at 10:16 PM, Arkaprava Basu aba...@wisc.edu wrote: Hi, We are trying to connect a dummy cpu model to caches. So we require to connect the icache and dcache ports of this dummy cpu model to that of M5 caches. Can anybody please tell us what is the best way to achieve

Re: [m5-dev] Review Request: Changing how CacheMemory interfaces with SLICC

Hi Nilay, On deadlock issue with MESI_CMP_directory : Yes, this can happen as ruby_tester or Sequencer only reports *possible* deadlocks. With higher number of processors there is more contention (and thus latency) and it can mistakenly report deadlock. I generally look at the protocol

Re: [m5-dev] Fixing MESI CMP directory protocol

threshold do you use? On Tue, 4 Jan 2011, Arkaprava Basu wrote: Hi Nilay, On deadlock issue with MESI_CMP_directory : Yes, this can happen as ruby_tester or Sequencer only reports *possible* deadlocks. With higher number of processors there is more contention (and thus latency) and it can

Re: [m5-dev] (no subject)

I think there are different topology file for different layouts and thus allowing different number of controllers. For example, topology named MeshDirCorners would allow a configuration with --num-cpus 16 --num-l2caches 16 --num-dirs 4 . This essentially places the MCs (a.k.a dirs) at the

Re: [m5-dev] Review Request: ruby: support to stallAndWait the mandatory queue

Hi Nilay, You are mostly correct. I believe this patch contains two things 1. Support in SLICC to allow waiting and stalling on messages in message buffer when the directory is in blocking state for that address (i.e. can not process the message at this point), until some event

Re: [m5-dev] changeset in m5: Ruby: Fixes MESI CMP directory protocol

directory protocol The current implementation of MESI CMP directory protocol is broken. This patch, from Arkaprava Basu, fixes the protocol. diffstat: ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Store Buffer

Hi Brad, I have very little knowledge about the store buffer implementation in libruby and o3 CPU model. But I have following high level question: Is this Store buffer in libruby only for keeping retired (non-speculative) stores ? If yes, then why a particular CPU models matters

Re: [m5-dev] Store Buffer

...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On Behalf Of Arkaprava Basu Sent: Wednesday, February 23, 2011 6:10 PM To: M5 Developer List Subject: Re: [m5-dev] Store Buffer Hi Brad, I have very little knowledge about the store buffer implementation in libruby and o3 CPU model. But I

Re: [m5-dev] Store Buffer

In sum, I think we all agree that Ruby is going to handle *only non-speculative stores*. M5 CPU model(s) handles all of speculative and non-speculative stores that are *yet to be revealed to the memory sub-system*. To make it clearer, as I understand, we now have following: 1. All store

[m5-dev] Ruby random tester failing with MESI_CMP_directory?

Hi, I just updated a clean gem5 repo, compiled MESI_CMP_directory and tried to run ruby random tester but it immediately failed as follows. Can any body reproduce this? Thanks Arka build/X86_SE_MESI_CMP_directory/m5.debug configs/example/ruby_random_test.py -l 10 -n 4 M5 Simulator

Re: [m5-dev] Ruby random tester failing with MESI_CMP_directory?

, Arkaprava Basu wrote: Hi Lisa and Nilay, Thanks for the response. Following is the tip of my repo changeset: 8174:e21f6e70169e tag: tip user:Nilay Vaishni...@cs.wisc.edu date:Tue Mar 22 06:41:54 2011 -0500 summary: Ruby: Remove CacheMsg class from SLICC So