Re: [gem5-dev] Review Request: Enabled instruction fetch pipelining.

I'm working on fixing this patch as it doesn't apply cleanly to the current code. It also fails to pipeline fetch for the corner case when the pipeline uses all the fetch bandwidth and you have reached the end of a cache block. It should start the fetch for the next cycle but won't. Probably not

[gem5-dev] changeset in m5: O3: Fix issue with interrupts/faults occuring i...

changeset 13ac7b9939ef in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=13ac7b9939ef description: O3: Fix issue with interrupts/faults occuring in the middle of a macro-op This patch fixes two problems with the O3 cpu model. The first is an issue with

[gem5-dev] changeset in m5: O3: Fix issue w/wbOutstading being decremented ...

changeset 6173b87e7652 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=6173b87e7652 description: O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache. If a split load fails on a blocked cache wbOutstanding can be decremented

[m5-dev] changeset in m5: O3: Fix an issue with a load branch instructi...

changeset 3c1296738e34 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3c1296738e34 description: O3: Fix an issue with a load branch instruction and mem dep squashing Instructions that load an address and are control instructions can execute down the

[m5-dev] TBH/TBB ARM instructions should potentially be split into 2 micro-ops?

I've run into a buggy interaction for the ARM ISA between a TBH (or TBB) instruction and a dependent memory operation (that gets squashed) in the O3 model leading to erroneous behavior when diffed against the Atomic model. The TBH instruction is a table-based branch that has to index into memory

[m5-dev] changeset in m5: Fix bug in MDT BITMAP to allow more than 2GB of...

changeset 6b05deee0ca3 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=6b05deee0ca3 description: Fix bug in MDT BITMAP to allow more than 2GB of memory. Signed-off by Ali Saidi sa...@eecs.umich.edu diffstat: system/alpha/console/console.c | 19

[m5-dev] Memory corruption in m5 dev repository when using --trace-flags=ExecEnable

I stumbled upon what appears to be a memory corruption bug in the current M5 repository. If on the command line I enter: % ./build/ALPHA_FS/m5.opt -trace-flags=ExecEnable -trace-start=14000 fs.py -b benchmark -t -n cpus more parameters. The simulator will error with a segmentation fault

Re: [m5-dev] syscall tracer

What exactly are you trying to do with making a syscall tracer Gabe? I thought your original problem was a happening with GLIBC doing some bizarre pointer encryption/decryption and it was getting it wrong leading to a segmentation fault? To help find that seg fault, I'd suggest going into the

Re: [m5-dev] SLOOOOOOOOOOW IDE controller

I'm pretty sure in the alpha linux code, that they've added the quiesce() pseudo-inst to just skip past any busy wait loops. They've done this for the cpu_idle() loop as well in Alpha. -Original Message- From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On Behalf Of Gabe

RE: [m5-dev] tracing data for stores in simple CPU

I believe if you turn on ExecResult in the trace-flags option, it will show data, at least it does for me. -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Gabe Black Sent: Friday, May 02, 2008 5:32 AM To: M5 Developer List Subject: [m5-dev] tracing data