scons: *** [build/HSAIL_X86/gpu-compute/gpu_dyn_inst.do] Error 1
scons: *** [build/HSAIL_X86/gpu-compute/gpu_static_inst.do] Error 1
scons: *** [build/HSAIL_X86/marshal] Error 1
scons: *** [build/HSAIL_X86/cpu/testers/memtest/lib.do.partial] Error 1
scons: ***
Hi all,
The website has been moved over! Please let me know if you see any major
problems. If you find content errors, etc. you can either file a bug report
on https://gem5.atlassian.net/browse/GEM5 or create a changeset on gerrit:
Jason Lowe-Power has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24503 )
Change subject: misc: Updated old gem5 website URLs with new gem5 website
URLs
..
misc: Updated old gem5 website
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/24903 )
Change subject: sim,cpu: Move the call to initCPU into System.
..
sim,cpu: Move the call to initCPU into System.
Hi,
I use a simple hack in SLICC's grammar to allow referring to enum values
inside SLICC (.sm) files.
Add the following inside `src/mem/slicc/parser.py`:
def p_literal__enumvalue(self, p):
"literal : IDENT DOUBLE_COLON IDENT"
p[0] = ast.LiteralExprAST(self, p[1] + p[2] + p[3], p[1])
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/24905 )
Change subject: arch,sim: Merge initCPU into the ISA System classes.
..
arch,sim: Merge initCPU into the ISA
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/24904 )
Change subject: arch,sim: Merge initCPU and startupCPU.
..
arch,sim: Merge initCPU and startupCPU.
These two
*
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing:
FAILED!
*
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual:
FAILED!
*
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual:
FAILED!
*
On 1/29/20 8:30 AM, Ciro Santilli wrote:
> I would also recommend opening a bug report for this at:
> https://gem5.atlassian.net/projects/GEM5/issues with the arch-arm
> component to make it easier to keep track of.
Sure, I can do that.
Nils
___
On 1/29/20 3:26 AM, Gabe Black wrote:
> It looks to me like this is because the MicroUopSetPCCPSR microop
> (uopSet_uop, the one actually setting the CPSR) is not marked as
> IsSerializeAfter. The macroop it's a part of is, but the flags on macroops,
> other than the one that says it's a macroop,
scons: *** [build/HSAIL_X86/gpu-compute/gpu_dyn_inst.do] Error 1
scons: *** [build/HSAIL_X86/gpu-compute/gpu_static_inst.do] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/branch.do] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/gen_exec.do] Error 1
scons: ***
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