[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Move the inUserMode function to the ISA object.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39323 )
Change subject: arch,cpu: Move the inUserMode function to the ISA object.
..
arch,cpu: Move the inUserMode function to the ISA object.
This function is used when tracing execution with --debug-flags=Exec.
The data used by the function (now method) is stored in the ISA object,
and so that's a logical place to move it.
Change-Id: I624f9365124679343e988cabfb4e1929225b439a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39323
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/iris/isa.hh
M src/arch/arm/isa.hh
M src/arch/arm/utility.hh
M src/arch/generic/isa.hh
M src/arch/mips/isa.hh
M src/arch/mips/utility.hh
M src/arch/power/isa.hh
M src/arch/power/utility.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/utility.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/utility.hh
M src/arch/x86/isa.hh
M src/arch/x86/utility.hh
M src/cpu/exetrace.cc
15 files changed, 66 insertions(+), 65 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/iris/isa.hh
b/src/arch/arm/fastmodel/iris/isa.hh
index d9646df..a7ae7b5 100644
--- a/src/arch/arm/fastmodel/iris/isa.hh
+++ b/src/arch/arm/fastmodel/iris/isa.hh
@@ -28,6 +28,7 @@
#ifndef __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
#define __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
+#include "arch/arm/utility.hh"
#include "arch/generic/isa.hh"
namespace Iris
@@ -39,6 +40,13 @@
ISA(const Params ) : BaseISA(p) {}
void serialize(CheckpointOut ) const;
+
+bool
+inUserMode() const override
+{
+CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
+return ::inUserMode(cpsr);
+}
};
} // namespace Iris
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index dd4dc6e..7888229 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -48,6 +48,7 @@
#include "arch/arm/system.hh"
#include "arch/arm/tlb.hh"
#include "arch/arm/types.hh"
+#include "arch/arm/utility.hh"
#include "arch/generic/isa.hh"
#include "arch/generic/traits.hh"
#include "debug/Checkpoint.hh"
@@ -891,6 +892,13 @@
{
return readMiscRegNoEffect(MISCREG_CONTEXTIDR);
}
+
+bool
+inUserMode() const override
+{
+CPSR cpsr = miscRegs[MISCREG_CPSR];
+return ArmISA::inUserMode(cpsr);
+}
};
}
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index e255b1c..bd043df 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -111,23 +111,11 @@
}
static inline bool
-inUserMode(ThreadContext *tc)
-{
-return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
-}
-
-static inline bool
inPrivilegedMode(CPSR cpsr)
{
return !inUserMode(cpsr);
}
-static inline bool
-inPrivilegedMode(ThreadContext *tc)
-{
-return !inUserMode(tc);
-}
-
bool isSecure(ThreadContext *tc);
bool inAArch64(ThreadContext *tc);
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 7d5daa8..4c717c7 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -56,6 +56,7 @@
virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
virtual uint64_t getExecutingAsid() const { return 0; }
+virtual bool inUserMode() const = 0;
};
#endif // __ARCH_GENERIC_ISA_HH__
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 1e94a98..cc05781 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -140,6 +140,26 @@
// dummy
int flattenCCIndex(int reg) const { return reg; }
int flattenMiscIndex(int reg) const { return reg; }
+
+bool
+inUserMode() const override
+{
+RegVal Stat = readMiscRegNoEffect(MISCREG_STATUS);
+RegVal Dbg = readMiscRegNoEffect(MISCREG_DEBUG);
+
+if (// EXL, ERL or CU0 set, CP0 accessible
+(Stat & 0x1006) == 0 &&
+// DM bit set, CP0 accessible
+(Dbg & 0x4000) == 0 &&
+// KSU = 0, kernel mode is base mode
+(Stat & 0x0018) != 0) {
+// Unable to use Status_CU0, etc directly,
+// using bitfields & masks.
+return true;
+} else {
+return false;
+}
+}
};
}
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 0cb9349..6fb211d 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -65,22 +65,6 @@
bool isQnan(void *val_ptr, int size);
bool isSnan(void *val_ptr, int size);
-static inline bool
-inUserMode(ThreadContext *tc)
-{
-RegVal Stat = tc->readMiscReg(MISCREG_STATUS);
-RegVal Dbg = tc->readMiscReg(MISCREG_DEBUG);
-
-if ((Stat & 0x1006) == 0 && // EXL, ERL or CU0 set,
[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Move the inUserMode function to the ISA object.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39323 )
Change subject: arch,cpu: Move the inUserMode function to the ISA object.
..
arch,cpu: Move the inUserMode function to the ISA object.
This function is used when tracing execution with --debug-flags=Exec.
The data used by the function (now method) is stored in the ISA object,
and so that's a logical place to move it.
Change-Id: I624f9365124679343e988cabfb4e1929225b439a
---
M src/arch/arm/fastmodel/iris/isa.hh
M src/arch/arm/isa.hh
M src/arch/arm/utility.hh
M src/arch/generic/isa.hh
M src/arch/mips/isa.hh
M src/arch/mips/utility.hh
M src/arch/power/isa.hh
M src/arch/power/utility.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/utility.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/utility.hh
M src/arch/x86/isa.hh
M src/arch/x86/utility.hh
M src/cpu/exetrace.cc
15 files changed, 66 insertions(+), 65 deletions(-)
diff --git a/src/arch/arm/fastmodel/iris/isa.hh
b/src/arch/arm/fastmodel/iris/isa.hh
index d9646df..a7ae7b5 100644
--- a/src/arch/arm/fastmodel/iris/isa.hh
+++ b/src/arch/arm/fastmodel/iris/isa.hh
@@ -28,6 +28,7 @@
#ifndef __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
#define __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
+#include "arch/arm/utility.hh"
#include "arch/generic/isa.hh"
namespace Iris
@@ -39,6 +40,13 @@
ISA(const Params ) : BaseISA(p) {}
void serialize(CheckpointOut ) const;
+
+bool
+inUserMode() const override
+{
+CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
+return ::inUserMode(cpsr);
+}
};
} // namespace Iris
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 97b41cc..d350378 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -48,6 +48,7 @@
#include "arch/arm/system.hh"
#include "arch/arm/tlb.hh"
#include "arch/arm/types.hh"
+#include "arch/arm/utility.hh"
#include "arch/generic/isa.hh"
#include "arch/generic/traits.hh"
#include "debug/Checkpoint.hh"
@@ -892,6 +893,13 @@
{
return readMiscRegNoEffect(MISCREG_CONTEXTIDR);
}
+
+bool
+inUserMode() const override
+{
+CPSR cpsr = miscRegs[MISCREG_CPSR];
+return ArmISA::inUserMode(cpsr);
+}
};
}
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index e255b1c..bd043df 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -111,23 +111,11 @@
}
static inline bool
-inUserMode(ThreadContext *tc)
-{
-return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
-}
-
-static inline bool
inPrivilegedMode(CPSR cpsr)
{
return !inUserMode(cpsr);
}
-static inline bool
-inPrivilegedMode(ThreadContext *tc)
-{
-return !inUserMode(tc);
-}
-
bool isSecure(ThreadContext *tc);
bool inAArch64(ThreadContext *tc);
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 9ea2d9f..12c58ad 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -59,6 +59,7 @@
virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
virtual uint64_t getExecutingAsid() const { return 0; }
+virtual bool inUserMode() const = 0;
};
#endif // __ARCH_GENERIC_ISA_HH__
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 1b81046..6242c62 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -142,6 +142,26 @@
// dummy
int flattenCCIndex(int reg) const { return reg; }
int flattenMiscIndex(int reg) const { return reg; }
+
+bool
+inUserMode() const override
+{
+RegVal Stat = readMiscRegNoEffect(MISCREG_STATUS);
+RegVal Dbg = readMiscRegNoEffect(MISCREG_DEBUG);
+
+if (// EXL, ERL or CU0 set, CP0 accessible
+(Stat & 0x1006) == 0 &&
+// DM bit set, CP0 accessible
+(Dbg & 0x4000) == 0 &&
+// KSU = 0, kernel mode is base mode
+(Stat & 0x0018) != 0) {
+// Unable to use Status_CU0, etc directly,
+// using bitfields & masks.
+return true;
+} else {
+return false;
+}
+}
};
}
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 0cb9349..6fb211d 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -65,22 +65,6 @@
bool isQnan(void *val_ptr, int size);
bool isSnan(void *val_ptr, int size);
-static inline bool
-inUserMode(ThreadContext *tc)
-{
-RegVal Stat = tc->readMiscReg(MISCREG_STATUS);
-RegVal Dbg = tc->readMiscReg(MISCREG_DEBUG);
-
-if ((Stat & 0x1006) == 0 && // EXL, ERL or CU0 set, CP0 accessible
-(Dbg & 0x4000) == 0 && // DM bit set, CP0 accessible
-(Stat & 0x0018) != 0) { // KSU = 0, kernel mode is base mode
-// Unable to use Status_CU0, etc directly, using bitfields & masks
-
