Robert Scheffel has uploaded this change for review. (
https://gem5-review.googlesource.com/9822
Change subject: arch-riscv: add support for xret instructions
......................................................................
arch-riscv: add support for xret instructions
The instructions URET, SRET and MRET have been implemented according to
the specification. The current privilege level is set to the one stored
in the xpp field of the mstatus register. The interrupt enable bits are
restored from the previous interrupt enable field and the xpie field is
set to 1, indicating that interrupts were allowed globally.
The xpp field is set to U and finally the pc stored in the xepc register
is restored.
Change-Id: Ifbc4e498b94a9ad21a1f615da01b265e1b56fb1a
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 40 insertions(+), 3 deletions(-)
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index e3992d7..fd5bafd 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1692,9 +1692,46 @@
0x1: ebreak({{
fault = make_shared<BreakpointFault>();
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
- 0x100: eret({{
- fault = make_shared<UnimplementedFault>("eret");
- }}, No_OpClass);
+ 0x2: uret({{
+ MSTATUS status = xc->readMiscReg(MISCREG_MSTATUS);
+ // xie -> xpie
+ status.uie = status.upie;
+ // xpie -> 1
+ status.upie = 1;
+ xc->setMiscReg(MISCREG_MSTATUS, status);
+ // restore process counter
+ PCState pc = xc->readMiscReg(MISCREG_UEPC);
+ xc->pcState(pc)
+ }}, IsReturn);
+ 0x102: sret({{
+ MSTATUS status = xc->readMiscReg(MISCREG_MSTATUS);
+ // change priv lvl to xpp
+ xc->setMiscReg(MISCREG_PRV, status.spp);
+ // xie -> xpie
+ status.sie = status.spie;
+ // xpie -> 1
+ status.spie = 1;
+ // xpp -> U (0)
+ status.spp = 0;
+ xc->setMiscReg(MISCREG_MSTATUS, status);
+ // restore process counter
+ PCState pc = xc->readMiscReg(MISCREG_SEPC);
+ xc->pcState(pc)
+ }}, IsReturn);
+ 0x302: mret({{
+ MSTATUS status = xc->readMiscReg(MISCREG_MSTATUS);
+ // change priv lvl to xpp
+ xc->setMiscReg(MISCREG_PRV, status.mpp);
+ // xie -> xpie
+ status.mie = status.mpie;
+ // xpie -> 1
+ status.mpie = 1;
+ // xpp -> U (0)
+ status.mpp = 0;
+ xc->setMiscReg(MISCREG_MSTATUS, status);
+ // restore process counter
+ NPC = xc->readMiscReg(MISCREG_MEPC);
+ }}, IsReturn);
}
}
format CSROp {
--
To view, visit https://gem5-review.googlesource.com/9822
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ifbc4e498b94a9ad21a1f615da01b265e1b56fb1a
Gerrit-Change-Number: 9822
Gerrit-PatchSet: 1
Gerrit-Owner: Robert Scheffel <robert.scheff...@tu-dresden.de>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
