[gem5-dev] Change in public/gem5[master]: arch-riscv: Move compressed ops out of ISA

2017-12-06 Thread Alec Roelke (Gerrit) 
Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6026 )


Change subject: arch-riscv: Move compressed ops out of ISA
..

arch-riscv: Move compressed ops out of ISA

This patch moves static portions of the compressed instruction
definitions out of the ISA generated code.

Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
Reviewed-on: https://gem5-review.googlesource.com/6026
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Alec Roelke 
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/compressed.cc
A src/arch/riscv/insts/compressed.hh
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/includes.isa
5 files changed, 111 insertions(+), 29 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, but someone else must approve
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/insts/SConscript  
b/src/arch/riscv/insts/SConscript

index 439219c..fcfb627 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -31,6 +31,7 @@

 if env['TARGET_ISA'] == 'riscv':
 Source('amo.cc')
+Source('compressed.cc')
 Source('mem.cc')
 Source('standard.cc')
 Source('static_inst.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/compressed.cc  
b/src/arch/riscv/insts/compressed.cc

new file mode 100644
index 000..ff9eccc
--- /dev/null
+++ b/src/arch/riscv/insts/compressed.cc
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2015 RISC-V Foundation
+ * Copyright (c) 2017 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+
+#include "arch/riscv/insts/compressed.hh"
+
+#include 
+#include 
+
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+std::string
+CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+registerName(_srcRegIdx[0]);
+return ss.str();
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/compressed.hh  
b/src/arch/riscv/insts/compressed.hh

new file mode 100644
index 000..021a4b4
--- /dev/null
+++ b/src/arch/riscv/insts/compressed.hh
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2015 RISC-V Foundation
+ * Copyright (c) 2017 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND

[gem5-dev] Change in public/gem5[master]: arch-riscv: Move compressed ops out of ISA

2017-11-28 Thread Alec Roelke (Gerrit) 

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/6026

to look at the new patch set (#4).

Change subject: arch-riscv: Move compressed ops out of ISA
..

arch-riscv: Move compressed ops out of ISA

This patch moves static portions of the compressed instruction
definitions out of the ISA generated code.

Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/compressed.cc
A src/arch/riscv/insts/compressed.hh
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/includes.isa
5 files changed, 111 insertions(+), 29 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
Gerrit-Change-Number: 6026
Gerrit-PatchSet: 4
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move compressed ops out of ISA

2017-11-28 Thread Alec Roelke (Gerrit) 

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/6026

to look at the new patch set (#3).

Change subject: arch-riscv: Move compressed ops out of ISA
..

arch-riscv: Move compressed ops out of ISA

This patch moves static portions of the compressed instruction
definitions out of the ISA generated code.

Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/compressed.cc
A src/arch/riscv/insts/compressed.hh
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/includes.isa
5 files changed, 115 insertions(+), 29 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
Gerrit-Change-Number: 6026
Gerrit-PatchSet: 3
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move compressed ops out of ISA

2017-11-27 Thread Alec Roelke (Gerrit) 
Alec Roelke has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/6026 )


Change subject: arch-riscv: Move compressed ops out of ISA
..

arch-riscv: Move compressed ops out of ISA

This patch moves static portions of the compressed instruction
definitions out of the ISA generated code.

Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/compressed.cc
A src/arch/riscv/insts/compressed.hh
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/includes.isa
5 files changed, 49 insertions(+), 29 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
Gerrit-Change-Number: 6026
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke 
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move compressed ops out of ISA

2017-11-21 Thread Alec Roelke (Gerrit) 
Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/6026



Change subject: arch-riscv: Move compressed ops out of ISA
..

arch-riscv: Move compressed ops out of ISA

This patch moves static portions of the compressed instruction
definitions out of the ISA generated code.

Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/compressed.cc
A src/arch/riscv/insts/compressed.hh
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/includes.isa
5 files changed, 47 insertions(+), 29 deletions(-)



diff --git a/src/arch/riscv/insts/SConscript  
b/src/arch/riscv/insts/SConscript

index d058f85..39205a2 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -2,6 +2,7 @@

 if env['TARGET_ISA'] == 'riscv':
 Source('amo.cc')
+Source('compressed.cc')
 Source('mem.cc')
 Source('standard.cc')
 Source('static_inst.cc')
diff --git a/src/arch/riscv/insts/compressed.cc  
b/src/arch/riscv/insts/compressed.cc

new file mode 100644
index 000..8a8481e
--- /dev/null
+++ b/src/arch/riscv/insts/compressed.cc
@@ -0,0 +1,21 @@
+#include "arch/riscv/insts/compressed.hh"
+
+#include 
+#include 
+
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+std::string
+CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+registerName(_srcRegIdx[0]);
+return ss.str();
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/compressed.hh  
b/src/arch/riscv/insts/compressed.hh

new file mode 100644
index 000..7d7e693
--- /dev/null
+++ b/src/arch/riscv/insts/compressed.hh
@@ -0,0 +1,24 @@
+#ifndef __ARCH_RISCV_INSTS_COMPRESSED_HH__
+#define __ARCH_RISCV_INSTS_COMPRESSED_HH__
+
+#include 
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Base class for compressed operations that work only on registers
+ */
+class CompRegOp : public RiscvStaticInst
+{
+  protected:
+using RiscvStaticInst::RiscvStaticInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+}
+
+#endif // __ARCH_RISCV_INSTS_COMPRESSED_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/compressed.isa  
b/src/arch/riscv/isa/formats/compressed.isa

index 1fd2319..91b6672 100644
--- a/src/arch/riscv/isa/formats/compressed.isa
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -28,35 +28,6 @@
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 //
 // Authors: Alec Roelke
-
-output header {{
-/**
- * Base class for compressed operations that work only on registers
- */
-class CompRegOp : public RiscvStaticInst
-{
-  protected:
-/// Constructor
-CompRegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
-: RiscvStaticInst(mnem, _machInst, __opClass)
-{}
-
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-}};
-
-output decoder {{
-std::string
-CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab)  
const

-{
-std::stringstream ss;
-ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
-registerName(_srcRegIdx[0]);
-return ss.str();
-}
-}};
-
 def format CROp(code, *opt_flags) {{
 iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags)
 header_output = BasicDeclare.subst(iop)
diff --git a/src/arch/riscv/isa/includes.isa  
b/src/arch/riscv/isa/includes.isa

index f4662da..9f3d99f 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -43,6 +43,7 @@
 #include 

 #include "arch/riscv/insts/amo.hh"
+#include "arch/riscv/insts/compressed.hh"
 #include "arch/riscv/insts/mem.hh"
 #include "arch/riscv/insts/standard.hh"
 #include "arch/riscv/insts/static_inst.hh"

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Gerrit-Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
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Gerrit-Owner: Alec Roelke 
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