changeset fe601d7bd955 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=fe601d7bd955 description: cpu: Fix the O3 CPU Drain
The drain did not wait until stages were ready again. Therefore, as a result of messages in the TimeBuffer being drain, the state after the drain was not consistent and asserts fired in some places when the draining happened after a stage got blocked, but before the notification arrived to the previous stages. Change-Id: Ib50b3b40b7f745b62c1eba2931dec76860824c71 Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com> diffstat: src/cpu/o3/decode_impl.hh | 3 ++- src/cpu/o3/fetch_impl.hh | 4 +++- src/cpu/o3/iew_impl.hh | 1 + src/cpu/o3/rename_impl.hh | 3 ++- 4 files changed, 8 insertions(+), 3 deletions(-) diffs (52 lines): diff -r f54a527153f4 -r fe601d7bd955 src/cpu/o3/decode_impl.hh --- a/src/cpu/o3/decode_impl.hh Thu Sep 22 10:49:09 2016 +0100 +++ b/src/cpu/o3/decode_impl.hh Thu Sep 22 10:49:10 2016 +0100 @@ -209,7 +209,8 @@ DefaultDecode<Impl>::isDrained() const { for (ThreadID tid = 0; tid < numThreads; ++tid) { - if (!insts[tid].empty() || !skidBuffer[tid].empty()) + if (!insts[tid].empty() || !skidBuffer[tid].empty() || + (decodeStatus[tid] != Running && decodeStatus[tid] != Idle)) return false; } return true; diff -r f54a527153f4 -r fe601d7bd955 src/cpu/o3/fetch_impl.hh --- a/src/cpu/o3/fetch_impl.hh Thu Sep 22 10:49:09 2016 +0100 +++ b/src/cpu/o3/fetch_impl.hh Thu Sep 22 10:49:10 2016 +0100 @@ -424,8 +424,10 @@ void DefaultFetch<Impl>::drainResume() { - for (ThreadID i = 0; i < numThreads; ++i) + for (ThreadID i = 0; i < numThreads; ++i) { + stalls[i].decode = false; stalls[i].drain = false; + } } template <class Impl> diff -r f54a527153f4 -r fe601d7bd955 src/cpu/o3/iew_impl.hh --- a/src/cpu/o3/iew_impl.hh Thu Sep 22 10:49:09 2016 +0100 +++ b/src/cpu/o3/iew_impl.hh Thu Sep 22 10:49:10 2016 +0100 @@ -391,6 +391,7 @@ DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); drained = false; } + drained = drained && dispatchStatus[tid] == Running; } // Also check the FU pool as instructions are "stored" in FU diff -r f54a527153f4 -r fe601d7bd955 src/cpu/o3/rename_impl.hh --- a/src/cpu/o3/rename_impl.hh Thu Sep 22 10:49:09 2016 +0100 +++ b/src/cpu/o3/rename_impl.hh Thu Sep 22 10:49:10 2016 +0100 @@ -304,7 +304,8 @@ if (instsInProgress[tid] != 0 || !historyBuffer[tid].empty() || !skidBuffer[tid].empty() || - !insts[tid].empty()) + !insts[tid].empty() || + (renameStatus[tid] != Idle && renameStatus[tid] != Running)) return false; } return true; _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev