Re: [gem5-dev] Review Request 2462: mem: Page Table map api modification
On Nov. 18, 2014, 4:30 p.m., Andreas Hansson wrote: src/mem/page_table.hh, line 95 http://reviews.gem5.org/r/2462/diff/1/?file=42140#file42140line95 I'd suggest to specify the storage type (uint32_t) Thought it is the only enum that will have an explicit storage type. - Alexandru --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2462/#review5474 --- On Oct. 6, 2014, 6:58 p.m., Alexandru Dutu wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2462/ --- (Updated Oct. 6, 2014, 6:58 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 10429:e0f8a026df2c --- mem: Page Table map api modification This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes. Diffs - src/arch/alpha/pagetable.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/arch/arm/pagetable.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/arch/mips/pagetable.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/arch/power/tlb.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/arch/sparc/pagetable.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/arch/x86/pagetable.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/arch/x86/pagetable.cc 148b96b7bc77190686f532d3b8f9f30cf911b36a src/mem/multi_level_page_table.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/mem/multi_level_page_table_impl.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/mem/page_table.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/mem/page_table.cc 148b96b7bc77190686f532d3b8f9f30cf911b36a src/sim/Process.py 148b96b7bc77190686f532d3b8f9f30cf911b36a src/sim/process.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/sim/process.cc 148b96b7bc77190686f532d3b8f9f30cf911b36a Diff: http://reviews.gem5.org/r/2462/diff/ Testing --- Quick regressions testing done. Thanks, Alexandru Dutu ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2462: mem: Page Table map api modification
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2462/ --- (Updated Nov. 20, 2014, 6:27 a.m.) Review request for Default. Changes --- Addressed raised issues. Repository: gem5 Description (updated) --- Changeset 10553:d4148bafebad --- mem: Page Table map api modification This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes. Diffs (updated) - src/arch/alpha/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/arm/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/mips/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/power/tlb.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/sparc/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/x86/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/x86/pagetable.cc 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/mem/multi_level_page_table.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/mem/multi_level_page_table_impl.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/mem/page_table.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/mem/page_table.cc 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/sim/Process.py 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/sim/process.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/sim/process.cc 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 Diff: http://reviews.gem5.org/r/2462/diff/ Testing --- Quick regressions testing done. Thanks, Alexandru Dutu ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2462: mem: Page Table map api modification
On Nov. 18, 2014, 4:30 p.m., Andreas Hansson wrote: src/mem/page_table.hh, line 95 http://reviews.gem5.org/r/2462/diff/1/?file=42140#file42140line95 I'd suggest to specify the storage type (uint32_t) Alexandru Dutu wrote: Thought it is the only enum that will have an explicit storage type. We have to start somewhere :-) - Andreas --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2462/#review5474 --- On Nov. 20, 2014, 6:27 a.m., Alexandru Dutu wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2462/ --- (Updated Nov. 20, 2014, 6:27 a.m.) Review request for Default. Repository: gem5 Description --- Changeset 10553:d4148bafebad --- mem: Page Table map api modification This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes. Diffs - src/arch/alpha/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/arm/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/mips/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/power/tlb.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/sparc/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/x86/pagetable.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/arch/x86/pagetable.cc 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/mem/multi_level_page_table.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/mem/multi_level_page_table_impl.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/mem/page_table.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/mem/page_table.cc 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/sim/Process.py 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/sim/process.hh 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 src/sim/process.cc 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 Diff: http://reviews.gem5.org/r/2462/diff/ Testing --- Quick regressions testing done. Thanks, Alexandru Dutu ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2462: mem: Page Table map api modification
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2462/#review5474 --- src/arch/x86/pagetable.hh http://reviews.gem5.org/r/2462/#comment4922 i guess these should be const src/mem/page_table.hh http://reviews.gem5.org/r/2462/#comment4923 I'd suggest to specify the storage type (uint32_t) src/sim/process.hh http://reviews.gem5.org/r/2462/#comment4924 please update the doxygen comments Some minor things. Looks ok for the rest. - Andreas Hansson On Oct. 6, 2014, 6:58 p.m., Alexandru Dutu wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2462/ --- (Updated Oct. 6, 2014, 6:58 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 10429:e0f8a026df2c --- mem: Page Table map api modification This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes. Diffs - src/arch/alpha/pagetable.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/arch/arm/pagetable.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/arch/mips/pagetable.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/arch/power/tlb.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/arch/sparc/pagetable.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/arch/x86/pagetable.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/arch/x86/pagetable.cc 148b96b7bc77190686f532d3b8f9f30cf911b36a src/mem/multi_level_page_table.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/mem/multi_level_page_table_impl.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/mem/page_table.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/mem/page_table.cc 148b96b7bc77190686f532d3b8f9f30cf911b36a src/sim/Process.py 148b96b7bc77190686f532d3b8f9f30cf911b36a src/sim/process.hh 148b96b7bc77190686f532d3b8f9f30cf911b36a src/sim/process.cc 148b96b7bc77190686f532d3b8f9f30cf911b36a Diff: http://reviews.gem5.org/r/2462/diff/ Testing --- Quick regressions testing done. Thanks, Alexandru Dutu ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
