Re: [gem5-users] memory access time

Hi Marziye, I suggest you have a look at the description of the stats. If that is not explanatory enough, there is always the source code… Andreas From: marziye esmslampanah mesmslampa...@yahoo.commailto:mesmslampa...@yahoo.com Reply-To: marziye esmslampanah

Re: [gem5-users] Adding New Class to GEM5/src

You should create your own class in C++ and instantiate it in Python. You also have to add SimObject('YourInstance.py') and Source('class.cpp') to your SConscript - Mensaje original - De: Kumail Ahmed kumai...@gmail.com Para: gem5 users mailing list gem5-users@gem5.org Enviados:

[gem5-users] simulation speed (FreeBSD)

Hello, I experience a speed problem running FreeBSD/ARMv8 in FS mode: for some reason gem5 takes ~1 hour to boot FreeBSD multiuser, while Linux on a same host PC (using same gem5.opt binary) takes about 7-10 minutes. I tested FreeBSD boot with rootfs on ATA (PCI bus) disk device as well with

Re: [gem5-users] Adding New Class to GEM5/src

Hi, Thanks for your reply. Can you tell me an example of Python instantiations inside GEM5? On 14 Apr 2015 10:10 am, Marcos Horro Varela marcos.ho...@udc.es wrote: You should create your own class in C++ and instantiate it in Python. You also have to add SimObject('YourInstance.py') and

Re: [gem5-users] ruby_network_test Memory address range for system.physmem is overlapping

Which Cache coherence protocol did you use in the first case while building? Have you tried with Network_test ? Did you change any other attributes like cache line size or ruby block size? On 7 March 2015 at 04:49, Tanvir Mustofa via gem5-users gem5-users@gem5.org wrote: Hello everyone, I

Re: [gem5-users] Adding New Class to GEM5/src

You have an example in gem5/src/mem/cache/BaseCache.py You should also understand first how gem5 creates and instantiates objects internally. It will help you to develop your classes. - Mensaje original - De: Kumail Ahmed kumai...@gmail.com Para: gem5 users mailing list

[gem5-users] DVFS with self defined policies on gem5

Hello all, I am working on a project where I have to use DVFS to change the frequency of cores based on my evaluation of some counters that I inserted in the gem5 o3 cpu src code. I followed the guidelines given on http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS . But with these steps,

Re: [gem5-users] Simulating Shared Cache among few processors

If you are executing your code in SE mode, such a configuration can be created with adding new CoherentXbar in the se.py file. You can than connect new caches to these bars through your own logic. PS: I think in future, there should be a graphical tool for making a CPU tool in GEM5. On 10 Apr

[gem5-users] switch_cpu\'stats is missing in stats.txt

Hi, Xiangyang I have the same problem with you. It seems that we can only use the data of cpu’s stats, not switch_cpus’. And, I wonder whether you have solved this problem and how you deal with this finally? Regards Kai ___ gem5-users mailing list

[gem5-users] Mem Request Assertion fail [VALID_VADDR]

Hi , I'm trying to access the Virtual Address of the packets to *handleFill()* and *access()* methods using *pkt-req-getVaddr()* Seems that some of the packets don't have Virtual Addresses.. If this is the case, then how can I access the Virtual address of a particular data being written into