Re: [gem5-users] DVFS with self defined policies on gem5

Thanks for the solution AndreasI will try that. On Apr 15, 2015 6:29 PM, Andreas Hansson andreas.hans...@arm.com wrote: Hi all, The nice and clean option would be to use add an architecturally visible performance counter read from the DVFS governor (in software). The hackish option

Re: [gem5-users] DVFS with self defined policies on gem5

Hi Andreas, The nice and clean option would be to use add an architecturally visible performance counter read from the DVFS governor (in software). Is there any example of any such counter which I can look at to get an idea how this will be done?? On Apr 16, 2015 10:43 AM, Nimish Girdhar

[gem5-users] armdroid kernel panic

Hello, I have been following the building kernel turotial in http://www.gem5.org/BBench-gem5. I intend to apply m5struct.diff patch to it so I can integrate gem5 with streamline. However, even without patching, the freshly compiled kernel using make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi-

Re: [gem5-users] simulation speed (FreeBSD)

This controls timer frequency in Linux ? I've played with generic timer frequency in freebsd decreasing the frequency from 100MHz (default) to 10MHz - it gives some speed up but not too much. Ruslan On Tue, Apr 14, 2015 at 11:00:50PM -0700, Ali Saidi wrote: For linux we pass in a jiffies= on

Re: [gem5-users] simulation speed (FreeBSD)

Not just about controlling the frequency, but *avoiding* the costly calibration loop involved. Some other tests that come to mind are timeouts waiting for devices (prune the compiled modules / support for devices) and other calibration loops (RAID throughput, encryption throughput,...) --

Re: [gem5-users] DVFS with self defined policies on gem5

Hi Nimish, as Andreas pointed out, there are two possible ways for this. If you want to simulate a smart *software* governor, then you can access the PMU (see code in src/arch/arm/{pmu.cc,pmu.hh,ArmPMU.py}). The interface to that should be through the normal PMU functions, and the counters

Re: [gem5-users] bytesWritten (8 * number of 64-bit stores to unique addresses)

Thanks, Andreas. This makes sense. On Wed, Apr 15, 2015 at 5:26 PM, Andreas Hansson andreas.hans...@arm.com wrote: Hi Patrick, When it comes to the stores you are looking at a rather small number of operations, and my guess is that they are still in the DRAM write queues. These queues are

Re: [gem5-users] [gem5-dev] ARM DVFS : Core dead time and Voltage change time

Hi Lokesh, gem5 does indeed currently only capture the delay in the transition, and still “clocks” the components that are affected. A more detailed model of the PMIC and voltage regulators, battery etc can definitely be added, the transitions refined etc. The question is how much it matters, and

[gem5-users] Android and Machine Type

Hi Is Android supported only with RealView_PBX machine type. The discussion at https://www.mail-archive.com/gem5-users@gem5.org/msg11185.html suggests so. If yes then how to use 2GB configuration for Android. Any help will he highly appreciated. -- Have a great day! Thanks and Warm Regards

Re: [gem5-users] ARM - Cache Coherence Protocol

Hello Andreas Thanks for prompt reply. Can you please let me know what you mean by You should only ever have to do this in the L1 (or the LSQ) ? My implementation is for L2 cache line i.e. when cache line request comes from L1 cache corresponding to Master Id of 12. I know the implementation is

[gem5-users] ARM DVFS : Core dead time and Voltage change time

Hello everyone In DVFS in real systems, there are 2 parameters that come into picture during voltage-frequency transition. 1. Core dead time during which core does not execute anything and is the time taken to actually change the frequency. 2. voltage change time during which the core is