Hi Nimish,
as Andreas pointed out, there are two possible ways for this.
If you want to simulate a smart *software* governor, then you can access
the PMU (see code in src/arch/arm/{pmu.cc,pmu.hh,ArmPMU.py}). The
interface to that should be through the normal PMU functions, and the
counters therefore should be available through the perf toolkit, PAPI,
and the respective ARM coprocessor interface (gory details here:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Bcgddibf.html#
)
Directly evaluating the stats inside gem5 and then changing the
frequency of the right ClockDomain without OS / simulated system
involvement, can either be a quick approximation of such a thing, or
modelling a *hardware* DVFS controller.
Hope that helps.
--
Thanks,
Stephan
Stephan Diestelhorst
Staff Engineer
ARM Research - Systems
+44 (0)1223 405662
On Thursday 16 April 2015 16:49:03 Nimish Girdhar wrote:
> Hi Andreas,
>
> "The nice and clean option would be to use add an architecturally visible
> performance counter read from the DVFS governor (in software)."
> Is there any example of any such counter which I can look at to get an idea
> how this will be done??
> On Apr 16, 2015 10:43 AM, "Nimish Girdhar"
> <nimi...@tamu.edu<mailto:nimi...@tamu.edu>> wrote:
> Thanks for the solution Andreas....I will try that.
>
> On Apr 15, 2015 6:29 PM, "Andreas Hansson"
> <andreas.hans...@arm.com<mailto:andreas.hans...@arm.com>> wrote:
Hi all,
>
> The nice and clean option would be to use add an architecturally visible
> performance counter read from the DVFS governor (in software).
> The hackish option is to change the clock speed behind the back of the OS,
> by having the DVFSHandler object change the clocks based on e.g. a probe
> point or similar.
> Andreas
>
> From: Nimish Girdhar <nimi...@tamu.edu<mailto:nimi...@tamu.edu>>
> Reply-To: gem5 users mailing list
> <gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Date: Wednesday, 15
> April 2015 20:04
> To: gem5 users mailing list
> <gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Subject: Re:
> [gem5-users] DVFS with self defined policies on gem5
>
> Okay.....Actually I am making the decision of what frequency which core has
> to run, inside the cpu...
> So I guess I have to somehow communicate this to the dvfs handler which
> doesn't look so clean....
> Is there any other way around or hack anybody has done??
>
> On Apr 15, 2015 10:14 AM, "Yahia Benmoussa"
> <yahia.benmou...@gmail.com<mailto:yahia.benmou...@gmail.com>> wrote:
> Hello,
>
> Setting the required frequency in
> /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed should not be in gem5
> sources files. It can be done in a program (written in C, shell script or
> any other language)
and running under Linux in FS mode.
>
> Regards
> Yahia
>
> 2015-04-15 16:55 GMT+02:00 Nimish Girdhar
> <nimi...@tamu.edu<mailto:nimi...@tamu.edu>>:
> Thanks Yahia for sharing that.
>
> Can you explain a bit more as I don't have much experience with that.
>
> Let's say I have some algo to decide the cpu freq in gem5
> SRC/CPU/O3/commit_impl.hh... How can I set the file you mentioned to that
> freq from here??
> Thanks,
>
> On Apr 15, 2015 2:53 AM, "Yahia Benmoussa"
> <yahia.benmou...@gmail.com<mailto:yahia.benmou...@gmail.com>> wrote:
> Hello,
>
> You have to enable userspace governor in your kernel then you can scale the
> CPU frequency by setting
> /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed file. It should
> work.
> Regards.
> Yahia
>
>
> 2015-04-15 4:00 GMT+02:00 Nimish Girdhar
> <nimi...@tamu.edu<mailto:nimi...@tamu.edu>>:
Hello all,
>
> I am working on a project where I have to use DVFS to change the frequency
> of cores based on my evaluation of some counters that I inserted in the
> gem5 o3 cpu src code.
> I followed the guidelines given on
> http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS .
But with these
> steps, the kernel will be the one who decides the performance levels of the
> cores at different point of time. But in my case I want to decide the
> levels based on some counters as mentioned above.
> Has anybody tried anything similar to that? I want to know how can I access
> and update the dvfs handler registers from within the cpu src code.
> Any help will be appreciated.
>
> Thanks,
>
> --
> Warm regards
> Nimish Girdhar
> Department of Electrical and Computer Engineering
> Texas A&M University
>
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