*Hi again*
*I've tried what you told me about the multi-threaded workload like this:*
for i in xrange(np):
p = LiveProcess()
p.cmd = ['/home/anoir/m5threads/lock_test/test_lock']
system.cpu[i].workload = p
system.cpu[i].createThreads()
*but i get this error message:*Beginning si
Thank you, Jason,
you are a saver
On Wed, Oct 26, 2016 at 12:15 AM, Jason Lowe-Power
wrote:
> Hi Anoir,
>
> You can also look at this script: https://github.com/
> powerjg/gem5/blob/devel/simplefs/configs/myconfigs/system/caches.py
>
> It should be very simple to do what you're suggesting. You j
Hi Anoir,
You can also look at this script:
https://github.com/powerjg/gem5/blob/devel/simplefs/configs/myconfigs/system/caches.py
It should be very simple to do what you're suggesting. You just need to
create the cache and crossbar objects and hook them up. Pretty much any
topology you can think
Hi Anouar,
I've never tried to use the checker CPU myself, so I can't tell you exactly
what's wrong. Have you used gdb to find out where the error is occuring? I
assume it's a null pointer dereference. So what object isn't allocated that
should be?
Jason
On Fri, Oct 21, 2016 at 10:16 AM anoir ne
I agree with Alex: the ISA description system was designed for Alpha, and
it remains the purest example of how it was intended to be used, so I think
there's some value in keeping it around for that.
To me, it should boil down to a cost/benefit consideration. I agree that
the benefits are not that
Hi Andreas,
Not sure I understand this decision/proposal. Certainly, there are some ISAs in
the current repo which are not used or maintained by anyone. This might render
them good candidates for removal. However, ALPHA is quite a big exception in my
mind.
Surely, very few people are using ALP
Hey Ashkan,
The ITB and the DTB are the TLBs for the instruction and data accesses
respectively. The ITB port is the port hooking up the ITB to the CPU.
I am unable to trigger the assertion you saw when I tried this out myself.
What revision of gem5 are you on? I would suggest trying again with t
Hi All,
I am trying to run a dual system simulation with ARM64 in FS mode. I use the
following command
./build/ARM/gem5.fast -d dual_sys configs/example/fs.py --kernel=vmlinux
--machine-type=VExpress_GEM5_V1
--dtb-file=/home/yqureshi/gem5_16/system/arm/dt/armv8_gem5_v1_1cpu.dtb
--disk-image
Hi all,
I would like to simulate an armv7 big.LITTLE platform. However, the
big.LITTLE dts in system/arm/dt is for an armv8 platform. If I manually
change armv8 by armv7, the model name and the compatibility, is it
representative of an armv7 big.LITTLE SoC ?
Thanks.
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