[gem5-users] reg router configuration

Hello, I wish to add additional router parameters inside each router. Please tell us under which file we must add that? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Creating Blocking caches (i.e., 1 target per MSHR)

(There was a typo in previous mail) Hello Nikos and Everyone, In src/mem/cache/cache.cc for function handleTimingReqMiss(), we only check if there is an existing mshr entry corresponding to Miss Request. And then we call *BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time,

Re: [gem5-users] Creating Blocking caches (i.e., 1 target per MSHR)

Hello Nikos and Everyone, In src/mem/cache/cache.cc for function handleTimingReqMiss(), we only check if there is an existing mshr entry corresponding to Miss Request. And then we call *BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time, request_time);* In

[gem5-users] Switching off AVX-512 for running SPEC 2017 in SE mode

Hello, I want to run the SPEC 2017 workloads in SE mode(X86), but when I do many of them run into an error about an unrecognised instruction. After some search I found this thread in the list : https://gem5-users.gem5.narkive.com/jO22f7kV/spec2017-on-gem5-se-mode where there was described

Re: [gem5-users] Creating Blocking caches (i.e., 1 target per MSHR)

I want to have just 1 target per cache line in MHSR queue ie., one target per MSHR entry, but if I set parameter tgt_per_mshr to be 1, I get the number of blocked cycles to zero i.e, there is no blocking due to full targets. If we see the allocateMissBuffer calls code in base.cc and base.hh, the

Re: [gem5-users] Creating Blocking caches (i.e., 1 target per MSHR)

Hi Abishek, A single MSHR can keep track of more than one requests for a given cache line. If you set tgts_per_mshr to 1, then the MSHR will only be able to keep track of a single request for any given cache line. But it can still service requests to other cache lines by allocating more MSHRs.

Re: [gem5-users] ValueError in Garnet_standalone

Yesss! It worked :) On Mon, Mar 25, 2019 at 10:17 AM Gambord, Ryan wrote: > I believe I've found the commit that broke this. Try rebasing and removing > this commit and see if it works for you. It did for me. > > >

[gem5-users] Creating Blocking caches (i.e., 1 target per MSHR)

Hello Everyone, I am trying to simulate D-cache with one target per mshr, I tried changing the parameter "tgts_per_mshr" defined in "configs/common/Caches.py" to 1, it does not work. This is because when we allocate target for existing MSHR, we always check the "tgts_per_mshr" parameter after

[gem5-users] m5threads: look for address on a different bus

Hi all, My configuration has 2 CPUs, one of which has a local memory.   cpu0  cpu1   |    |   |  X --- Local Memory   |    |           __