[gem5-users] simulate() limit problem when I'm running openmp benchmarks on gem5

Hi all, I have compiled openmp benchmarks using m5threads. command lines are as follow: "./build/X86/gem5.opt configs/example/se.py -n 4 -c ../m5threads/tests/test_omp -o '2 2' --caches --l2cache --l1d_size=128kB --l1i_size=128kB --l2_size=1MB --l1d_assoc=2 --l1i_assoc=2 --l2_assoc=1

[gem5-users] Full-system experiments with MOESI AMD Base Protocol

Hi Everyone, I'm wondering if anyone has used the MOESI AMD Base protocol to run full-system experiments? For the DMA controller, I used the implementation from GCN3 staging branch but my experiments encounter live-locks

Re: [gem5-users] Compressor

Hello Pooneh, There is currently no support for compressed L1 caches (and there is no plan to add, since it would require great modifications to the caches), therefore if you setup the configuration in src/mem/cache/Cache.py it is going to break it (it sets for all caches, including L1). What

Re: [gem5-users] Update an architectural register on eviction from dCache

Has anyone used Model Specific register in caches? That is, to set single bit value in any of the MSR from caches? Best regards, Abhishek On Wed, May 15, 2019 at 2:54 PM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hello Everyone and Gabe, > > I am having difficulty in finding a