Re: [gem5-users] x64 support on Gem5

Thanks Ayaz, I am noticing that other ISAs have this file but X86 doesnt have it ./arch/alpha/isa/branch.isa ./arch/arm/isa/formats/branch.isa ./arch/arm/isa/insts/branch.isa ./arch/arm/isa/templates/branch.isa ./arch/mips/isa/formats/branch.isa ./arch/power/isa/formats/branch.isa

[gem5-users] gem5 GUI Project

Hello gem5 users, I am part of an undergraduate student group working under Jason Lowe-Power. Our project is to create a GUI for gem5. Linked below is a requirements document for the project. If anybody has any suggestions or questions, please let us know, we are currently still prototyping right

Re: [gem5-users] RISCV nop executed as c.addi...

Nop is actually with the rd set to x0, and an immediate of 0 indicates an architectural hint, which gem5 doesn't have to my knowledge. That instruction appears to decode to c.addi x0, 0, which should do nothing even though it isn't explicitly decoded as a nop. What are you seeing happening? On

Re: [gem5-users] x64 support on Gem5

Hi Niranjan, Can you give some specific examples of instructions where you find these problems (and what cpu model are you using)? Is this issue on gem5 Jira ( https://gem5.atlassian.net/projects/GEM5/issues/GEM5-338?filter=allopenissues=priority%20DESC) related to branch operation type behavior

[gem5-users] MSHR entry number

Dear All, I wonder how to change the mshr entry number? I use X86 O3 detailed CPU model. I edited the Caches.py, and set the L2 cache mshrs to 20. class L2Cache(Cache): assoc = 8 tag_latency = 12 data_latency = 12 response_latency = 12 mshrs = 20 tgts_per_mshr = 12

Re: [gem5-users] Getting the virtual address of a specific physical address in x86 se mode

Ah! Of course, sorry about that. You have to call the function *after* `m5.instantiate()`. The `m5.instantiate()` function instantiates all of the C++ classes. Only after that can you call C++ functions. Cheers, Jason On Fri, Feb 14, 2020 at 6:09 AM Muhammad Aamir wrote: > Hi Jason, > > thank

Re: [gem5-users] Getting the virtual address of a specific physical address in x86 se mode

Hi Jason, thank you for the answer, I just have one more basic question(which might seem trivial to you), How do I correctly initialize the cxxMethods, as I am continuously receiving errors while initializing the map function, I also created my own simple cxxMethod to check what I was doing and

[gem5-users] x64 support on Gem5

Hello How is the x64 support on Gem5. I am finding that the decoded instructions don’t have their types set, for example branch instructions. Has someone been able to resolve this issue Thanks Niranjan ___ gem5-users mailing list gem5-users@gem5.org

Re: [gem5-users] [gem5-dev] gem5 segfault with DPRINTFs

Please don't cross post on dev/user as it can divide discussion. On Fri, Feb 14, 2020 at 3:32 AM Daniel Gerzhoy wrote: > > Hi all, > > I've added a series of DPRINTFs into the coherence protocol (GPU_VIPER) > and its been working ok, up until this morning when I added a bunch all at > once and