Hi Matt,
The docker image worked for us. Thanks for providing this image and making it
available for use. We were able to run some HIP programs.
Thank you
> On Mar 21, 2020, at 5:43 PM, Anirudh wrote:
>
> Hi Matt,
>
> Thanks for the detailed response and link to the docker image.
>
> I
Sure, just posted it on the JIRA.
Best,
Heng
> On Mar 19, 2020, at 17:42, Giacomo Travaglini
> wrote:
>
> Heng, could you open a bug in JIRA for this?
>
> Many thanks
>
> Giacomo
>
> -Original Message-
> From: gem5-users On Behalf Of HENG ZHUO
> Sent: 19 March 2020 15:42
> To:
Hi,
You can refer Intel manual it gives you complete explanation
Also somewhere in the code I don’t remember exactly but there was a
reference to particular intel manual
Also refer to older mail threads which tell about x86 instruction deciding
On Sun, Mar 22, 2020 at 12:02 PM Anis Peysieux
Hello,
I wonder how the decomposition of macroops in microops were decided for
x86 in gem5 (for example, DIV in div1, div2, div2i, br, divq and divr).
Are there some resources that helped to know which microops are used in
real-world CPU?
Thanks,
Anis.
--
Anis Peysieux
Doctorant -
See
http://www.gem5.org/documentation/general_docs/ruby/garnet-2/
http://www.gem5.org/documentation/general_docs/ruby/garnet_synthetic_traffic/
configs/network/Network.py and configs/example/garnet_synth_traffic.py are the
two config files to look at.
On Mar 22, 2020, 1:42 AM -0400, Mitra M ,
