[gem5-users] Running a program with spin lock under the ARM architecture gets the wrong result

Hi, Recently I ran a program which has spin lock(I did it myself using atomic operations) under ARM architecture on gem5, but I found that the result was not as expected! I ran this program on a physical machine with arm64 and the result is right. Also, I compiled the same source code with

[gem5-users] Page crossing prefetch

Hi, Has anyone looked at enabling page crossing prefetch in Gem5? I see the below code where it says ignoring the page crossing prefetch if the new address is not in the same page. } else { DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n"); } Thanks, Rejith

[gem5-users] Re: how to add more than 1 ide disk in gem5 fullsystem

Hi, I think the config script (system.py) in boot tests on gem5-resources ( https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/boot-exit/configs/) shows how to add two disks in your configuration. Specifically, looking into setDiskImages()might be helpful. -Ayaz On

[gem5-users] Re: Instruction execute stage clock cycles in MinorCPU

Yeah, it does not seem like m5ops are implemented in RISC-V yet. I did not see any RISC-V specific code in "util/m5/src/abi/". One workaround could be to stop simulation at a particular instruction count (e.g. if you know at what instruction number your function of interest starts and ends) from