Hi,
I am a graduate student interested in GEM5 simulator and am currently trying to
carry out experiments using gem5.\
I compiled VEGA_X86/gem5.opt using gcn-gpu images on source gem5-v22.0.0, but
it only seems to support VEGA10 (gfx900,gfx902), so my first question is, Does
gem5 now support
Hi Sebastian,
I am not aware of an existing example which does what are you looking for.
But, I think the best way to achieve this will be annotating your workloads
using m5 ops (you might have to add special m5 ops to recognize what
workload finished) to move control from the simulated system to
Hi Haseung
On 06/03/2023 11:47, 봉하승 wrote:
Hi Giacomo,
Got it, thanks for your reply.
Can you tell me what architecture or processor the default ARM configuration
used in gem5'O3CPU is based on?
The O3CPU is ISA agnostic, so it is not Arm specific. The architecture under
use is defined by
Hi Giacomo,
Got it, thanks for your reply.
Can you tell me what architecture or processor the default ARM
configuration used in gem5'O3CPU is based on?
Regards
Hasueng
2023년 3월 6일 (월) 오후 7:01, Giacomo Travaglini 님이
작성:
> Hi Haseung,
>
>
>
> In Arm FP registers share the same storage with
Hi Haseung,
In Arm FP registers share the same storage with SIMD (Vector) registers, so we
usually refer to them as SIMD registers.
This is why in gem5 we don’t use the floating point register type and we use
the vector type only
Kind Regards
Giacomo
From: 봉하승 via gem5-users
Reply to: The
