Right now my controller object just intended to work as wrapper for icache
( when I could ensure that I could take request from cpu and send it to
icache and vice versa, I'll start working on my main target).
my simple script:
> ## import librarie
# Parameters ##
>
> #Memory
>
Hi Shaikhul,
I think that you have somehow unset the `assoc` parameter (or set it to
None) in the cache. Can you provide us the exact script you're running, the
command line that you use to run, the information about the gem5 build
(variant used), the version of gem5 you're using, and any modifica
Hi Anoop,
I'm glad that increasing -n helped. It's hard to say what exactly the
problem is without digging in further, but often the ROCm stack will launch
additional processes to do a variety of things (e.g., check which version
of LLVM is being used). In gem5, each of these require a separate
Hi Chathura,
I don’t know the other ISAs, but Arm supports an IOMMU (SMMU in Arm
terminology):
https://github.com/gem5/gem5/blob/stable/src/dev/arm/RealView.py#L1475
Kind Regards
Giacomo
From: Chathura Rajapaksha via gem5-users
Date: Thursday, 17 August 2023 at 14:28
To: gem5-users@gem5.org
Hi All,
I am looking into simulating a system with an IOMMU.
I could not find any details about IOMMU in the official documentation.
Is there support for IOMMU in full system simulation (for x86, Arm or RISC-V)?
If not, are there any known open-source projects that provide this
functionality to GE
