Hi all,
I'm looking for a way to count the total number of dirty/clean blocks
within the cache hierarchy to get an overall ratio from each cache
simulated. So far I haven't had much luck in finding a straightforward way
to do this other than running through the cache/base.cc file and manually
Hi,
The files you want to look at for the memory access are src/mem/
dram_ctrl.cc/.hh and src/mem/DRAMCtrl.py for issuing requests from the
memory controller. The memory access itself is performed in
DRAMCtrl::accessAndRespond, with a call to access() which is defined in
src/mem/abstract_mem.cc.
Hello all,
I'm running a single core X86 o3 sim with SPEC2006 benchmarks, and have run
into a scenario where some of the benchmarks are terminating early. Using
the "DRAM" debug flag, I see this message upon termination:
Exiting @ tick 67067500 because exiting with last active thread context
los Silva Junior
> Phd Student
>
> ----------
> *De:* Alex Freij via gem5-users
> *Enviado:* quinta-feira, 7 de maio de 2020 11:31
> *Para:* gem5-users@gem5.org
> *Cc:* Alex Freij
> *Assunto:* [gem5-users] Adding new source files
>
> Hi all,
>
> I'm trying to understand how to
Hi all,
I'm trying to understand how to add source files to the gem5 project
without the need to create a SimObject. I've added `Source('myFile.cc')`
into the respective SConscript file, but when I try to build I get this
message:
scons: *** [build/X86/sim/myFile.o] Source
