Has someone managed to do an ARM64 full system simulation of SPEC2k17? I’m
attempting to bring it up and the only tutorials I see are x86 using KVM CPU.
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I’m interested in using Gem5’s O3 model but I’m trying to model the A55 CPU
(since that’s what we use in silicon).
I know there’s previous work getting the O3 model configuration to correlate
with Cortex A9. Has anyone done work on more recent ARM processors like the
A76(or A77/A78) and the
you can convert from the port interface to
the AXI, then it should "just work". Note that there are also already bindings
to SystemC/TLM in gem5 as well that could serve as good examples.
Cheers,
Jason
On Wed, Apr 26, 2023 at 11:44 AM Jonathan Kang via gem5-users
mailto:gem5-users@
port. If you can convert from the port interface to
the AXI, then it should "just work". Note that there are also already bindings
to SystemC/TLM in gem5 as well that could serve as good examples.
Cheers,
Jason
On Wed, Apr 26, 2023 at 11:44 AM Jonathan Kang via gem5-users
mailto:
I’m looking to integrate a Gem5 full system model with some of our internal IP.
The IP and memory (caches) will be memory mapped. So I’d like it if the Gem5
full system could handle some parts of the system (file IO, system calls) but
route requests to certain memory address regions to an
I’m trying to compile the ARM gem5 model:
# python3 /usr/bin/scons build/ARM/gem5.opt
However, I’m getting this error:
{standard input}: Assembler messages:
{standard input}:135661: Warning: end of file not at end of a line; newline
inserted
{standard input}:135860: Error: unknown pseudo-op:
;mailto:mos...@meta.com>
Subject: Re: [gem5-users] Capturing SimPoint and running on ARM CycleModel
Hi Jonathan On 08/03/2023 01: 43, Jonathan Kang via gem5-users wrote: Hi all,
I’m attempting to get SPEC 2k17 to run on our performance model that uses an
ARM Cycle Model (A55). Obviousl
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Hi Jonathan
On 08/03/2023 01:43, Jonathan Kang via gem5-users wrote:
Hi all,
I’m attempting to get SPEC 2k17 to run on our performance model that uses an
ARM Cycle Model (A55). Obviously it’d take forever to run the whole binary so I
was wondering if anyone has had experience
Travaglini
Date: Wednesday, March 8, 2023 at 6:26 AM
To: The gem5 Users mailing list
Cc: Jonathan Kang
Subject: Re: [gem5-users] Capturing SimPoint and running on ARM CycleModel
Hi Jonathan On 08/03/2023 01: 43, Jonathan Kang via gem5-users wrote: Hi all,
I’m attempting to get SPEC 2k17 to run
Hi all,
I’m attempting to get SPEC 2k17 to run on our performance model that uses an
ARM Cycle Model (A55). Obviously it’d take forever to run the whole binary so I
was wondering if anyone has had experience capturing SimPoints using Gem5 and
then running the resulting reduced binary on a
Yes, you use SimPoint with the “fast” model (something simple, with no timing)
so that the tool knows the activity. It then determines windows of importance
so that you can run only those windows with the cycle accurate model.
From: Markus Bichl via gem5-users
Date: Wednesday, November 9, 2022
code (basically the back-end packet generation)
and write your own front-end (ETM parser) and middle logic.
Let me know what you think about it.
Kind regards,
Giacomo
From: Jonathan Kang via gem5-users
Sent: 13 April 2022 22:17
To: gem5-users@gem5.org
Cc
Hi all,
I’m new to Gem5 (just Googled it) and am interested in TraceCPU. A bit of
background on what I’m trying to achieve:
1. I have a device (Snapdragon) that I am capturing ARM ETM traces on.
2. I’m looking for a way to use a trace-driven CPU model to replay these ARM
traces in my
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