This image can work.
The offset of the image is 65536, not 32256
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%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
of
testers (-t argument) to make it look more like your system.
Nikos
On 21/08/2020 12:50, chenboya via gem5-users wrote:
>
> Hi, ALL
>
> I'm doing some design space exploration work using GEM5.
> My work is exploring the different cache structures, using ARM cores, classic
> cache
Hi, Ciro
Thank you for sharing this.
I saw Jason initiated a code review for Tiago's update last month.
So I guess this work will be added to the main repository soon.
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Hi, ALL
I'm doing some design space exploration work using GEM5.
My work is exploring the different cache structures, using ARM cores, classic
cache structure, and use parsec-3.0 to simulate the multi-core performance.
My system has 4-level caches, every level using L2XBar to connect. Use big
There are some GIC issues about running the KVM mode, fortunately an engineer
had given the solution.
Here are some discussions about the KVM mode for ARM.
https://gem5.atlassian.net/browse/GEM5-547
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