Thank you for providing the valuable source, Just a few more questions
regarding this files and the custom micro-op ISA,
1. the terms "t1,t2,t3" in the files I presume refer to some registers
in x86 architecture, underlying are they referring the "EAX, EBX, ECX
EDX" registers? if yes
Hello,
These are written in a custom micro-op ISA. See
http://new.gem5.org/documentation/general_docs/architecture_support/x86_microop_isa/
for
more details.
Also, I know there's a lot of missing x86 instruction implementations, so
please contribute anything back that you fix! You can find out
Hi everyone,
I am trying to extend the x86 instruction set, and I have come across some
microops written in macrops that are not the typical x86 instructions e.g
rdip limm riprel.
Basically, I am referring to the files located in this directory:
gem5/src/arch/x86/isa/insts
In which
