Thank you for your help!
-Chang Hyun Park
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Hi,
You are right about values of ports not being sensible.
Set the values depending on the architecture (coffee lake, skylake, etc)
Correct values of hardware components can be found in their manual
On Tue, Mar 3, 2020 at 5:32 PM Chang Hyun Park
wrote:
> Thank you, Abhishek for your reply.
>
Thank you, Abhishek for your reply.
(For some reason your mail didn't make it into my inbox).
The reason I brought the question up was because the other parameters
(ROB size, register file size, dispatch width, etc) look like sensible
values, but the cacheLoad/StorePorts just seemed way off.
And
Hi,
The configuration in source code are not decided depending on any specific
architecture.
One needs to change it depending on what architecture they are targeting.
If you read papers who have used gem5, they always target a particular
architecture (skylake, coffee lake, or any and or arm, etc)
Hello all,
I ran into a question while looking through the `cacheLoadPorts` and
`cacheStorePorts` variable in `src/cpu/o3/O3CPU.py`[1].
The default values are set to 200, and a search through GitHub shows
that this default value seems to be always used. (At least for the
provided example
