Re: [gem5-users] What is the default coherence mechanism in gem5 for multicore systems?

2019-12-11 Thread Francisco Carlos
em nome de Giacomo Travaglini Enviado: quarta-feira, 11 de dezembro de 2019 14:02 Para: Abhishek Singh Cc: gem5 users mailing list Assunto: Re: [gem5-users] What is the default coherence mechanism in gem5 for multicore systems? No problem! 🙂 From: Abhishek

Re: [gem5-users] What is the default coherence mechanism in gem5 for multicore systems?

2019-12-11 Thread Giacomo Travaglini
No problem! 🙂 From: Abhishek Singh Sent: 11 December 2019 16:59 To: Giacomo Travaglini Cc: gem5 users mailing list Subject: Re: [gem5-users] What is the default coherence mechanism in gem5 for multicore systems? Thank you for the clarification. On Wed, Dec

Re: [gem5-users] What is the default coherence mechanism in gem5 for multicore systems?

2019-12-11 Thread Abhishek Singh
- > *From:* gem5-users on behalf of Abhishek > Singh > *Sent:* 11 December 2019 16:32 > *To:* gem5 users mailing list > *Subject:* Re: [gem5-users] What is the default coherence mechanism in > gem5 for multicore systems? > > Hi, > The default is MI pr

Re: [gem5-users] What is the default coherence mechanism in gem5 for multicore systems?

2019-12-11 Thread Giacomo Travaglini
the default coherence mechanism in gem5 for multicore systems? Hi, The default is MI protocol in classic cache model, there are various protocols which you can find in build_opts directory. Also, you can find the build info by using —build-info flag. For example ./build/X86/gem5.opt —build-info

Re: [gem5-users] What is the default coherence mechanism in gem5 for multicore systems?

2019-12-11 Thread Abhishek Singh
Hi, The default is MI protocol in classic cache model, there are various protocols which you can find in build_opts directory. Also, you can find the build info by using —build-info flag. For example ./build/X86/gem5.opt —build-info On Wed, Dec 11, 2019 at 10:11 AM Francisco Carlos wrote: > Hi a

[gem5-users] What is the default coherence mechanism in gem5 for multicore systems?

2019-12-11 Thread Francisco Carlos
Hi all, I am currently running simulation in a multicore processor. I connect the memory system as follow: for i in range(np): system.cpu[i].icache = L1_ICache() system.cpu[i].dcache = L1_DCache() system.cpu[i].icache.connectCPU(system.cpu[i]) system.cpu[i].dcache.connectCPU(syst